JPH0244443U - - Google Patents
Info
- Publication number
- JPH0244443U JPH0244443U JP1988122922U JP12292288U JPH0244443U JP H0244443 U JPH0244443 U JP H0244443U JP 1988122922 U JP1988122922 U JP 1988122922U JP 12292288 U JP12292288 U JP 12292288U JP H0244443 U JPH0244443 U JP H0244443U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- low frequency
- clock signal
- generating means
- frequency clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 claims description 6
- 238000001228 spectrum Methods 0.000 claims 2
- 230000000630 rising effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Synchronisation In Digital Transmission Systems (AREA)
Description
第１図は本考案要部の一実施例を示す図、第２
図は従来例を示す図、第３図は符号位相の相対変
化を示す図である。
１１……第１検出回路、１２……第２検出回路
、１３……第１ゲート回路、１４……第２ゲート
回路、１５……アツプダウンカウンタ、１６……
プログラマブル分周器。
Fig. 1 is a diagram showing an embodiment of the main part of the present invention;
The figure shows a conventional example, and FIG. 3 shows a relative change in code phase. 11...First detection circuit, 12...Second detection circuit, 13...First gate circuit, 14...Second gate circuit, 15...Up-down counter, 16...
Programmable frequency divider.
Claims (1)
生手段と、この低周波クロツク信号発生手段から
の低周波クロツク信号に応じて前記高周波信号発
生手段からの高周波信号の位相を調整する位相調
整手段と、この位相調整手段からの出力信号に基
づき符号を発生する符号発生手段と、この符号発
生手段からの符号とスペクトラム拡散信号とを乗
算する第１乗算手段と、この第１乗算手段の出力
信号のエンベロープ成分と前記低周波クロツク信
号とを乗算し、その出力信号を制御信号として高
周波信号発生手段に供給する第２乗算手段とを備
えたスペクトラム拡散信号復調回路であつて、前
記位相調整手段が前記高周波信号を入力とするプ
ログラマブル分周器と、前記低周波クロツク信号
の立上りを検出する第１検出回路と、前記低周波
クロツク信号の立下りを検出する第２検出回路と
、第１及び第２検出回路からの検出信号に基づき
前記プログラマブル分周器に設定される分周比を
制御する分周比設定回路とより構成されているこ
とを特徴とするスペクトラム拡散信号復調回路。 a high frequency signal generating means; a low frequency clock signal generating means; a phase adjusting means for adjusting the phase of the high frequency signal from the high frequency signal generating means in accordance with the low frequency clock signal from the low frequency clock signal generating means; code generation means for generating a code based on the output signal from the phase adjustment means; first multiplication means for multiplying the code from the code generation means by a spread spectrum signal; and an envelope component of the output signal of the first multiplication means. and a second multiplier for multiplying the output signal by the low frequency clock signal and supplying the output signal to the high frequency signal generating means as a control signal, the phase adjusting means a programmable frequency divider that receives as an input, a first detection circuit that detects a rising edge of the low frequency clock signal, a second detection circuit that detects a falling edge of the low frequency clock signal, and first and second detection circuits. A spread spectrum signal demodulation circuit comprising: a frequency division ratio setting circuit that controls a frequency division ratio set in the programmable frequency divider based on a detection signal from the programmable frequency divider.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988122922U JPH066639Y2 (en) | 1988-09-20 | 1988-09-20 | Spread spectrum signal demodulation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988122922U JPH066639Y2 (en) | 1988-09-20 | 1988-09-20 | Spread spectrum signal demodulation circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0244443U true JPH0244443U (en) | 1990-03-27 |
| JPH066639Y2 JPH066639Y2 (en) | 1994-02-16 |
Family
ID=31371306
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988122922U Expired - Lifetime JPH066639Y2 (en) | 1988-09-20 | 1988-09-20 | Spread spectrum signal demodulation circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH066639Y2 (en) |
-
1988
- 1988-09-20 JP JP1988122922U patent/JPH066639Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH066639Y2 (en) | 1994-02-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0244443U (en) | ||
| JPS5661833A (en) | Phase synchronous oscillating circuit | |
| JPS6455911A (en) | Frequency synthesizer | |
| JPH0321076Y2 (en) | ||
| JPH0210637U (en) | ||
| JPH0763146B2 (en) | Standby circuit | |
| JPH01180833U (en) | ||
| JPH0325924U (en) | ||
| JPH01177616U (en) | ||
| JPH0475469U (en) | ||
| JPH0466746U (en) | ||
| JPS5830341U (en) | PLL circuit | |
| JPS59104636U (en) | frequency synthesizer | |
| JPS6249336U (en) | ||
| JPS62159029U (en) | ||
| JPS623125U (en) | ||
| JPS6314170U (en) | ||
| JPS5587986A (en) | Electronic watch system | |
| JPS63114505U (en) | ||
| JPS59100351U (en) | Processor synchronous control circuit | |
| JPS58164342U (en) | frequency synthesizer | |
| JPH0181037U (en) | ||
| JPS56158549A (en) | Pusedo random noise pulse train synchronizing circuit | |
| JPS57162839A (en) | Direct variable type freuquency division circuit | |
| JPS5843044U (en) | frequency synthesizer |