JPH0243635A - Address tracer - Google Patents

Address tracer

Info

Publication number
JPH0243635A
JPH0243635A JP63195518A JP19551888A JPH0243635A JP H0243635 A JPH0243635 A JP H0243635A JP 63195518 A JP63195518 A JP 63195518A JP 19551888 A JP19551888 A JP 19551888A JP H0243635 A JPH0243635 A JP H0243635A
Authority
JP
Japan
Prior art keywords
firmware
execution
address
storing
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63195518A
Other languages
Japanese (ja)
Inventor
Tsuneo Fujiwara
藤原　常雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63195518A priority Critical patent/JPH0243635A/en
Publication of JPH0243635A publication Critical patent/JPH0243635A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To know the locus of the execution of a firmware for a long time with a small hardware quantity by providing a firmware executing address storing circuit, a storing instruction control circuit controlled by the firmware and a storing instruction enable signal. CONSTITUTION:The address tracer provides a firmware execution address storing circuit 10 to store an execution address 1 of the firmware and a storing instruction control circuit 20 to generate a storing instruction enable signal 3 to control the interval of the execution address storing by the instruction of the firmware for a firmware executing address storing circuit 10. The instruction is executed to the storing instruction control circuit with the firmware and in the execution interval of a successive or arbitrary firmware, the control of the storing of the execution address of the firmware is executed. Thus, the locus of the execution of the firmware can be known by a small hardware quantity.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はアドレストレーサに関し、特に情報処理装置の
ファームウェアの実行アンレスのトレースに関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address tracer, and particularly to tracing of execution unresponsiveness of firmware of an information processing device.

〔従来の技術〕[Conventional technology]

従来、ファームウェアにより制御されるプロセッサを持
つ情報処理装置において、ファームウェア実行アドレス
を記憶するアドレストレーサは、ファームウェア実行ア
ドレスを順次に記憶していた。Conventionally, in an information processing device having a processor controlled by firmware, an address tracer that stores firmware execution addresses sequentially stores the firmware execution addresses.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、上述した従来のアドレストレーサでは、ファー
ムウェアの実行アドレスを記憶する記憶回路のハードウ
ェア量により記憶容量が限定されてしまい、ファームウ
ェアの実行の軌跡が狭い範囲でしか知ることができない
という欠点がある。However, the above-mentioned conventional address tracer has the disadvantage that its storage capacity is limited by the amount of hardware in the storage circuit that stores the firmware execution address, and the trajectory of firmware execution can only be known within a narrow range. .

〔課題を解決するための手段〕[Means to solve the problem]

本発明のアドレストレーサの構成は、ファームウェアに
より制御されるプロセッサを有する情報処理装置におい
て、前記ファームウェアの実行アドレスを記憶するファ
ームウェア実行アドレス記憶回路と、該ファームウェア
実行アドレス記憶回路に対し、前記ファームウェアの指
示によりその実行アドレス記憶の間隔を制御する記憶指
示イネーブル信号を発生する記憶指示制御回路とを具備
し、前記ファームウェアが前記記憶指示制御回路に対し
指示を出して順次又は任意のファームウェアの実行間隔
においてこのファームウェアの実行アドレスの記憶の制
御を行う事を特徴とする。The configuration of the address tracer of the present invention is such that, in an information processing apparatus having a processor controlled by firmware, a firmware execution address storage circuit that stores an execution address of the firmware, and an instruction of the firmware to the firmware execution address storage circuit are provided. and a storage instruction control circuit that generates a storage instruction enable signal for controlling the execution address storage interval, and the firmware issues an instruction to the storage instruction control circuit to perform this operation sequentially or at an arbitrary firmware execution interval. It is characterized by controlling the storage of firmware execution addresses.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の一実施例のブロック図、第２図は第１
図の各信号のタイミングチャートである。FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
3 is a timing chart of each signal in the figure.

第１図で、１０はファームウェア実行アドレス記憶回路
、２０は記憶指示制御回路、１はファームウェア実行ア
ドレス（ＡＤＲ）　、２はファームウェア実行うロック
（ＣＬＫ）、３は記憶指示イネーブル信号（ＥＮＢ）、
４は記憶指示切り換え信号（ＣＨＧ）である。In FIG. 1, 10 is a firmware execution address storage circuit, 20 is a storage instruction control circuit, 1 is a firmware execution address (ADR), 2 is a firmware execution lock (CLK), 3 is a storage instruction enable signal (ENB),
4 is a storage instruction switching signal (CHG).

ファームウェア実行アドレス記憶回路１０は、ファーム
ウェア実行アドレス（ＡＤＲ）１をファームウェア実行
うロック（ＣＬＫ）２及び記憶指示イネーブル信号（Ｅ
ＮＢ）３により記憶する（第２図（１）〜（３））。The firmware execution address storage circuit 10 has a lock (CLK) 2 for executing firmware execution address (ADR) 1 and a storage instruction enable signal (E).
NB) 3 (FIG. 2 (1) to (3)).

ファームウェアは記憶指示切り換え信号（ＣＨＧ）４を
用いて記憶指示制御回路２０に指示を出すことにより、
記憶指示イネーブル信号（ＥＮＢ）３を順次（第２図り
３）又は１実行間隔（第２図（４））又は任意の間隔を
おいて（第２図（５）〜（６））出力し、ファームウェ
ア実行アドレス（ＡＤＲ）１をファームウェア実行アド
レス記憶回路１０に記憶する。The firmware issues an instruction to the storage instruction control circuit 20 using the storage instruction switching signal (CHG) 4 to
Outputs the storage instruction enable signal (ENB) 3 sequentially (second diagram 3) or at one execution interval (FIG. 2 (4)) or at arbitrary intervals (FIG. 2 (5) to (6)); A firmware execution address (ADR) 1 is stored in the firmware execution address storage circuit 10.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ファームウェア実行アド
レス記憶回路と、ファームウェアにより制御される記憶
指示制御回路と、記憶指示イネーブル信号とを有するこ
とにより、ファームウェアの実行アドレスを順次又は任
意の間隔をおいて記憶可能となる為、少ないハードウェ
ア量で、長期間にわたるファームウェアの実行の軌跡を
知ることか可能となる効果がある。As explained above, the present invention includes a firmware execution address storage circuit, a storage instruction control circuit controlled by the firmware, and a storage instruction enable signal, so that execution addresses of firmware can be stored sequentially or at arbitrary intervals. Since it can be stored, it has the effect of making it possible to know the trajectory of firmware execution over a long period of time with a small amount of hardware.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例のブロック図、第２図は第１
図の各信号のタイミングチャートである。 １・・・ファームウェア実行アドレス（ＡＤＲ）、２・
・・ファームウェア実行うロック（ＣＬＫ）、３・・・
記憶指示イネーブル信号（ＥＮＢ）、４・・・記憶指示
切り換え信号（ＣＨＧ）、１０・・・ファームウェア実
行アドレス記憶回路、２０・・・記憶指示制御回路。FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
3 is a timing chart of each signal in the figure. 1...Firmware execution address (ADR), 2...
...Firmware execution lock (CLK), 3...
Storage instruction enable signal (ENB), 4... Storage instruction switching signal (CHG), 10... Firmware execution address storage circuit, 20... Storage instruction control circuit.

Claims (1)

【特許請求の範囲】[Claims] ファームウェアにより制御されるプロセッサを有する情
報処理装置において、前記ファームウェアの実行アドレ
スを記憶するファームウェア実行アドレス記憶回路と、
該ファームウェア実行アドレス記憶回路に対し、前記フ
ァームウェアの指示によりその実行アドレス記憶の間隔
を制御する記憶指示イネーブル信号を発生する記憶指示
制御回路とを具備し、前記ファームウェアが前記記憶指
示制御回路に対し指示を出して順次又は任意のファーム
ウェアの実行間隔においてこのファームウェアの実行ア
ドレスの記憶の制御を行う事を特徴とするアドレストレ
ーサ。In an information processing device having a processor controlled by firmware, a firmware execution address storage circuit that stores an execution address of the firmware;
The firmware execution address storage circuit is further provided with a storage instruction control circuit that generates a storage instruction enable signal for controlling the execution address storage interval according to instructions from the firmware, and the firmware instructs the storage instruction control circuit. 1. An address tracer that controls storage of execution addresses of firmware sequentially or at arbitrary firmware execution intervals.
JP63195518A 1988-08-04 1988-08-04 Address tracer Pending JPH0243635A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63195518A JPH0243635A (en) 1988-08-04 1988-08-04 Address tracer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63195518A JPH0243635A (en) 1988-08-04 1988-08-04 Address tracer

Publications (1)

Publication Number Publication Date
JPH0243635A true JPH0243635A (en) 1990-02-14

Family

ID=16342418

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63195518A Pending JPH0243635A (en) 1988-08-04 1988-08-04 Address tracer

Country Status (1)

Country Link
JP (1) JPH0243635A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1059558A4 (en) * 1998-03-03 2004-06-23 Sharp Kk Method of scattering fine particles, method of manufacturing liquid crystal display, apparatus for scattering fine particles, and liquid crystal display

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1059558A4 (en) * 1998-03-03 2004-06-23 Sharp Kk Method of scattering fine particles, method of manufacturing liquid crystal display, apparatus for scattering fine particles, and liquid crystal display

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