JPH0240961A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a device wherein characteristics of a thin film transistor is excellent and the generation of failures is little in a manufacturing process, by forming a gate insulating film of the thin film transistor, of a two-layered silicon nitride whose film properties are different with each other. CONSTITUTION:A chromium gate electrode 12 is formed on a glass substrate 11. Silicon nitride gate insulating films 13a, 13b, an amorphous silicon semiconductor layer 14, and amorphous silicon semiconductor layers 15a, 15b containing phosphorus are continuously formed in order. In this case, the composition of mixed gas of silane, ammonia, nitrogen and hydrogen, which is used for forming the films 13a, 13b, is made different, thereby reducing the etching speed of the film 13b. By using mixed solution of hydrofluoric acid and nitric acid, the layers 14, 15a, 15b are formed in an island type, and source drain electrodes 16a, 16b are formed. Finally, the layers 15a, 15b left on the layer 14 of a thin film transistor(TFT) channel part are eliminated by using mixed solution of hydrofluoric acid and nitric acid. Since the film 13a is etched very little, a TFT having no failures such as corrosion, disconnection, and short-circuiting of an electrode 12 can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to semiconductor devices, particularly thin film transistors (hereinafter referred to as TP) for constructing image display devices in combination with liquid crystals and the like.
It is used between semiconductor devices such as gate insulating films (referred to as T).

Conventional technology FIG. 5 is a sectional view of the main parts of a conventional TPT.

A gate electrode 2 made of, for example, chromium is formed on a glass substrate l, an amorphous silicon semiconductor layer 4 is formed via a silicon nitride gate insulating film 3, and source and drain electrodes 6a and 6b made of aluminum contain phosphorus. It is formed via amorphous silicon semiconductors N5a and 5b.

Next, the manufacturing process of the TPT having the above structure will be briefly explained. First, a chromium gate electrode 2 is placed on a glass substrate 1.
selectively applied. Next, a silicon nitride gate insulating film 3, an amorphous silicon semiconductor layer 4, and an amorphous silicon semiconductor layer 5 containing phosphorus are sequentially deposited over the entire surface by chemical vapor deposition. Thereafter, as shown in FIG. 5, the amorphous silicon semiconductor layer 4 and the phosphorus-containing amorphous silicon semiconductor layer 5 are formed into an island shape. Further, an opening (shown in FIG. 5(b)) is provided in the silicon nitride gate insulating film 3 in order to expose the surface of the gate electrode and make electrical contact with the metal forming the source and drain electrodes. Source, train electrodes 6a, 6
After forming the channel portion b, the phosphorus-containing amorphous silicon semiconductor layer 5 deposited on the amorphous silicon semiconductor layer 4 serving as the channel portion is removed to complete the TPT shown in FIG.

In the TPT having such a conventional structure, the amorphous silicon semiconductor layer 4 and the phosphorus-containing amorphous silicon semiconductor layer 5 are formed into islands in the manufacturing method described above. In the step and the step of removing the phosphorus-containing amorphous silicon semiconductor N5 deposited on the amorphous silicon semiconductor layer 4, a hydrofluoric acid-based etching liquid or an etching gas containing fluorine element is used. However, these etching liquids and etching gases can also etch the silicon nitride gate insulating film.
Corrosion of the gate electrode 2 may occur due to the etching solution penetrating into the pinholes in the silicon nitride gate insulating film during the above process and enlarging the pinholes, or due to the high etching speed of the stepped portion of the silicon nitride film caused by the gate electrode 2. , defects such as disconnection or short circuit between the gate electrode 2 and the source and drain electrodes 6 are likely to occur.

Furthermore, since the shape of the above-mentioned opening is steep, cracks occur in the metal that comes in contact with the hole, resulting in defects in which electrical connection cannot be obtained.

On the other hand, in order to prevent the above-mentioned defects, it is desirable to use silicon nitride as the gate insulating film, which has an extremely low etching rate with respect to a hydrofluoric acid-based etching solution or an etching gas containing elemental fluorine. However, silicon nitride, which has a low etching rate, has a composition in which the silicon component is higher than the stoichiometric ratio, or the composition ratio is close to the stoichiometric ratio but the density is large, so the inherent stress of silicon nitride is extremely high. It may be stress.

When silicon nitride, which has a large silicon content, is used for the gate insulating film, the change in the threshold voltage of the TPT over time becomes very large, resulting in very poor reliability. Furthermore, when a large compressive stress was applied to the gate insulating film, the amorphous silicon semiconductor layer peeled off, resulting in a defect in which the TPT did not operate.

The present invention was invented in view of the problems of the prior art, and by forming the gate insulating film with two layers of silicon nitride of different film quality, it exhibits good TPT characteristics and is free from defects in the manufacturing process. The purpose is to provide a semiconductor device that does not

Means for Solving the Problems The present invention forms a silicon nitride film with an extremely low etching rate on the gate electrode, and on top of that a silicon nitride film with a relatively higher etching rate than the former silicon nitride film and a good TP.
The present invention is characterized by a two-layer gate insulating film formed of a conventional silicon nitride film that provides T characteristics.

In terms of operational TPT characteristics, the characteristics of the interface between the amorphous silicon semiconductor layer and the silicon nitride film are important, and are largely influenced by the quality of the silicon nitride film. In the present invention, the silicon nitride film in contact with the amorphous silicon semiconductor layer is formed of a conventional silicon nitride film that has good interface characteristics, so it exhibits good TPT operating characteristics and has a small change in threshold value over time. TPT is obtained. By forming the silicon nitride in contact with the gate electrode, which does not have a large effect on the TPT characteristics, with a film with an extremely low etching rate, the silicon nitride film in contact with the amorphous silicon semiconductor layer in the T and FT manufacturing process can be easily etched. Even if the etching solution enters through pinholes, etc., the silicon nitride in contact with the gate electrode is hardly etched, and the etching rate is slow; in other words, the silicon nitride film, which has become compressively stressed due to high density, has a lower etching rate at the stepped portion. Therefore, defects such as corrosion of the gate electrode and short circuit between the gate electrode and the source and drain electrodes can be suppressed. In addition, since the inherent stress of the conventional silicon nitride film in contact with the amorphous silicon semiconductor layer is very small or tensile stress, the compressive stress of the silicon nitride film in contact with the gate electrode can be alleviated. It can prevent layer peeling.

Furthermore, since the etching rate of silicon nitride in contact with the semiconductor layer side is higher than that with the gate electrode side, the diameter of the opening in the silicon nitride for obtaining electrical contact with the gate electrode is larger on the semiconductor layer side. Therefore, the shape becomes gentle and it is possible to prevent cracks from forming in the metal used for electrical contact.

Example· Examples of the present invention will be described below.

FIG. 1(a) shows a sectional view of a main part of a TPT which is an embodiment of the present invention. 11 is a glass substrate, 12 is a gate electrode made of chromium (film thickness 1000XIO-8011), 13a
is the first silicon nitride gate insulating film (film thickness 1500XlO
-'eWI), 13b is the second silicon nitride gate insulating film (1500XIO-8[!W+), 14 is the amorphous silicon semiconductor layer (100OXIO-8cm), 15a, 15
b is an amorphous silicon semiconductor layer containing phosphorus (500×1
0-8 cm), 16a, and 16b are source and drain electrodes (7000×10-'am) made of aluminum. Here, the first silicon nitride gate insulating film 13a,
Etching solution for the second silicon nitride gate insulating film 13b (
Each etching rate for hydrofluoric acid: ammonium fluoride = 1:6) was 50 x 10-8L? III/
5eC1380×10-81/see.

Next, a method for manufacturing this TPT will be explained.

First, a chromium gate electrode 12 is formed on a glass substrate 11. Subsequently, the first silicon nitride gate insulating film 13a, the second silicon nitride gate insulating film 13b, the amorphous silicon semiconductor layer 14, and the amorphous silicon semiconductor layer 15 containing phosphorus were formed using glow discharge at a frequency of 13.56 MHz. Continuously formed by chemical vapor deposition method.

Here, when forming the first silicon nitride gate insulating film 13a and the second silicon nitride gate insulating film 13b, silane 5
A mixed gas of iHa-ammonia NH3-nitrogen N2-hydrogen H2 is used, but of this mixed gas, nitrogen N2 and hydrogen H2
The relationship between the composition ratio H2/(N2+H2) of 2 and the etching rate is as shown in FIG. Therefore, when forming the first silicon nitride gate insulating film 13a, the composition ratio H2/
(N2+H2) is 0.3, and when forming the second silicon nitride gate insulating film 13b, the composition ratio H2/(N2 +
Set H2) to 1.0. As a result, silicon nitride gate insulating films 13a and 13b having the above-mentioned etching speed can be formed.

Subsequently, the formed amorphous silicon semiconductor N14 and the phosphorus-containing amorphous silicon semiconductor layer 15 are made into island shapes using a mixed solution of hydrofluoric acid and nitric acid. After that, source and drain electrodes 1
6a and 16b, and finally, the amorphous silicon semiconductor layer 15 containing phosphorus remaining on the amorphous silicon semiconductor layer 14 in the TPT channel portion is removed using a mixed solution of hydrofluoric acid and nitric acid. TPT according to the present invention is completed.

According to this embodiment, the amorphous silicon semiconductor layer 14 and the phosphorus-containing amorphous silicon semiconductor layer 15 are formed in an island shape and a TFT.
Most of the first silicon nitride gate insulating film 13a is removed by a mixed solution of hydrofluoric acid and nitric acid used when removing the amorphous silicon semiconductor layer 15 containing phosphorus remaining on the amorphous silicon semiconductor layer 14 in the channel region. Since it is not etched, the gate electrode 12 may be corroded or cut, or the gate electrode 1
Accordingly, it is possible to manufacture a TPT free from defects such as short circuits between the electrodes 2 and the source and drain electrodes 16a and 16b.

In addition, since the shape of the opening in the silicon nitride for making electrical contact with the gate electrode 12 has a gentle shape as shown in FIG. 1(b), cracks occur in the metal for making electrical contact. Therefore, defects such as failure to obtain electrical connection with the gate electrode 12 can be prevented.

Furthermore, it also has the following effects.

Figure 4 shows TPT characteristics (drain current-gate voltage curve) A of this embodiment, conventional example B, and gate insulating film 3000X.
The TPT characteristics of C are shown when 10-8 cyn is formed under the same conditions as the first silicon nitride gate insulating film. If a gate insulating film of 3000XIO-8cm is formed under the same conditions as the first silicon nitride gate insulating film, the above-mentioned defects will not occur, but as shown in FIG.
T characteristics deteriorate. The cause of this deterioration is that the amorphous silicon semiconductor layer has peeled off.

On the other hand, the TPT characteristics of this embodiment are not much different from those of the conventional example. That is, according to this example, a defect-free TPT can be manufactured without deteriorating the TPT characteristics.

Next, other embodiments of the present invention will be described.

FIG. 2 shows a sectional view of the main part of the TPT of this embodiment. Second
As shown in the figure, the TPT of this embodiment has a silicon nitride film for passivation (thickness: 1000XIO"8ctn) on the amorphous silicon semiconductor layer 24 forming the channel part.
27, and the other configurations are similar to those of the previous embodiment.

A method for manufacturing TPT having this configuration will be explained.

A gate electrode 22 is formed in the same manner as in the previous embodiment. Next, a first silicon nitride gate insulating film 23a, a second silicon nitride gate insulating film 23b, an amorphous silicon semiconductor layer 24, A silicon nitride film 27 for passivation is successively deposited. Note that the first silicon nitride gate insulating film 23a and the second silicon nitride gate insulating film 23b in this embodiment are also the same as the first silicon nitride gate insulating film 13a and the second silicon nitride gate insulating film 1 in the previous embodiment.
Formed under the same conditions as 3b. Subsequently, as shown in FIG. 2, the passivation silicon nitride film 27 is made into an island shape using an etching solution containing hydrofluoric acid and ammonium fluoride in a mixing ratio of 1:6. Next, after forming amorphous silicon semiconductor layers 25a and 25b containing phosphorus on the entire surface, the amorphous silicon semiconductor layer 24 and the amorphous silicon semiconductor layer 25 containing phosphorus are formed.
A and b are made into islands using a mixture of hydrofluoric acid and nitric acid.

After that, source and drain electrodes 26a and 26b are formed,
Finally, the amorphous silicon semiconductor FI 25 containing phosphorus remaining on the passivation silicon nitride film 27 is removed using a mixed solution of hydrofluoric acid and nitric acid to complete the TPT of this embodiment.

According to this embodiment, the passivation film 27 is formed in the channel portion without deteriorating the TPT characteristics or causing defects in the process, as in the previous embodiments.
PT can be produced.

Although the above two embodiments of the present invention were mainly explained using a wet etching method using an etching liquid in the manufacturing process, the present invention has similar effects even when a dry etching method using an etching gas is used.

In addition, as a method of controlling the etching rate of the silicon nitride film, the composition ratio H2/
Although a method of changing (N2+H2) was used, the etching rate can also be controlled by changing the flow rate ratio of 5iHa and NH3, formation temperature, glow discharge power, etc., and similar effects can be obtained.

Effects of the Invention As described above, the present invention provides a TPT gate insulating film with a two-layer structure of silicon nitride of different film quality, that is,
For example, the gate insulating film in contact with amorphous silicon is a silicon nitride film of the same quality as the conventional one, while the gate insulating film in contact with the gate electrode is a nitride film whose etching rate is extremely slow (long etching time) compared to the aforementioned silicon nitride. Use silicon film. By this technical means, it is possible to manufacture a semiconductor device that maintains the conventional TPT characteristics and is free from defects such as gate electrode disconnection and short circuit between the gate electrode and the source and drain electrodes during the manufacturing process.

FIG. 3 is a cross-sectional view of the main part of the device, and shows the composition ratio H in the raw material gas under the formation conditions of the silicon nitride film according to the embodiment of the present invention.
2/ A graph showing the relationship between (N2+H2) and the etching rate of the silicon nitride film. Figure 4 shows the characteristics (drain current-gate voltage curve) of TPT in the embodiment of the present invention, conventional TPT, etc.・Glass substrate, 2... Gate electrode, 3... Silicon nitride gate insulating film, 13a
, 23a...first silicon nitride gate insulating film, 13b
, 23b... second silicon nitride gate insulating film, 4...
- Amorphous silicon semiconductor layer, 5... Amorphous silicon semiconductor layer containing phosphorus, 6a, 6b... Source and drain electrodes, 27... Silicon nitride film for passivation.

Name of agent: Patent attorney Shigetaka Awano (1 person) Figure 1 (a)] - Glass substrate] 2 - - Gate electrode 13a - - Head 1 Gytide silicone case 13b
---Second empty silicone insulating trap 14--Amorphous silicon semiconductor layer 15a, 15b---Phosphorus 1-containing amorphous silicon semiconductor layer 16a, 16b---Source/drain electrode FIG. 2 FIG. 1(b) 2] - Glass substrate 22 - Gate @, @ 23a-m - First silicon nitride gate insulating shell 23b -
-1-O-2-nitrogen concatenate Zekagezukisu 24--G-crystal*':, t-recon semiconductor layer 25a, 25b--phosphorus 1
Amorphous crystalline semiconductor main layers 26a, 26b---'
1-Glass substrate 2--Gate electrode 3-Silicon nitride for passivation Special - Mo4 - Non-quality silicon semiconductor and Genma □□□, 5b - 1L crystal containing phosphorus name Semiconductor layer 6a, 6b --- Source/drain electrode Figure 4 □A --- B Gate voltage (V) Figure 5(b)

Claims (4)

[Claims] (1) A first conductor layer is selectively formed on one main surface of the substrate, and a first non-single crystal semiconductor layer mainly composed of silicon is formed through a multilayer insulating thin film layer that can be etched with the same etching agent. is selectively formed so as to partially overlap with the first conductor layer, and the second conductor layer connects the first conductor layer through a second non-single crystal semiconductor layer mainly composed of silicon containing phosphorus. A semiconductor device formed so as to partially overlap with a non-single crystal semiconductor layer of the multilayer insulating thin film layer, and characterized in that the etching rate of the layer closer to the main surface of the substrate of the multilayer insulating thin film layer is lower. (2) The semiconductor device according to claim 1, wherein the second insulating thin film layer is selectively formed so as to partially overlap with the first non-single crystal semiconductor layer mainly composed of silicon. . (3) The semiconductor device according to claim 1, wherein the main component of the multilayer insulating thin film layer is silicon nitride. (4) The multilayer insulating film layer, the first non-single crystal semiconductor layer, and the second non-single crystal semiconductor layer are formed into a predetermined pattern using an etching solution. semiconductor devices.