JPH0239597A - Forming method for thick film circuit - Google Patents

Forming method for thick film circuit

Info

Publication number
JPH0239597A
JPH0239597A JP18824288A JP18824288A JPH0239597A JP H0239597 A JPH0239597 A JP H0239597A JP 18824288 A JP18824288 A JP 18824288A JP 18824288 A JP18824288 A JP 18824288A JP H0239597 A JPH0239597 A JP H0239597A
Authority
JP
Japan
Prior art keywords
conductor
insulator
forming
thick film
film circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18824288A
Other languages
Japanese (ja)
Inventor
Midori Yanagisawa
柳澤 緑
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Juki Corp
Original Assignee
Juki Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Juki Corp filed Critical Juki Corp
Priority to JP18824288A priority Critical patent/JPH0239597A/en
Publication of JPH0239597A publication Critical patent/JPH0239597A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • H05K3/4667Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders characterized by using an inorganic intermediate insulating layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/09Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092Dispersed materials, e.g. conductive pastes or inks
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding

Abstract

PURPOSE:To form a thick film circuit with high yield by forming a connecting conductor having a thickness substantially corresponding to the step of the edge of a viahole region or an insulator connected to a lower conductor by a direct lithography, and forming an upper conductor for connecting a plurality of connecting conductors by a direct lithography. CONSTITUTION:Lower conductors 83 are formed on a board 42, dried and baked. Then, insulators 82 are formed in a predetermined pattern, dried, and baked. In this case, viaholes 84 for connecting the independent conductor 83 is simultaneously formed. The thickness of the insulator 82 is considerably thicker than that of the conductor 83, and a large step is generated at the edges of the viahole 84 and the insulator 82. Then, a connecting conductor 11 of thickness substantially corresponding to the depth of the viahole 84 is formed at the part of the viahole 84. A connecting conductor 11' is also formed at a position for connecting the conductor 83 at a part having large step of the edge of the insulator 82. After the conductors 11, 11' are formed, they are dried and connected. Then, an upper conductor 81 is so formed by lithography as to connect the conductors 11, 11' formed in the viaholes 84, 84.

Description

【発明の詳細な説明】 [1卒業上の利用分野] 本発明は厚膜回路の形成方法、特に直接描画により導体
、絶縁体の積層からなる厚膜回路を形成する厚膜回路の
形成方法に関するものである。
[Detailed Description of the Invention] [Field of Use after Graduation] The present invention relates to a method for forming a thick film circuit, and particularly to a method for forming a thick film circuit that is formed by direct writing to form a thick film circuit consisting of a laminated layer of conductors and insulators. It is something.

[従来の技術] J!11模回路形成技術は、ハイブリッドICの製造に
用いられている。ハイブリッドICは、厚膜回路を基板
上に形成し、ディスクリートな回路素子をスルーホール
を介してハンダ付けなどによって実装して形成される。
[Prior art] J! The No. 11 simulated circuit formation technique is used in the manufacture of hybrid ICs. A hybrid IC is formed by forming a thick film circuit on a substrate and mounting discrete circuit elements through through holes by soldering or the like.

このようなICは比較的電流容i1)を必要とし、P!
jll!形成技術では回路構成が困難である用途に用い
られている。
Such an IC requires a relatively high current carrying capacity i1) and P!
jll! It is used in applications where circuit configuration is difficult using forming technology.

現在のハイブリー、ドICは、薄膜ICと同様に高密度
化、多層化が要求されており、このため絶縁体をはさん
で複数の導体パターンを何層にも積層する構造となって
おり、同一のパターン平面内で接続することができない
導体パターンどうしを導通させるためのビアホールが必
要となっている。
Like thin-film ICs, current high-density ICs are required to be highly dense and multi-layered, and for this reason, they have a structure in which multiple conductor patterns are laminated in many layers with insulators in between. Via holes are required to connect conductor patterns that cannot be connected within the same pattern plane.

ビアホールは絶縁体の下部に設けられた孤立した導体パ
ターンを接続するために露出させる絶縁体に設けられた
穴である。絶縁体はガラスペーストなどから構成され、
通常的40〜507zmの膜厚で充分な絶縁性を保てる
。ところが、この絶縁体の膜厚は、銀パラジウム、金、
銀などから成る導体の膜厚が10〜20gmであるのに
対してかなり厚く、従って絶縁体を39けるとその縁部
および上記ビアホール部ではかなり大きな段差が生じる
A via hole is a hole provided in an insulator that is exposed to connect an isolated conductor pattern provided below the insulator. The insulator is made of glass paste etc.
Sufficient insulation can be maintained with a typical film thickness of 40 to 507 zm. However, the film thickness of this insulator is
The film thickness of a conductor made of silver or the like is 10 to 20 gm, which is considerably thicker, and therefore, when an insulator is applied, a considerably large step is created at its edge and at the via hole portion.

第8図(A)〜(C)にハイブリッドICにおける厚膜
回路の一例を示す、第8図(A)は厚膜回路の平面図、
(B)、(C)は第8図(A)のx−xおよびY−Y線
に沿った断面を示している0図において符号83はセラ
ミックなどがら成る基板1ユに直接形成された下部導体
であり、第8図(A)に破線で示すような回路パターン
を有する。また、符号−82はガラスなどから成る絶縁
体で、第8図(A)に−点鎖線で示すような形状を有す
る。絶縁体82は孤立した下部導体83を接続するため
のビアホール部84を有する。符号8工は1−二部導体
で、第8図(A)に実線で示すパターンを有し、上記ビ
アホール84あるいは絶縁体82の縁部に露出する下部
導体83どぅしを接続する。
FIGS. 8(A) to (C) show an example of a thick film circuit in a hybrid IC, FIG. 8(A) is a plan view of the thick film circuit,
(B) and (C) are cross sections taken along lines xx and Y-Y in FIG. It is a conductor and has a circuit pattern as shown by the broken line in FIG. 8(A). Further, reference numeral -82 denotes an insulator made of glass or the like, and has a shape as shown by the -dotted chain line in FIG. 8(A). The insulator 82 has a via hole portion 84 for connecting the isolated lower conductor 83. Reference numeral 8 designates a 1-2 part conductor, which has a pattern shown in solid lines in FIG.

[発り1が解決しようとする課題] V記のような構造では、第8図(B)、(C)に示すよ
うに絶縁体82の必要な膜厚が下部導体の膜厚よりもか
なり大きく、ビアホール84あるいは絶縁体82の縁部
においてかなり大きな段差が生じる。
[Problem to be solved by Origin 1] In the structure shown in V, the required film thickness of the insulator 82 is much larger than the film thickness of the lower conductor, as shown in FIGS. 8(B) and (C). This results in a fairly large step difference at the edge of the via hole 84 or the insulator 82 .

回路1模を形成する方法としてはスクリーン印刷や直接
描画が考えられるが、特に直接描画を行なう場合には第
8図CB)、(C)に符号86で示すようなビアホール
84の部分、あるいは絶縁体82の縁部の段差において
断線を起こしやすい。
Screen printing or direct drawing can be considered as a method for forming the circuit 1 model, but in particular, when direct drawing is performed, the portions of the via holes 84 or insulation as shown in FIGS. Wire breakage is likely to occur at the step at the edge of the body 82.

この様子を第9図(A)、(B)に示す、第9図におい
て符号43は上部導体81を形成するための導体ペース
トを所定の太さで吐出するノズルである。第9図(A)
に示すように、絶縁体82の段差部に上部導体81を形
成する場合、基板は図のX(ないしY)方向に等速移動
され、その間にノズル43から単位時間当たり一定の敬
のペースト91が吐出される。
This situation is shown in FIGS. 9(A) and 9(B). In FIG. 9, reference numeral 43 indicates a nozzle for discharging conductive paste to a predetermined thickness for forming the upper conductor 81. Figure 9 (A)
As shown in the figure, when forming the upper conductor 81 on the stepped portion of the insulator 82, the substrate is moved at a constant speed in the X (or Y) direction in the figure, and during that time a constant amount of paste 91 is applied from the nozzle 43 per unit time. is discharged.

通常、絶縁体82などの凹凸に追従させるために高さセ
ンサなどを設け、ノズル43の位置を基板の凹凸に追従
させる構成が用いられてはいるが、それでも段差のはげ
しい場所では第9図(B)に符号92で示すようにペー
ストが引っ張られ、基板の段差に追従せずに断線してし
まう。
Usually, a configuration is used in which a height sensor or the like is provided to make the position of the nozzle 43 follow the unevenness of the insulator 82, etc.; In B), the paste is pulled as shown by reference numeral 92, and the wire breaks without following the step of the board.

特に、第10図に示すようにパターン設計の都合によっ
て複数の絶縁体を介して各導体を接続するような場合で
は、符号87のような非常に大きな段差が生じ、このよ
うな部分では従来方法では完全に連続した上部導体81
を確実に形成するのは困難であった。
In particular, as shown in Fig. 10, when each conductor is connected through multiple insulators due to pattern design, a very large step as shown by numeral 87 occurs. Now, the completely continuous upper conductor 81
It was difficult to form it reliably.

本発明の課題は、以りの問題を解決し、完全に連続した
導体パターンを有する厚11り回路を歩留りよ〈製苗で
きるようにすることである。
It is an object of the present invention to solve these problems and to make it possible to manufacture circuits with a thickness of 11 mm with a completely continuous conductor pattern at a high yield.

[課題を解決するための手段] 以上の課題を解決するために、本発明においては、直接
描画により導体、絶縁体の積層からなる厚膜回路を形成
する厚膜回路の形成方法において、基扱七に下部導体を
形成する工程と、下部導体上に絶縁体を形成する工程と
、下部導体と上部導体とを接続するため絶縁体に設けら
れたビアホール領域ないし絶縁体縁部における下部導体
と」一部導体の接続領域に、下部導体と接続され前記ビ
アホール領域ないし絶縁体縁部の段差にほぼ相ジする厚
みの接続導体を直接描画により形成する工程と、複数の
前記接続導体を接続する上部導体を直接描画により形成
する工程から厚膜回路を形成する、あるいは、特に下部
導体−ヒに複数層からなる絶縁体を形成する場合には、
上層側の絶縁体の面積をド層側の絶縁体の面積よりも小
さく形成し、その後複数層の絶縁体の縁部を越えて下層
の下部導体と接続される上部導体を形成するようにした
[Means for Solving the Problems] In order to solve the above problems, in the present invention, a method for forming a thick film circuit consisting of a laminated layer of conductors and insulators is formed by direct writing. (7) a step of forming a lower conductor; a step of forming an insulator on the lower conductor; and a step of forming the lower conductor in a via hole area provided in the insulator or at the edge of the insulator for connecting the lower conductor and the upper conductor. A step of forming a connecting conductor connected to the lower conductor in the connecting area of some of the conductors and having a thickness that is approximately compatible with the step of the via hole area or the edge of the insulator by direct drawing, and an upper part connecting the plurality of connecting conductors. When forming a thick film circuit from the process of forming a conductor by direct drawing, or when forming an insulator consisting of multiple layers especially on the lower conductor,
The area of the insulator on the upper layer side is made smaller than the area of the insulator on the double layer side, and then an upper conductor is formed that crosses the edges of the multiple layers of insulators and connects to the lower conductor of the lower layer. .

[作 用] 以上の構成によれば、絶縁体を乗り越えて下部導体を接
続する上部導体を形成するような場合、いったん接続導
体を形成してからこの接続導体どうしを断線などを生じ
ることなく上部導体により結合できる。また、複数層の
絶縁体を形成する場合には、F層側の絶縁体の面積を下
層側よりも小さくすることで、絶縁体縁部の段差を小さ
くすることができ、上部導体の断線を防止できる。
[Function] According to the above configuration, when forming an upper conductor that crosses over an insulator to connect a lower conductor, it is possible to form a connecting conductor and then connect the connecting conductors to each other without causing disconnection. Can be coupled with a conductor. In addition, when forming multiple layers of insulators, by making the area of the insulator on the F layer side smaller than that on the lower layer side, it is possible to reduce the level difference at the edge of the insulator and prevent disconnection of the upper conductor. It can be prevented.

[実施例] 以下1図面に示す実施例に基づき、本発明の詳細な説明
する。
[Example] The present invention will be described in detail below based on an example shown in one drawing.

第4図に本発明に使用される直接描画装置を。Figure 4 shows the direct drawing device used in the present invention.

また第5図に第4図の装置の制御系の構造を示す。Further, FIG. 5 shows the structure of the control system of the apparatus shown in FIG. 4.

第4図において符号42はセラミックなどから成る回路
基板で、XおよびY方向に移動されるXYテーブル45
上の所定位置に位置決めされる。
In FIG. 4, reference numeral 42 denotes a circuit board made of ceramic or the like, and an XY table 45 that is moved in the X and Y directions.
is positioned at a predetermined position above.

この基板42に対して導体および絶縁体を形成するペー
ストを吐出するノズル43はXY子テーブル5に対して
昨直に配置され、XY平面に垂直なZ軸方向に駆動機構
44を介して移動される。
A nozzle 43 for discharging paste that forms a conductor and an insulator onto the substrate 42 is placed directly in front of the XY child table 5, and is moved via a drive mechanism 44 in the Z-axis direction perpendicular to the XY plane. Ru.

ノズル43からのペーストの吐出および吐出停止、XY
子テーブル5のXY平面における移動をあらかじめ決定
されたプログラムに応じて数値制御することによって、
基板42上に各種の回路膜を形成することができる。そ
の際、基板42の凹凸は高さセンサ41によって検出さ
れ、ノズル43の高さはZ軸方向に沿って駆動機構44
を介して自動的に制御される。
Paste discharge from nozzle 43 and discharge stop, XY
By numerically controlling the movement of the child table 5 in the XY plane according to a predetermined program,
Various circuit films can be formed on the substrate 42. At this time, the unevenness of the substrate 42 is detected by the height sensor 41, and the height of the nozzle 43 is detected by the drive mechanism 44 along the Z-axis direction.
automatically controlled via.

第5図において符号55はXY子テーブル5をXY力方
向移動させるためのモータを制御するモータドライバで
、モータコントローラ54を介してマイクロプロセッサ
などから成るCPU51によって制御される。また、ノ
ズル43の高さは第4図の駆動機構44を構成するモー
タドライバ44aおよびモータコントローラ44bから
成る。ノズル43の高さも、CPU51によって制御さ
れる。
In FIG. 5, reference numeral 55 denotes a motor driver for controlling a motor for moving the XY child table 5 in the XY force directions, and is controlled by a CPU 51 comprising a microprocessor or the like via a motor controller 54. Further, the height of the nozzle 43 is made up of a motor driver 44a and a motor controller 44b that constitute the drive mechanism 44 shown in FIG. The height of the nozzle 43 is also controlled by the CPU 51.

また、ノズル43の膜形成位置における基板42からの
高さは高さセンサ41によって検出され、この検出情報
はCPU51に入力される。ノズル43はコンプレッサ
その他から成る空気源56の圧力によって材料を一定の
速度で吐出するように構成されており、吐出および吐出
停止は圧力制御を行なう7I!磁弁58によって制御さ
れる。
Further, the height of the nozzle 43 from the substrate 42 at the film forming position is detected by the height sensor 41, and this detection information is input to the CPU 51. The nozzle 43 is configured to discharge the material at a constant speed by the pressure of an air source 56 consisting of a compressor or the like, and the discharge and discharge stop are controlled by pressure control. It is controlled by a magnetic valve 58.

電磁弁58の開閉はコントローラ57を介してCPU5
1によって制御される。CPU51はROMあるいはR
AMなどから成るメモリ52にあらかじめ格納されたプ
ログラムに従って、上記のようにモータドライバ55を
介してXY子テーブル5のXY平面における移動を制御
しつつ、適切なタイミングで電磁弁58を介して材料の
吐出/非吐出を制御し、基板42上にパターンを形成す
る。
The opening/closing of the solenoid valve 58 is controlled by the CPU 5 via the controller 57.
1. CPU51 is ROM or R
According to the program stored in advance in the memory 52 consisting of an AM or the like, the movement of the XY child table 5 in the XY plane is controlled via the motor driver 55 as described above, and the material is moved at an appropriate timing via the solenoid valve 58. Ejection/non-ejection is controlled to form a pattern on the substrate 42.

その際、常時高さセンサ41によってノズル43の基板
42からの高さを検出し、この検出値に応じてモータド
ライバ44aを介してノズル43の高さを副筒する。こ
のような直接描画動作は、キーボードおよび表示塁など
から構成される入出力装置53を介して制御される。
At this time, the height of the nozzle 43 from the substrate 42 is constantly detected by the height sensor 41, and the height of the nozzle 43 is adjusted via the motor driver 44a according to this detected value. Such direct drawing operations are controlled via an input/output device 53 comprised of a keyboard, a display board, and the like.

第3図に第4図、第5図の装置を用いて行なわれる直接
描画処理全体の流れを示す、また、第1図(A)〜(D
)、および第2図(A)〜(D)に第3図の手順により
順次形成される導体膜あるいは絶縁膜の状態を示す、第
1図(A)〜(D)および第2図(A)〜(D)はそれ
ぞれ第8図(B)、(C)に示したものと同じ回路パタ
ーンを形成する際の膜形成の様子を示している。以下、
第1図〜第3図を参照して本実施例における厚膜回路の
形成手順を説明する。
Figure 3 shows the flow of the entire direct drawing process performed using the apparatus shown in Figures 4 and 5.
), and FIGS. 1(A) to 2(D) show the states of the conductor film or insulating film formed sequentially by the procedure shown in FIG. 3. ) to (D) respectively show the state of film formation when forming the same circuit pattern as shown in FIGS. 8(B) and (C). below,
The procedure for forming a thick film circuit in this embodiment will be explained with reference to FIGS. 1 to 3.

第3図のステップSlでは下部導体83を第1図(A)
、第2図(A)に示すように基板42上に形成する。こ
の際、CPU51はあらかじめメモリ52に格納された
絶縁体82のパターンに応じてXY子テーブル5の移動
およびペーストの吐出/非吐出を従来と同様の方法によ
って制御する0次に、ステップS2では形成した下部導
体83を乾燥および焼成する。
In step Sl of FIG. 3, the lower conductor 83 is
, are formed on the substrate 42 as shown in FIG. 2(A). At this time, the CPU 51 controls the movement of the XY child table 5 and the discharge/non-discharge of the paste according to the pattern of the insulator 82 stored in the memory 52 in advance in the same manner as in the conventional method. The lower conductor 83 thus obtained is dried and fired.

続いてステップS3では、第1図(B)、第2図(B)
に示すように、あらかじめ決められたパターンで絶縁体
82を形成する。この際、孤立した下部導体83を接続
するためのビアホール84が同時に形成される。ガラス
ペーストなどから成る絶縁体82の厚み(例えば40〜
50pm)は、従来と同様に金、銀、パラジウム合金な
どから成る下部導体83(例えば、lO〜20ILm)
に比べてかなり厚く、ビアホール84および絶縁体82
の縁部では大きな段差が生じる。ステップS4では絶縁
体82の乾燥および焼成を行なう。
Subsequently, in step S3, FIG. 1(B) and FIG. 2(B)
As shown in FIG. 2, an insulator 82 is formed in a predetermined pattern. At this time, a via hole 84 for connecting the isolated lower conductor 83 is formed at the same time. The thickness of the insulator 82 made of glass paste or the like (for example, 40~
50pm) is the lower conductor 83 (for example, lO~20ILm) made of gold, silver, palladium alloy, etc. as in the conventional case.
It is considerably thicker than the via hole 84 and the insulator 82.
There is a large step at the edge. In step S4, the insulator 82 is dried and fired.

続いて、ステップS5では第1図(C)に示すようにビ
アホール84の部分に接続導体11を形成する。従来で
は直接ビアホール部からビアホール部まで上部導体を形
成していたが1本実施例では、図示のようにビアホール
84の深さにほぼ相当する厚み(例えば、20〜30g
m)の接続導体11をビアホール84のみに設ける。ま
た、ビアホール84のみならず、第2図(C)に示すよ
うに絶縁体82の縁部の段差の大きい部分において下部
導体83との結合を行なう位置にも、接続導体11′を
形成する。これらの接続導体11゜11′を形成後、ス
テップS6ではこれらの導体の乾燥および焼成を行なう
Subsequently, in step S5, the connection conductor 11 is formed in the via hole 84 as shown in FIG. 1(C). In the past, the upper conductor was formed directly from via hole part to via hole part, but in this embodiment, as shown in the figure, the upper conductor is formed with a thickness approximately equivalent to the depth of the via hole 84 (for example, 20 to 30 g).
The connection conductor 11 of m) is provided only in the via hole 84. Further, the connecting conductor 11' is formed not only in the via hole 84 but also at a position where the connection with the lower conductor 83 is to be made in a large stepped portion of the edge of the insulator 82, as shown in FIG. 2(C). After forming these connecting conductors 11° and 11', these conductors are dried and fired in step S6.

ステップS7においては、上部導体81を例えば10〜
20JLm厚さで描画する。この場合、第1図(D)に
示すようにすでにビアホール84.84内に形成された
接続導体11.11を結合するようにL油導体81を描
画する。この時、すでに接続導体11が形成されている
ため、上部導体81が乗り越えるべき段差は従来に比べ
て非常に小さく、断線などを生じることなく確実に接続
導体11を介して接続すべき下部導体83を接続できる
。第2図CD)に示すように絶縁体82の縁部において
も同様で、この位置においてもL油導体81が乗り越え
る段差が小さいため、確実に下部導体を接続できる。
In step S7, the upper conductor 81 is
Draw with a thickness of 20JLm. In this case, as shown in FIG. 1(D), the L oil conductor 81 is drawn so as to connect the connection conductor 11.11 already formed in the via hole 84.84. At this time, since the connecting conductor 11 has already been formed, the step that the upper conductor 81 must overcome is much smaller than in the past, and the lower conductor 83 must be reliably connected via the connecting conductor 11 without causing any disconnection. can be connected. As shown in FIG. 2CD), the same applies to the edge of the insulator 82, and since the level difference that the L oil conductor 81 overcomes is small at this position as well, the lower conductor can be reliably connected.

この様子を第6図(A)、(B)に示す、第6図(A)
、(B)は第9図(A)、(B)に相当し、絶縁体82
の縁部においてペースト91によって上部導体81を形
成する場合を示している。
This situation is shown in Fig. 6 (A) and (B). Fig. 6 (A)
, (B) correspond to FIGS. 9(A) and (B), and the insulator 82
The case where the upper conductor 81 is formed with paste 91 at the edge of is shown.

■−記手順によれば、第6図(A)に示すように絶縁体
82の縁部(あるいはビアホール部)においてはあらか
じめ接続導体11”が形成されているため、第6図(B
)に示すように段差部分が小さくなり、断線なく確実に
上部導体81を形成できる。この場合、ノズル43の高
さを高さセンサ41を介して調節することによって、確
実な導体パターン形成が行なえるのは言うまでもない。
According to the procedure described in ■-, the connection conductor 11'' has been formed in advance at the edge of the insulator 82 (or the via hole part) as shown in FIG. 6(A).
), the step portion becomes smaller and the upper conductor 81 can be reliably formed without disconnection. In this case, it goes without saying that by adjusting the height of the nozzle 43 via the height sensor 41, a reliable conductor pattern can be formed.

ステップS7で上部導体描画が終了した場合には、ステ
ップS8でこの上部導体の乾燥および焼成を行なって処
理を終了する。さらに多層にわたって絶縁層、導体層を
形成する場合には、上記の手順を繰り返せばよい。
When the drawing of the upper conductor is completed in step S7, the upper conductor is dried and fired in step S8, and the process ends. Furthermore, in the case of forming multiple insulating layers and conductive layers, the above procedure may be repeated.

上記実施例によれば、ビアホール部、あるいは絶縁体縁
部など、絶縁体の段差が大きくなりがちな部分において
はあらかじめ導体形成を行ない、乾燥・焼成した後それ
らを結合するE油導体を形成するようにしたので、導体
の断線などを生じることなく確実に歩留りよ〈厚膜回路
を形成できる。
According to the above embodiment, conductors are formed in advance in areas where insulator steps tend to be large, such as via holes or insulator edges, and after drying and firing, an E oil conductor is formed to connect them. As a result, thick film circuits can be formed with high yield without causing disconnection of conductors.

なお、1−記実施例では上部導体が単数の絶縁層を東り
越えて下部導体を結合する構成を示したが、第1O図に
示すようにパターン設計の結合によって複数の絶縁体8
2を乗り越える必要がある場合には、第7図に示すよう
に複数の絶縁体82のうち1−側の絶縁体の面積を下部
の絶縁体の面積よりも小さく構成するとよい、このよう
な構成によって実質的な段差部の角度がより緩やかにな
るため、断線を生じることなく確実に上部導体を形成で
きる。
In the embodiment 1-, the upper conductor crosses a single insulating layer to connect the lower conductor, but as shown in FIG.
2, it is preferable to configure the area of the insulator on the 1- side of the plurality of insulators 82 to be smaller than the area of the lower insulator, as shown in FIG. Since the actual angle of the stepped portion becomes gentler, the upper conductor can be reliably formed without causing wire breakage.

[発明の効果] 以上から明らかなように、本発明によれば、直接描画に
より導体、絶縁体の積層からなる厚膜回路を形成する厚
膜回路の形成方法において、基板上に下部導体を形成す
る工程と、F油導体上に絶縁体を形成する工程と、下部
導体と上部導体とを接続するため絶縁体に設けられたビ
アホール領域ないし絶縁体縁部における下部導体と一ヒ
部導体の接続領域に、下部導体と接続され前記ビアポー
ル領域ないし絶縁体縁部の段差にほぼ相当する厚みの接
続導体を直接描画により形成する1程と、複数の前記接
続導体を接続する上部導体を直接描画により形成するに
程から厚膜回路を形成する、あるいは、特に下部導体上
に複数層からなる絶縁体を形成する場合には、F層側の
絶縁体の面積を下層側の絶縁体の面積よりも小さく形成
し、その後複数層の絶縁体の縁部を越えて下層の下部導
体と接続される1−油導体を形成するようにしているの
で、絶縁体を乗り越えて下部導体を接続する上部導体を
形成するような場合、いったん接続導体を形成してから
この接続導体どうしを断線などを生じることなく上部導
体により結合できる。また、複数層の絶縁体を形成する
場合には、上層側の絶縁体の面積を下層側よりも小さく
することで、絶縁体縁部の段差を小さくし、上部導体の
断線を防ロー、でき、完全に連続した導体パターンを有
する厚膜回路を歩留りよく製造できるという優れた効果
がある。
[Effects of the Invention] As is clear from the above, according to the present invention, in a thick film circuit forming method for forming a thick film circuit made of a laminated layer of conductors and insulators by direct writing, a lower conductor is formed on a substrate. a step of forming an insulator on the F oil conductor; and a step of connecting the lower conductor and the lower conductor in the via hole area provided in the insulator or the edge of the insulator for connecting the lower conductor and the upper conductor. forming a connecting conductor connected to the lower conductor in the area by direct drawing and having a thickness approximately corresponding to the step of the via pole area or the edge of the insulator; and forming an upper conductor connecting the plurality of connecting conductors by direct drawing. When forming a thick film circuit from the stage of formation, or especially when forming an insulator consisting of multiple layers on the lower conductor, the area of the insulator on the F layer side should be larger than the area of the insulator on the lower layer side. Since the 1-oil conductor is formed small and then crosses over the edges of multiple layers of insulators to connect to the lower conductor of the lower layer, the upper conductor that crosses over the insulators and connects the lower conductor. In the case where the connecting conductors are formed, once the connecting conductors are formed, the connecting conductors can be connected to each other by the upper conductor without causing disconnection or the like. In addition, when forming multiple layers of insulators, by making the area of the insulator on the upper layer smaller than that on the lower layer, the step at the edge of the insulator can be reduced, preventing disconnection of the upper conductor. This method has an excellent effect in that a thick film circuit having a completely continuous conductor pattern can be manufactured with high yield.

【図面の簡単な説明】[Brief explanation of the drawing]

第11,4(A)〜(D)および第2図(A>〜(D)
はそれぞれ本発明による厚膜回路の形成の様子をzl?
した断面図、第3図は本発明による厚膜回路形成のf順
を示したフローチャート図、第4図は本発明において用
いられる直接描画装置の構成を示した斜視図2第5図は
第4図の制御系の構成を示したブロック図、第6図(A
)、(B)は本発明における利点を示した説明図、第7
図は本発明の異なる絶縁体形成方法を示した断面図、第
8図(A)は厚膜回路パターンの上面図、第8図(B)
、(C)はそれぞれ第8図(A)におけるx−Xおよび
Y−Y線に沿った断面図、第9図(A)、CB)は従来
の厚膜回路形成方法の問題点を示した説明図、第10図
は従来方法による異なる問題点を示した断面図である。 11・・・接続導体   41・・・高さセンサ42・
・・ノ、(板      43・・・ノズル44・・・
駆動a構   45・・・XYテーブル51・・・CP
U      52・・・メモリ54・・・モータコン
トローラ 55・・・モータドライバ 58・・・′市磁弁 82・・・絶縁体 84・・・ビアホール 81・・・上部導体 83・・・下部導体 91・・・ペースト 駅遣午1直の)O−婬斗め 第30 第1図 屑悄ヂC話弔へロ毛の舶′j閲 第2図 お光即系のフ0−770 第5図 r泊ト蹄塙綺−説咥閲 第6図 輯rJづkv番伽割し断面防
11, 4(A)-(D) and FIG. 2(A>-(D)
zl? and zl? respectively show how the thick film circuit is formed according to the present invention.
FIG. 3 is a flowchart showing the f order of thick film circuit formation according to the present invention. FIG. 4 is a perspective view showing the configuration of the direct writing apparatus used in the present invention. A block diagram showing the configuration of the control system in Figure 6 (A
), (B) is an explanatory diagram showing the advantages of the present invention, No. 7
The figures are cross-sectional views showing different methods of forming an insulator according to the present invention, FIG. 8(A) is a top view of a thick film circuit pattern, and FIG. 8(B) is a top view of a thick film circuit pattern.
, (C) are cross-sectional views taken along lines x-X and Y-Y in FIG. 8(A), respectively, and FIGS. 9(A) and CB) show problems with the conventional thick film circuit forming method. The explanatory diagram, FIG. 10, is a sectional view showing different problems caused by the conventional method. 11... Connection conductor 41... Height sensor 42.
・・・ノ、(Plate 43... Nozzle 44...
Drive a mechanism 45...XY table 51...CP
U 52...Memory 54...Motor controller 55...Motor driver 58...' City valve 82...Insulator 84...Via hole 81...Upper conductor 83...Lower conductor 91 ...Paste Station's 1st shift) r Tomari Totoihanaki - Commentary Review Figure 6

Claims (1)

【特許請求の範囲】 1)直接描画により導体、絶縁体の積層からなる厚膜回
路を形成する厚膜回路の形成方法において、基板上に下
部導体を形成する工程と、下部導体上に絶縁体を形成す
る工程と、下部導体と上部導体とを接続するため絶縁体
に設けられたビアホール領域ないし絶縁体縁部における
下部導体と上部導体の接続領域に、下部導体と接続され
前記ビアホール領域ないし絶縁体縁部の段差にほぼ相当
する厚みの接続導体を直接描画により形成する工程と、
複数の前記接続導体を接続する上部導体を直接描画によ
り形成する工程とからなることを特徴とする厚膜回路の
形成方法。 2)直接描画により導体、絶縁体の積層からなる厚膜回
路を形成する厚膜回路の形成方法において、基板上に下
部導体を形成する工程と、下部導体上に複数層からなる
絶縁体を形成する場合上層側の絶縁体の面積を下層側の
絶縁体の面積よりも小さく形成する工程と、前記複数層
の絶縁体の縁部を越えて下層の下部導体と接続される上
部導体を形成する工程とからなることを特徴とする厚膜
回路の形成方法。
[Claims] 1) A method for forming a thick film circuit in which a thick film circuit consisting of a laminated layer of a conductor and an insulator is formed by direct writing, which includes the step of forming a lower conductor on a substrate, and forming an insulator on the lower conductor. forming a via hole region provided in the insulator for connecting the lower conductor and the upper conductor, or a connecting region of the lower conductor and the upper conductor at the edge of the insulator, the via hole region or the insulator connected to the lower conductor; A process of forming a connecting conductor with a thickness approximately equivalent to the step at the body edge by direct drawing;
A method for forming a thick film circuit, comprising the step of forming an upper conductor connecting the plurality of connection conductors by direct drawing. 2) A method for forming a thick film circuit in which a thick film circuit consisting of a stack of conductors and insulators is formed by direct writing, which includes a step of forming a lower conductor on a substrate and forming an insulator consisting of multiple layers on the lower conductor. In this case, the area of the insulator on the upper layer side is formed smaller than the area of the insulator on the lower layer side, and the upper conductor is formed to be connected to the lower conductor of the lower layer beyond the edges of the multiple layers of insulators. A method for forming a thick film circuit, comprising the steps of:
JP18824288A 1988-07-29 1988-07-29 Forming method for thick film circuit Pending JPH0239597A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18824288A JPH0239597A (en) 1988-07-29 1988-07-29 Forming method for thick film circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18824288A JPH0239597A (en) 1988-07-29 1988-07-29 Forming method for thick film circuit

Publications (1)

Publication Number Publication Date
JPH0239597A true JPH0239597A (en) 1990-02-08

Family

ID=16220276

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18824288A Pending JPH0239597A (en) 1988-07-29 1988-07-29 Forming method for thick film circuit

Country Status (1)

Country Link
JP (1) JPH0239597A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006140437A (en) * 2004-09-27 2006-06-01 Seiko Epson Corp Method for forming multilayer structure, method for manufacturing wiring board, and method for manufacturing electronic apparatus
JP2007247573A (en) * 2006-03-17 2007-09-27 Matsushita Electric Ind Co Ltd Ceiling fan
JP2008034880A (en) * 2004-08-20 2008-02-14 Seiko Epson Corp Method of forming multilayer structure, and method of manufacturing wiring substrate and electronic device
JP2009039748A (en) * 2007-08-08 2009-02-26 Senju Metal Ind Co Ltd Jet soldering bath
JP2012089204A (en) * 2010-10-20 2012-05-10 Dainippon Printing Co Ltd Flexure substrate with wiring, method for manufacturing flexure substrate with wiring, flexure with wiring, flexure with wiring with element and hard disk drive

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182293A (en) * 1982-04-19 1983-10-25 松下電器産業株式会社 Thick film circuit board
JPS62282448A (en) * 1986-05-30 1987-12-08 Sharp Corp Multilayer interconnection structure
JPS6358996A (en) * 1986-08-29 1988-03-14 株式会社島津製作所 Method of forming conductor pattern of hybrid ic
JPS63164392A (en) * 1986-12-26 1988-07-07 ジューキ株式会社 Circuit forming equipment

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58182293A (en) * 1982-04-19 1983-10-25 松下電器産業株式会社 Thick film circuit board
JPS62282448A (en) * 1986-05-30 1987-12-08 Sharp Corp Multilayer interconnection structure
JPS6358996A (en) * 1986-08-29 1988-03-14 株式会社島津製作所 Method of forming conductor pattern of hybrid ic
JPS63164392A (en) * 1986-12-26 1988-07-07 ジューキ株式会社 Circuit forming equipment

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008034880A (en) * 2004-08-20 2008-02-14 Seiko Epson Corp Method of forming multilayer structure, and method of manufacturing wiring substrate and electronic device
JP4506809B2 (en) * 2004-08-20 2010-07-21 セイコーエプソン株式会社 MULTILAYER STRUCTURE FORMING METHOD, WIRING BOARD AND ELECTRONIC DEVICE MANUFACTURING METHOD
JP2006140437A (en) * 2004-09-27 2006-06-01 Seiko Epson Corp Method for forming multilayer structure, method for manufacturing wiring board, and method for manufacturing electronic apparatus
US7767252B2 (en) 2004-09-27 2010-08-03 Seiko Epson Corporation Multilayer structure forming method, method of manufacturing wiring board, and method manufacturing of electronic apparatus
JP2007247573A (en) * 2006-03-17 2007-09-27 Matsushita Electric Ind Co Ltd Ceiling fan
JP2009039748A (en) * 2007-08-08 2009-02-26 Senju Metal Ind Co Ltd Jet soldering bath
JP2012089204A (en) * 2010-10-20 2012-05-10 Dainippon Printing Co Ltd Flexure substrate with wiring, method for manufacturing flexure substrate with wiring, flexure with wiring, flexure with wiring with element and hard disk drive

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