JPH0239440A - High speed transistor - Google Patents

Abstract

PURPOSE:To reduce the lateral degree of freedom of a two-dimensional carrier gas and make the gas a one-dimensional carrier gas and increase its mobility by a method wherein the electron (positive hole) supply layer and the channel layer of a high electron mobility transistor having a modulated doping structure are divided into a plurality of lattices in parallel with the direction connecting between the source and drain. CONSTITUTION:For instance, an i-type AlGaAs layer 2, an intrinsic GaAs layer 2 and an n<+>-type AlGaAs layer 4 which are successively built up on a semi-insulating GaAs substrate 1 and source and drain electrodes 5 which are brought into ohmic contact with the layers 2-4 are provided. Electrons supplied by the layer 4 are accumulated to form a two-dimensional electron gas. An aperture 7 is formed in an interlayer insulating layer 6 formed on the layer 4 on the part between the source and drain electrodes 5 and a gate electrode 8 is so provided as to be brought into contact with the substrate 1 and the respective layers 2-4. At least the parts of the layers 2-4 corresponding to the aperture 7 are divided into layers 22, layers 23 and layers 24 by wedge type cuts and a plurality of fine lattices 20 separated from each other are provided in parallel with the direction connecting between the source and drain electrodes 5. The gate electrode 8 is brought into contact with the side surfaces of the respective lattices 20.

Description

DETAILED DESCRIPTION OF THE INVENTION (Summary) The present invention relates to a high electron mobility or high hole mobility transistor having a modulated doping structure.

The aim is to increase the speed by making the carrier transport direction one-dimensional.

A first layer made of an intrinsic semiconductor formed on the semiconductor substrate, having a defined gate formation region on a high-resistance semiconductor substrate, and an electron affinity of the intrinsic semiconductor of the first layer. or the sum of the electron affinity and the hand gap is larger than the sum of the electron affinity and the hand gap of the intrinsic semiconductor of the first layer; a second layer laminated on top of the first layer; a source and a drain formed in ohmic contact with at least the first layer; and at least the first layer in the gate formation region. The structure includes a cutout portion that separates the second and third layers into a plurality of lattices parallel to the direction connecting the source and drain, and a gate electrode formed to fill the cutout portion. Ru.

[Industrial application field]

The present invention describes HEMs formed using modulation doping techniques.
T (tight Electron Mobility
The present invention relates to high electron mobility transistors called transistors and 1-transistors that utilize high hole mobility with a similar structure.

[Conventional technology]

Various high electron mobility semiconductor devices have been proposed that use a two-dimensional electron gas generated at the heterointerface between an n-AlGaAs layer and a 1-GaAs layer as a channel layer. Furthermore, a semiconductor device with high hole mobility has already been proposed in which a two-dimensional hole gas generated at the hetero interface between a p-AlGaAs layer and a 1-GaAs layer is used as a channel layer. The electron mobility and hole mobility in two-dimensional electron gas and two-dimensional hole gas exhibit much higher values at low temperatures than those of normal three-dimensional electrons. It is theoretically predicted that higher electron mobility will result by further reducing the degree of freedom for carrier transport in a two-dimensional electron gas (H,5akaki et al., In
5t, Phys, Conf.

Ser. No. 63. Int, Symp,
GaAs and RelatedCompou
nds, p, 251-256.1981), this 1
A structure shown in FIG. 5 has been proposed as an element using dimensional electron gas.

In this structure, a groove 54 is provided in a laminated layer consisting of p-AlGaAs layers 51 and 53 and a ρ-GaAs layer 52 sandwiched between these layers, and a gate electrode 56 is provided in contact with the wall surface of this groove 54 via an insulating layer 55. A metal-
Old S (Metal-5emi) consisting of an insulating layer and a semiconductor
conductorInsulator) structure. Carrier electrons generated in the inversion layer 57 of p-GaAsN52 travel in a one-dimensional direction parallel to a54. However, since these electrons are scattered by impurities in the p-GaAs layer 52, high mobility cannot be expected.
There are problems with aAs, such as the fact that a high-quality and stable insulating layer with few interfacial impurity levels has not yet been found.

In contrast, the present inventor has developed a type of PBT (Permiable Ba5e Tran) that has a structure that confines the two-dimensional electron gas transport in the HEMT structure in one dimension.
sister) (patent application No. 62-0641)
71. (dated March 20, 1986). Its structure is as shown in FIG.

The principle of PBT was first disclosed in US Pat. No. 4,378,629. In the PBT disclosed in the above-mentioned US patent publication, electrons transported in the thickness direction of the semiconductor layer between the emitter collectors are controlled by a comb-tooth-shaped base electrode embedded in the semiconductor layer.

It does not use two-dimensional electron gas generated near the heterojunction interface. Its structure and problems are described in the above application.

The structure shown in FIG. 6 is one in which the principle of the above-mentioned early PBT is applied to the control of two-dimensional electron gas.

[Problem to be solved by the invention]

In the PBT having the structure shown in Fig. 6, 1, for example, 1GaA
1-AIGaAs layer 62 + 1-GaA on the s-substrate 61
s layer 63. n-AlGaAs layers 64 are sequentially stacked,
A comb-shaped gate 65 is provided that penetrates these layers. The gate 65 is connected to the upper electrode 67 through an opening provided in the insulating layer 66, and are set to the same potential. 2 generated in the x-GaAs layer 63 with a thickness of approximately 100 mm.
Dimensional electron gas passes through the 1000 mm gap between the gates 65 and flows between the source/drain 68. Since the thickness of the depletion layer generated around the gate 65 changes depending on the voltage applied to the upper electrode 67, the current flowing between the source/drain 68 is controlled, and the two-dimensional electron gas is perpendicular to the transport direction. It has limited directional freedom and behaves as a one-dimensional electron gas.

As described above, the structure shown in FIG. 6 allows the HEMT to operate at higher speeds. However, the structure of FIG.

It is necessary to form openings corresponding to the comb-tooth-shaped gates 65 in the semiconductor layers 62 to 64 and the insulating layer 66.

Furthermore, since it is necessary to form an upper electrode 67 connected to the gate 65, there is a drawback that the process is complicated. In addition, dry etching technology is used as a means to form openings, and especially when the opening area becomes minute, crystallographic defects may occur near the opening after etching, resulting in a drop in current, thermal instability, etc. There was a problem in that characteristics tended to deteriorate.

An object of the present invention is to solve the above-mentioned problems in conventional semiconductor devices using one-dimensional electron gas, and to make it possible to provide high-performance semiconductor devices with simpler steps.

[Means to solve the problem]

``The second object is to have a defined gate formation region on a high-resistance semiconductor substrate, to form a first layer made of an intrinsic semiconductor formed on the semiconductor substrate, and to have an electron affinity that the intrinsic semiconductor has. Consisting of a semiconductor of one conductivity type, which is either smaller than the electron affinity or whose sum of electron affinity and band gap is larger than the sum of the electron affinity and Hunt gap of the intrinsic semiconductor constituting the first layer, a second layer laminated on the first layer; a source and a drain formed in at least ohmic contact with the first layer; and at least the first layer in the gate formation region. It is characterized by comprising a cutout portion that separates the second and third layers into a plurality of lattices parallel to the direction connecting the source and drain, and a gate electrode formed to fill the cutout portion. This is achieved by the high-speed transistor according to the present invention.

[Function] 1-GaAs layer and n-AlGaA provided on both sides of this layer
The s-layer is processed into a plurality of microlattices parallel to the direction connecting the source/drain. A common gate electrode is formed in contact with these microlattices. n-type AlGaAs is an intrinsic G
Because it has a lower electron affinity than aAs, + n-AlGaA
Two-dimensional electron gas is generated in the 1-GaAs layer near the interface with the s-layer. When a negative voltage is applied to the gate electrode, the depletion layer in the 1-GaAs layer at the interface with the gate electrode expands,
The two-dimensional electron gas in each lattice-like 1-GaAs layer is 1
It becomes a dimensional electron gas.

Similarly, p-AlGaAs layers are provided on both sides of the 1-GaAs layer.

These 1-GaAs layers and p-AlGaAs layers are
Processed into multiple microlattices parallel to the direction connecting the drains.

A common gate electrode is formed in contact with these microlattices. Since the sum of the electron affinity and hand gap of p-type AlGaAs is larger than the sum of the electron affinity and hand gap of intrinsic GaAs, two-dimensional hole gas is generated in the 1-GaAs layer near the interface with the p-AlGaAs layer. . When a positive voltage is applied to the gate electrode, the depletion layer in the 1-GaAs layer at the interface with the gate electrode expands, and each 1-G
The two-dimensional hole gas in aA5N becomes a one-dimensional electron gas.

Current is carried by this one-dimensional electron gas or one-dimensional hole gas, and its magnitude is controlled by the magnitude of the negative or positive voltage applied to the gate electrode.

〔Example〕

It is a cutaway perspective view showing the structure of the cover. As shown,
For example, a 1-AlGaAs layer 2, an intrinsic GaAs (i-GaAs) layer 3, n, which are sequentially epitaxially grown on a semi-insulating GaAs (Sl-GaAs) substrate 1.
”-AlGaAs layer 4.

It has source/drain electrodes 5 in ohmic contact with these layers 2-4. 1-GaAs layer 33 has n゛Al
GaAsAlGaAs layer 4 Electrons are accumulated and a two-dimensional electron gas is generated. Although the 1-AlGaAs layer 2 is not essential, it strongly confines the electron gas generated in the 1-GaAs layer 3 within this layer, thereby increasing the two-dimensionality.

For example, 5iON (
An interlayer insulating layer 6 made of (silicon oxynitride) is formed. An open lower is provided at a predetermined position between the source/drain electrodes 5 of the interlayer insulating layer 6, and a layer 1, for example, of aluminum is formed in contact with the Sl-GaAs substrate 1 and each layer 2 to 4 exposed in the open lower. A gate electrode 8 made of (Al) is provided.

Note that the source/drain electrode 5 has a two-layer structure, for example, a gold-germanium (AuGe) alloy thin film and a gold (Au) thin film, and a part of it is directly below the n''-AlGaAs layer 4.
An alloy layer 9 is formed by diffusion to reach the 5l-GaAs substrate 1.

1-AlGaAs layer 2 and intrinsic GaAs (i-GaA
s) The layer 3 and the n-AlGaAs layer 4 have a small (open lower exposed region, that is, a portion in contact with the gate electrode 8, which has a plurality of layers parallel to the direction connecting the source/drain electrodes 5). are separated in a grid pattern.

FIG. 2 is a cross-sectional view taken along the line A-A in FIG.
3 and n''-AlGaAs layers 24.The period of the lattice is approximately 2000.
It's a person. The gate electrode 8 is formed to fill the notch 10 and is in contact with the side surface of each grating 20. As a result, the gate electrode 8 forms a 1-AlGaAs layer 22 . A Schottky junction is formed with the l-GaAs layer 23 and the n''-AlGaAs layer 24.

When a negative voltage is applied to the gate electrode 8 with respect to the source/drain electrode 5, 1-G near the interface with the gate electrode 8
The depletion layer in the aAs layer 23 is extended, and the two-dimensional electron gas is confined in the center of each 1-GaAs layer 23, as shown in FIG.

The two-dimensional electron gas loses its degree of freedom in the direction perpendicular to the axis of the lattice, and becomes a one-dimensional electron gas (IDEG). That is, the current between the source/drain electrodes 5 is carried by one-dimensional electron gas, and the current value is controlled by the magnitude of the negative voltage applied to the gate electrode 8.

As described above, the high electron mobility transistor of the present invention operates according to the hepatic principle, but unlike the conventional hepatic T, the carrier is a one-dimensional electron gas, so that higher speed operation is possible.

Figures 3 (al to C) show cross-sectional views of the grating in a structure of another embodiment of the invention. FIG. 3 (in the Al embodiment, 1-GaAs layer 23 and n''-AlGa
A plurality of As layers 24 are each provided. According to this structure.

One-dimensional electron gas (IDEG) is generated in each 1-GaAs layer 23.

The current capacity of the transistor is increased. FIGS. 3(b) and 3(c) show examples of gratings having shapes different from those of the previous embodiments. 1-AlGaAs layer 22 and 1-GaAs
The lattice consisting of the layer 23 and the n''-AlGaAs layer 24 has a trapezoidal shape (Fig. 3, (bl)) or a semicircular shape (Fig. 3(C)).
). These shapes are similar to the notch 1
It may be selected appropriately depending on the method of forming 0.

FIG. 4 is a sectional view of a main part showing the manufacturing process of a high electron mobility transistor according to the present invention, and the same parts as in the above embodiment are given the same reference numerals.

FIG. 4 (see al) 1 A semi-insulating GaAs substrate 1 with the (100) plane exposed, for example, using the well-known MBE (molecular beam epitaxy) method or FIOCVD (metal-organic chemical vapor deposition) method. On top, 1-AlGaAs layer 2
．． 1-GaAs layer 3°n'-AIGaAs layer 4 are sequentially crystal-grown. The thickness of AlGaAs layers 2 and 4 is
The thickness of the 1-GaAs layer 3 is approximately 100.The thickness of the 1-GaAs layer 3 is approximately 100.The steps up to this point are as follows: This is done by rapid reading in the same crystal growth apparatus.

After the above, an MN (not shown) is formed in a region other than the transistor formation region. In this method, for example, a resist mask having an opening in the isolation region is formed, and
A method may be used in which protons are ion-implanted to a depth reaching the 5I-GaAs substrate 1 from the GaAs layer 4 to inactivate the semiconductor layer, or a method may be used in which the semiconductor layer is inactivated.
A groove reaching the substrate 1 may also be formed. After this, an n"-AlGaAs layer 4 is formed using a well-known plasma CVD method or the like.
An interlayer insulating layer 6 made of, for example, 5iON (silicon oxynitride) and having a thickness of about 3,500 layers is formed thereon.

Next, a resist layer (not shown) is applied on the nine interlayer insulating layers 6, and this resist layer is patterned to form openings 11 over the source/drain forming regions.

Using a dry etching method, the interlayer insulating layer 6 in the opening 11 is selectively removed, and then the AlG exposed in the opening 11 is removed.
an Au thin film on the entire aAs layer 2 and the resist layer;
Sokel on Ni) thin film + AuGe7!4 film sequentially
Form. These metal thin films are formed using a well-known vapor deposition method.

A sputtering method may be used. Next, the resist layer is removed. At the same time as removing the resist.

The metal thin film other than the source/drain formation region is lifted off and removed. Thereafter, the 5l-GaAs substrate 1 is heat treated at 400° C. for about 10 minutes in an inert atmosphere. In this way, as shown in Figure 4 (bl),
A source/drain electrode 5 is formed in the opening 11, and a low resistance alloy layer 9 extending from the AlGaAs layer 4 to the 5l-GaAs substrate 1 is formed.

Next, using the glue sogelaf technique and dry etching method similar to those described above, as shown in FIG. 4 (0).

An open lower is provided in the interlayer insulation N6 of the gate formation region.

FIG. 4Fdl is a perspective view at this stage, showing a part of the separation region 12 on the surface of the AlGaAs layer 4 exposed in the open lower part.

5I-GaAs in the state shown in FIG. 4(C) and (dl)
A resist is applied to the surface of the substrate 1, and the portion above the open lower portion is patterned into a grid-like resist mask 13 as shown in FIG. 4(e). FIG. 4 (el shows a cross section in the AA direction of FIG. 4 (dl) after the resist mask 13 is formed, and the resist mask 13 has a lattice shape parallel to the direction in which the source/drain electrodes 5 are connected. A preferred method for forming the lattice-shaped resist mask 13 is an interference exposure method, in which the resist is exposed to a pattern of interference fringes produced by causing two coherent light beams to interfere with each other in a resist layer. is exposed and developed to obtain a lattice-shaped resist mask 13.Therefore, no exposure mask is required.The lattice period of the resist mask 13 is, for example, 2000 as described above.

Next, the surface exposed from the resist mask 13 is subjected to anisotropic etching. AlGaAs epitaxially grown on (100)X of 5l-GaAs substrate 1
Layer 4. 1-GaAs layer 3, AlGaAs layer 2,
NH<0lllhOz: flzO220 Near: 973
When a mixed solution of (111)A is used as an etching agent, (111)A
Since the etching rate of the s-plane is high, a square-shaped groove, that is, a notch 10 is formed in these layers, as shown in FIG. 4(f). The above etching progresses to the lower part of the resist mask 13 as side etching. Therefore, when the etching progresses beyond a certain point, the inclined surfaces come into contact with each other and the grating 20 becomes triangular. In the structure of the present invention, the lattice 20 does not necessarily have to be triangular, and as shown in FIG.
There is no problem even if the layer 4 has a trapezoidal shape with a flat portion still remaining at the top. Further, the bottom of the notch 10 only needs to reach the AlGaAs layer 2, and does not necessarily need to reach the GaAs 5 plate 1.

After the above-mentioned anisotropic etching, the resist mask 13 was removed, and a new resist was applied to the surface of the GaAs4 plate 1 on which the grating 20 was formed, and this resist layer was coated.

An opening corresponding to the gate opening 7 shown in FIG. As shown in FIG. A gate electrode 8 is formed in contact with the grid 20. The gate electrode 8 has a portion 81 extending over the interlayer insulating layer 6 around the open lower portion.This extending portion 81 is used as a contact portion of the gate wiring.

One-dimensional electron gas is utilized as described above.

A high electron mobility transistor according to the present invention having the structure shown in the perspective view of FIG. 4 (hl) is formed. FIG. 4 (h)
is equivalent to the partially cutaway perspective view of FIG.

According to the structure of the present invention, the formation of the grating 20 that generates one-dimensional electron gas is performed using interference exposure and wet etching, and it is only necessary to form the gate electrode 8 on the grating 20. Therefore, compared to the case where an opening is formed using dry etching, a comb-tooth-shaped gate 65 is formed in this opening, and an upper electrode 67 is further formed, as in the PBT having the structure shown in FIG. The process is simple and the problem of defects caused by dry etching can be avoided.

In the above embodiment, the case of a high electron mobility transistor using one-dimensional electron gas was explained, but the n-AlGaAs layer 4 in FIGS.
By replacing it with an lGaAs layer, a high hole mobility transistor can be formed.

That is, as described above, the sum of the electron affinity and band gap of p-type AlGaAs is greater than the sum of the electron affinity and band gap of intrinsic GaAs. therefore.

1-GaAs near the interface with p-AlGaAs layer
A two-dimensional hole gas is generated in the layer. Therefore, when a positive voltage is applied to the gate electrode, 1-
The depletion layer in the GaAs layer stretches, and each 1-GaAs layer in a lattice shape
The two-dimensional hole gas in the layer becomes one-dimensional hole gas. The current between the source/drain electrode 5 is carried by this one-dimensional hole gas, and the value of the current is controlled by the magnitude of the positive voltage applied to the gate electrode 8.

(Effects of the Invention) According to the present invention, the electron or hole supply layer and the channel layer in a high electron mobility or high hole mobility transistor with a modulation doping structure are formed into a plurality of lattices extending in the direction connecting the source/drain. By separating, the degree of freedom in the lateral direction of the two-dimensional carrier gas is reduced, making it a one-dimensional gas and increasing its mobility.As a result, it is possible to provide a higher speed transistor.

FIG. 3 is a sectional view of a main part for explaining the shape of a lattice and the generation of one-dimensional electron gas.

FIG. 5 is a cross-sectional view of a main part in an embodiment of the manufacturing process. FIG. 5 is a perspective view showing an example of a conventional structure using one-dimensional electron gas.

FIG. 6 is a perspective view showing an example of the structure of a PBT using one-dimensional electron gas.

In fig.

1 is a 5l-GaAs substrate.

2 and 22 are 1-AlGaAs layers 3 and 23 are 1-GaAs layers.

4 and 24 are n-AlGaAs layers 5 is a source/drain electrode.

6 is an interlayer insulating layer.

7 and 11 are openings.

8 is a gate electrode; 9 is the alloy layer.

10 is the notch 12 is the separation area 13 is resist mask 20 is a grid.

81 is the stretched part It is.

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Claims (1)

[Claims] A first layer made of an intrinsic semiconductor formed on the semiconductor substrate, having a gate formation region defined on a high-resistance semiconductor substrate, and an intrinsic semiconductor constituting the first layer. The first layer is made of a semiconductor of one conductivity type, which has an electron affinity smaller than that of the intrinsic semiconductor constituting the first layer, or whose sum of electron affinity and band gap is larger than the sum of the electron affinity and band gap of the intrinsic semiconductor constituting the first layer; a second layer stacked on the first layer; a source and a drain formed in ohmic contact with at least the first layer; and at least the first and second layers in the gate formation region.
A high-speed transistor comprising: a cutout portion that separates a layer into a plurality of lattices parallel to a direction connecting the source and drain; and a gate electrode formed to fill the cutout portion. .