JPH0238978A - Scan path circuit for integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the quantity of hardware by composing the scan path circuit of a shift register latch for input and output and a shift register latch stored with a microprogram for controlling the input and output of data of said input/output shift register latch. CONSTITUTION:The integrated circuit 100 equipped with logic circuit blocks 6a-6c and input/output registers 5a-5d and 7a-7c is provided with the microprogram and input/output shift register latches 11 and 12. Then when data is inputted from a scan-in terminal 1 to the input side shift register 12a, a microcode for controlling which logic block the scan-in data is inputted is inputted to the shift register 11 to control gates 9, 13, and 14 according to the microcode. Consequently, the scan path circuit consists of three shift registers and the quantity of the hardware is reducible.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a circuit configuration for realizing a so-called scanvase design for the purpose of testing integrated circuits, ie, LSI, VLSI, etc.

[Conventional technology]

BACKGROUND ART A test to determine whether a logic circuit integrated in an integrated circuit such as an LSI or a VLSr is functioning normally is an indispensable test during the manufacture of an integrated circuit.

For this purpose, a circuit configuration known as a so-called scanvase design is conventionally known.

FIG. 4 is a schematic diagram showing the configuration of an integrated circuit employing the above-described scan canvas design.

In the figure, 100 indicates an integrated circuit.

1 is a scan-in terminal as an external input terminal, into which test pattern data is input.

Reference numeral 2 denotes a scan-out terminal as an output terminal, from which final test result data is output.

Reference numeral 3 denotes a scan mode terminal, into which a mode signal for controlling the operation mode of the circuit integrated on the integrated circuit 100 is input.

4 is a scan clock terminal, to which a test clock pulse is supplied during testing.

5a, 5b, 5c, and 5d are shift register latches, each of which receives the test pattern data input from the scan-in terminal 1 and holds it.

6a, 6b, and 6c are logic circuit blocks, respectively;
This is the test target for the Scanvase circuit.

7a, 7b, 7c are shift register latches;
Each of the test result data output from the logic circuit blocks 6a, 8b, and 6c is held.

Here, shift register latches 5a, 5b, 5c, 5d
, 7a.

7b and 7c are normal operations as LSI components;
That is, a shift register latch is used for two operations: a load operation and an operation as a component of a scan canvas circuit, that is, a shift operation.
A simple register may be used as a component of I.

8 is a scan bus, which is used as a data bus during testing. This scan canvas 8 is connected in series from the scan-in terminal 1 to the shift register latches 5a+5b, 5c, 5d and shift register latches 7g+7b, 7ctl-to the scan-out terminal 2.

The operation of such a conventional scan canvas circuit is as follows. Incidentally, FIG. 5 is a timing chart thereof.

The operation is divided into three stages, phases 0, 1.2, and the first phase O is input of test pattern data, that is, scan-in.

In this phase O, first, the mode signal S? is input to the scan mode terminal 3? 'LD scan mode ("1
') as shift register latches 5a, 5b, 5c,
5d and shift register latches 7a, 7b, and 7c are placed in a state where only a shift operation is performed. Then, serial test pattern data Sl is input from the scan-in terminal l, and scan clock SCK is input from the scan clock terminal 4.
Enter. Thereby, the test pattern data SI is transmitted to the shift register latches 5a, 5b, 5 connected in series on the scan canvas B in synchronization with the scan clock SCK.
c, 5d and shift register latches 7a, 7b, and 7c. Therefore, by appropriately setting the number of clocks of the scan crofter SCK, the valid data included in the test pattern data SI can be shifted to the desired shift register latch, and the desired test pattern data can be transferred to the scan canvas 8. It can be set to any shift register latch 5a (5b, 5c, 5d) via the register.

With the above steps, scan-in is completed (at time T1 in the timing chart of FIG. 5).

Note that in this phase 0, the test result data SO output from the scan-out terminal 2 is meaningless data.

In the next phase 1, the mode signal SMD input to the scan mode terminal 3 is set to load mode (“0”), and the shift register latches 5a, 5b+5c+5d and shift register latches 7a, 7b, 7c are operated as normal without performing a shift operation. The state is such that only the loading operation is performed. Then, the scan clock S input from the scan crofter terminal 4
In phase O, one of the shift register latches 5a (5b, 5c.

5d) is applied to any of the logic circuit blocks 6a (6b, 6c) to be tested.
) is operated, and the output of the operation result, that is, the test result data SO, is sent to one of the shift register latches 7a.
(7b, 7c) (T2 in the timing chart of FIG. 5).

In Phase 2, as in Phase 1, the mode signal SMD input to the scan mode terminal 3 is set to scan mode ("1"), and the shift register latches 5a, 5b, 5
c, 5d and shift register latches 7a, 7b, and 7c are in a state where only a shift operation is performed. Then, by inputting an appropriate number of clocks of the scan clock SCK to the scan clock terminal 4, the test result data SO stored in either shift register rafter a (7b, 7c) is synchronized with this in phase 2. It is output as serial data from the scan out terminal 2 via the scan path 8 (T3 in the timing chart of FIG. 5).

Note that in this phase 2, the scan-in terminal I
The data input from is meaningless data.

[Problem to be solved by the invention]

In the conventional integrated circuit scan path circuit as described above,
It is necessary to form all or a considerable number of the memory elements for input/output to the logic circuit block as shift register latches. However, shift register latches require a large amount of hardware compared to regular registers, so the amount of hardware required for the integrated circuit as a whole increases, or if the amount of hardware is limited, The actual amount of hardware will be reduced.

Such a problem can be solved, for example, by using synchronous data buses 10a, 10b, 1 in an integrated circuit 100 as shown in FIG.
0c and has a configuration in which timing control is performed using tristate buffers 93 to 9e.
The same applies to etc.

The present invention was made in view of such problems,
An object of the present invention is to provide a scan path circuit for an integrated circuit that can avoid an increase in the amount of hardware and effectively utilize integrated elements when configuring the scan path circuit for an integrated circuit.

[Means for Solving the Problems] The scan path circuit of the integrated circuit of the present invention includes an input-side shift register latch for storing test pattern data, an output-side shift register latch for storing test result data, and these shift registers. The control circuit incorporates input-side and output-side gates that control the input and output of data to the latches, and a shift register latch that stores a microprogram for controlling the opening and closing of these gates.

[Effect]

In the scan path circuit of the integrated circuit of the present invention, test pattern data is applied to a desired logic circuit block under the control of a microprogram stored in a shift register latch, and test result data is output.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof.

FIG. 1 is a schematic diagram showing the configuration of an integrated circuit incorporating a scan path circuit according to the present invention.

In FIG. 1, 100 indicates an integrated circuit, which includes logic circuit blocks 6a, 6b, and 5c, input registers 5a, 5b, 5c, and 5d for inputting data to these blocks, and registers for holding output data. output side register 7a of
, 7b, 7c are provided as in the conventional example, but registers 5a, 5b, 5c, 5d and register 7a are provided.
For +7b and 7c, it was necessary to use a shift register latch in a conventional integrated circuit incorporating a scan path circuit, but the present invention differs from that and uses a simple register.

Registers 5b and 5d are connected to a synchronous data bus 10a for data input, and registers 5a and 5c are also connected to data bus 10b. Also, register Ia
, 7b, and Ic are connected to a synchronous data bus 10C for data output via tristate buffers 98°9b+9c, respectively.

Furthermore, the data buses 10a and 1Ob for data input and the data bus IOC for data output are connected via triste buffers 9d and 9e.

The above is a normal configuration for an integrated circuit, and the configuration for forming a scan path circuit will be described below.

In FIG. 1, l is a scan-in terminal as an external input terminal, to which test pattern data is input.

2 is a scan-out terminal as an output terminal, and data of the final test result is output.

Reference numeral 3 denotes a scan mode terminal, into which a mode signal for controlling the operation mode of the circuit integrated on the integrated circuit 100 is input.

4 is a scan clock terminal, to which a test clock pulse is supplied during testing.

11 is a shift register latch, the input terminal of which is connected to the scan-in terminal 1; The shift register latch 11 receives and holds a microprogram that controls the operations of registers, shift register latches, tri-state buffers, etc., which will be described later, in the integrated circuit 100 during testing through the scan-in terminal 1.

12a is an input-side shift register latch whose input terminal is connected to the shift register latch 11 via a path 8a. Also, this input side shift register latch 1
2a to the input side data bus lOa via the tristate buffer 13a, to the output side data bus 10b via the tristate buffer 13b, and further to the third data bus IOC via the tristate buffer 13c. Each is configured to be able to output data.

12b is an output-side shift register latch, the output terminal of which is connected to the scan-out terminal 2 via a path 8b. Also, this output side shift register latch 12a
from the input side data bus IOa via the tristate buffer 14a, and from the tristate buffer 1
4b from the output side data bus 10b, and further via the tri-state buffer 14c to the third data bus I.
The configuration is such that data can be input from the OC.

Next, the operation of the scan path circuit of the integrated circuit of the present invention configured as described above will be explained with reference to the timing chart of FIG.

The operation of the scan path circuit of the integrated circuit of the present invention is divided into three stages, phases 0 and 1.2, as in the conventional example, and the first phase O is the input of test pattern data SI and microprogram code.

In this phase O, first, the mode signal SMD input to the scan mode terminal 3 is set to scan mode ("1"), and the shift register latches 11.12a and 12b are put into a state in which a shift operation is performed. Then, the test pattern and the microprogram code data S2 are inputted as serial data from the scan-in terminal 1, and the scan clock SCK is inputted with an appropriate number of pulses from the scan clock terminal 4. As a result, the test pattern data S
1 can be input to the shift register latch 12a, and the microprogram code can be input to the shift register latch 11 and held therein.

With the above steps, scan-in is completed at Tll in the timing chart of FIG.

Note that the microprogram code held in the shift register latch 11 is stored in any of the registers 5a (5b, 5
register 5a (5b, 5c, 5d), register 7 depending on whether the test target is register 5a (5b, 5c, 5d)
a (7b, 7c) and tristate buffer y 13
a (13b, 13c), 14a (14b.

14c) etc. must be able to be appropriately controlled.

In the next phase I, the mode signal SMD input to the scan mode terminal 3 is set to load mode (“0”), and in phase O, the microprogram held in the shift register latch 11 is started (see Fig. 2). 712) in the timing chart of , as a result, the test pattern data S■ held in the shift register latch 12a on the input side is transferred to the tri-state buffer y 13a (1
3b) Any logic circuit block 6a (6b, 6c) to be tested via the data bus 10a (10b)
(T1 in the timing chart in Figure 2) is applied to the register 5a (5b, 5c, 5d) corresponding
3), and this register 5a (5b, 5c+
Test pattern data S set to any of 5d)
■ is the logic circuit block 6a (6b, 6
c), and the test result data is stored in register 7.
a(7b.

7c) and stored (714 in the timing chart of FIG. 2).

After this, one of the tri-state buffers 9a (9b, 9c) is further controlled according to the microprogram code set in the shift register latch 11, so that the test result data SO is output to the data bus IOC, and further data Output side shift register latch 12 from bus IOC via tri-state buffer 14c
b (T15 in the timing chart in Figure 2)
).

In Phase 2, similarly to Phase I, the mode signal SMD input to the scan mode terminal 3 is set to scan mode (“1”) and the shift register latch 12b on the output side is set to the scan mode (“1”).
The test result data SO stored in is output from the scan out terminal 2 in synchronization with the scan clock SCK. This allows the test results to be observed outside of the integrated circuit 100.

In the above embodiment, the tristate buffers 13a, 13b, 13c, and 14a for the scan path circuit are
, 14b, 14c are controlled by a microprogram set in the shift register latch 11. For example, as shown in FIG.
, 14b+14c have external control terminals 15a,
Control signals XIC, YIC, ZIC, XOC, YOC, from 15b, 15c, 16a, 16b, 16c,
It is also possible to adopt a configuration in which control is performed by giving ZOC.

In this case, although the number of external terminals of the integrated circuit 100 increases, the burden of the microprogram stored in the shift register latch 11 becomes lighter, and the shift register latch 11 can be made smaller.

〔Effect of the invention〕

As described above, according to the scan path circuit of the integrated circuit of the present invention, a shift register latch, which has a large amount of hardware compared to the register, is used for the scan path circuit instead of the register originally required for the integrated circuit. No need 5.
Since it only uses the HIi shift register latch,
It becomes possible to reduce the amount of hardware in an integrated circuit, and if the amount of hardware is constant, it becomes possible to increase the amount of hardware that can be used for actual purposes.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing the configuration of an integrated circuit incorporating a scan canvas circuit according to the present invention, FIG. 2 is a timing chart during a test operation thereof, and FIG. 3 is an integrated circuit diagram showing another embodiment of the present invention. A schematic diagram of the circuit; FIG. 4 is a schematic diagram showing an example of a scan canvas circuit in a conventional integrated circuit; FIG. 5 is a timing chart for explaining its operation; FIG. 6 is a schematic diagram showing another example of an integrated circuit. It is a diagram. ■...Scan-in terminal 2...Scan-out terminal 3...Scan mode terminal 5a, 5b, 5
c, 5d...Register 6a, 6b, 6c...Logic circuit block 7a, 7b, 7cm register 10a,
10b, 10cm data bus 11...Shift register latch 12a...Input end shift register latch 12b...Output side shift register latch 100.
...Integrated circuit Note that the same reference numerals in each figure indicate the corresponding parts.

Claims (1)

[Claims] 1. A plurality of logic circuit blocks, a plurality of buses for transferring data between each of the logic circuit blocks, and a plurality of buses for holding input data from each of these buses to each of the logic circuit blocks. Test pattern data is externally input to each logic circuit block of an integrated circuit including an input register and a plurality of output registers that hold data output from each logic circuit block, and the data is processed. A scan path circuit that tests the function of each logic circuit block using test result data outputted as a result, comprising: an input side shift register latch for holding test pattern data input from outside the integrated circuit; an input-side gate circuit for providing data held in the shift register latch to the input-side register via the bus; an output-side shift register latch for holding test result data; and an output-side shift register latch for holding test result data; an output side gate circuit for supplying the test result data held in the output side register to the output side shift register latch via the bus; and an output side gate circuit for supplying the test result data held in the output side register to the output side shift register latch; and a shift register latch that stores a program for controlling the input gate circuit and the output gate circuit so as to store test result data in the output shift register latch. An integrated circuit scan path circuit featuring: