JPH0238866A - Effective value conversion circuit - Google Patents

Abstract

PURPOSE:To obtain an effective value theoretically with zero error by arranging an absolute value circuit, a first logarithmic conversion circuit, a second logarithmic conversion circuit, a subtraction circuit, an inverse logarithmic conversion circuit, an integration circuit and a timing control circuit. CONSTITUTION:A ¦Sin¦ is outputted from an absolute value circuit 1 and 2 Log ¦Sin¦ is outputted from a first logarithmic conversion circuit 2. On the other hand, an output signal Sout from an integration circuit 4 is converted logarithmically with a second logarithmic conversion circuit 3. A signal 2Log ¦Sin¦-2Log ¦Sout¦ is determined with a computing circuit 4 while an inverse logarithm is determined with an inverse logarithmic conversion circuit 5 and the resulting signals are inputted to an integration circuit 6 to integrate. An integrating operation of the circuit 6 is controlled by a timing control circuit 7. As a result, a signal from the circuit 5 becomes equal to a value as obtained by dividing a square of an input signal by an output signal and an output signal from the circuit 6 becomes proportional to a value obtained by integrating a signal from the circuit 5, thereby enabling the determination of an effective from the output signal.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Use] The present invention relates to an effective value conversion circuit capable of reading effective values in real time.

[Prior art] There are three main conventional methods for determining effective values:
There is one.

The first method is to divide the square value of the input by the feedback output and filter the result.

The second method is to construct a circuit that generates an approximate value and sample it at a timing that minimizes the error.

The third method is to sample the input signal at an arbitrary period, input it into the CPU through an AD converter, and actually calculate the effective value using software.

[Problems to be Solved by the Invention] However, the above conventional method has the following problems.

The first method is effective when the averaging (filtering) time constant is sufficiently long with respect to the period of the lowest frequency, but is not suitable when a fast response is required.

In addition, although the second method can provide a fast response, it has the disadvantage of a large error in principle.

Furthermore, in the third method, the load on the CPU increases and quantization errors occur due to the sampling period and AD conversion.

The present invention has been made in view of the above points, and an object of the present invention is to provide an effective value conversion circuit that can output an effective value with a theoretical error of zero in real time.

[Means for Solving the Problems] Representative effective value conversion circuits according to the present invention are as follows.

That is, the effective value conversion circuit according to the present invention includes an absolute value circuit that performs absolute value conversion of an input signal, and a first logarithmic conversion circuit that performs logarithmic conversion of a signal from the absolute value circuit and doubles the result. , a second logarithmic conversion circuit for performing logarithmic conversion of the output signal, a subtraction circuit for calculating the difference between the signal from the first logarithmic conversion circuit and the signal from the second logarithmic conversion circuit, and a subtraction circuit for calculating the difference between the signal from the first logarithmic conversion circuit and the signal from the second logarithmic conversion circuit; an antilogarithmic conversion circuit for antilogarithmically converting a signal; an integrating circuit for integrating a signal from the antilogarithmic conversion circuit; a sampling signal for reading an output signal from the integrating circuit; and canceling the integrating operation of the integrating circuit. The device includes a timing control circuit that outputs a reset signal for starting the next integration operation.

In addition, there is an absolute value circuit that performs absolute value conversion of the input signal, and a logarithmic conversion of the signal from the absolute value circuit, and the result is converted into 2
A first logarithmic conversion circuit that multiplies the output signal, a second logarithmic conversion circuit that performs logarithmic conversion of the output signal, and a difference between the signal from the first logarithmic conversion circuit and the signal from the second logarithmic conversion circuit. The subtraction circuit to be obtained, the antilogarithm conversion circuit that performs antilogarithm conversion of the signal from the subtraction circuit, the integration circuit that integrates the equal sign from the antilogarithm conversion circuit, and the integration circuit that cancels the integration operation of this integration circuit and performs the next integration. The device includes a reset signal for starting operation and a timing control circuit that outputs a reset signal.

[Operation] According to the above-described means, the anti-logarithmic conversion circuit outputs a signal obtained by dividing the square of the input signal by the output signal. Further, the integration circuit outputs a signal obtained by integrating the signal from the anti-logarithmic conversion circuit. Here, the signal from the integrating circuit is proportional to the effective value.

Therefore, it is possible to immediately obtain the effective value from the signal (output signal) from the integrating circuit.

As a result, it becomes possible to obtain an effective value with zero theoretical error in real time.

[Embodiment] An embodiment of an effective value conversion circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 shows a circuit diagram of the effective value conversion circuit of the first embodiment.

This effective value conversion circuit is, If! Logarithmic conversion circuit 2 of logarithmic equivalence circuit 11, second logarithmic conversion circuit 3. Subtraction circuit 4, anti-logarithmic conversion @i! i5. It consists of an integrating circuit s6 and a timing control circuit 7.

Absolute value circuit 1 consists of operational amplifier A1 and diodes D□, D2
This absolute value circuit converts the absolute value of an input signal.

The first logarithmic conversion circuit 2 includes an operational amplifier A2 and transistors Q, , Q, and the logarithmic conversion circuit 2 performs logarithmic conversion of the signal output from the absolute value circuit 1. ing.

Further, the second logarithmic conversion circuit 3 includes an operational amplifier A and a transistor Q.

This logarithmic conversion circuit 3 performs logarithmic conversion of the signal output from the integrating circuit 6.

The subtraction circuit 4 is composed of a transistor Q (more precisely, the base and emitter of a transistor Q4), and the subtraction circuit 4 receives the signal from the first logarithmic conversion circuit 2 and the second logarithmic conversion circuit. The difference with the signal from 3 is calculated.

The anti-logarithmic conversion circuit 5 includes an operational amplifier A4.

The signal output from the arithmetic circuit 4 is subjected to anti-logarithmic transformation.

Also, the integrating circuit 6 includes an operational amplifier Aff and a capacitor C!
and a transistor Q4, and the integration circuit 6 integrates the signal output from the anti-logarithmic conversion port g5 by the function of the capacitor C1.

On the other hand, the timing control circuit 7 is connected to the comparator A.
, and a two-stage inverting output differentiating circuit 7a.

7b. Here, inverters A, A, which are components of the 1-inverting output unit circuits 7a and 7b
, the output pulses @T□, T2 can be freely set according to the time constant of CR, but in the embodiment, the pulse width T1. T is set to be extremely short.

Note that in this embodiment, a timing control circuit to which a zero cross circuit is applied is used as the timing control circuit.

The timing control circuit 7 configured in this manner receives a signal Ti that is the same as the input signal Sin entering the absolute value circuit 1 or another signal Ti having the same period as the input signal.
Comparator A5 where n is configured as a zero cross circuit
is converted to a square wave signal. Also, 1 inverted output machine @
At vt7a, the signal output from comparator A is differentiated, the rising edge of the signal is taken, and the resulting signal is inverted. This will create a sampling signal.

Further, the inverted output differentiation circuit 7b differentiates the sampling signal, takes the rising edge of the signal, and inverts the resulting signal.

This will create a reset signal. Then, the integration circuit 6 is controlled by this reset signal through the control of a reset switch SW made of a junction type FET. In other words, when the reset signal is at a high level "H", the reset switch SW is opened,
While this reset switch SW is open, in the integration circuit 6, charges corresponding to the signal from the anti-logarithmic conversion circuit 5 are accumulated in the capacitor C□. On the other hand, when the reset signal is at a low level "L11", the reset switch SW is closed and the integration operation of the integration port N6 is canceled.

Next, the operation of this effective value conversion circuit will be explained using the timing chart shown in FIG.

In the timing control circuit 7.

When the signal 5in (Fig. 2 (A)) crosses the zero level, the sampling pulse T□ (Fig. 2 (B)) is output, and following the sampling pulse, the reset pulse T2 (Fig. 2 (C)) is output. is output. And reset pulse T
2, the reset switch SW is closed, and the charge accumulated in the capacitor C is discharged in the integrating circuit 6.

As a result, the value of the output signal from the integrating circuit 6 becomes zero. Next, when the reset switch SW is opened, a charge corresponding to the effective value of the input signal is accumulated in the capacitor C1 in the integrating circuit 6, and an output signal Srm5 corresponding to the accumulated charge is output from the integrating circuit 6 (see Fig. 2). (d)) is output.

Then, with the next sampling pulse T, the output signal 5rl
Ils will be sampled. This makes it possible to obtain the effective value for one period of the fundamental wave of the input signal.

Next, the principle of the effective value conversion circuit of the embodiment will be explained using the block diagram of FIG.

When, for example, an AC input voltage Sin is input to the value circuit 1, the absolute value circuit 1 converts the absolute value of the input voltage Sin, and the absolute value circuit 1 outputs a signal 1sinl. Further, the first logarithmic conversion circuit 2 performs logarithmic conversion of the signals 1sj and nl from the absolute value circuit 1 and doubles the result. Then, this first logarithmic conversion circuit 2
2LoglSinl is output as a signal. −
On the other hand, the output signal S out from the integrating circuit 4 is logarithmically converted by the second logarithmic conversion circuit 3 . Then, the subtraction circuit 4 receives the signal 2Logl from the first logarithmic conversion circuit 2.
Sinl and the signal LoglS from the second logarithmic conversion circuit 3
The difference from outl is calculated, and the result is input to the anti-logarithmic conversion circuit 5. In this anti-logarithm conversion circuit 5, 2Lo g
The antilogarithm of l 5inl −Lo g l 5outl is determined.

Then, the signal is input to an integrating circuit 6 6 and
This signal is integrated by this integration circuit 6.

The integration operation of the integration circuit 6 at this time is performed only while the reset switch SW controlled by the timing control circuit 7 is open.

In the effective value conversion circuit as described above, the AC input voltage Vin is used as the input signal Sin, and the output voltage at that time is Vou.
If the current flowing through t and Ch is □, the current I is the output Log(2LoglSinlL) of the antilogarithmic conversion circuit 5.
ogISoutl), that is, V in2/Vout
Since it is proportional to, I,=KVin”/Vout・
It can be expressed as −(], ). Note that K here is a proportionality constant.

Also, Vout is 1! This is because it is an integral of the flow ■□.

Vout=1/C,/1. dt = (2).

From the above formulas (L) and (2), Vout = K/ C, / (Vin”/ V ou
T) dtIf you solve this using a differential equation.

Vout=v' 2 K/ C1f (Vin2) d
t=v'2KT/CIVin-rms=...(3)
T: The time is fi minutes.

Therefore, by appropriately selecting K and C, Vo
ut represents the true effective value of Vin, and Vou
t (integral waveform of Srn+s) traces the effective value of Vin in real time.6 Therefore, Vout at any given point in time represents the effective value up to that point. Also, the integration time is 1 of the fundamental wave of the input signal Vin.
By sampling the final value of Vout for a period, the effective value for that period can be obtained.

Note that in the above, the AC voltage signal Vi is used as the input signal Sin.
Although the case where n is used has been described, the situation is the same even when an alternating current signal is used.

According to the effective value conversion circuit of the embodiment configured as described above, the following effects can be obtained.

That is, according to the effective value conversion circuit of the above embodiment.

The signal from the antilogarithmic conversion circuit 5 is equal to the square of the input signal divided by the output signal, and the output signal from the integration circuit 6 is proportional to the value obtained by integrating the signal from the antilogarithmic conversion circuit 5. It turns out.

Therefore, it becomes possible to immediately obtain the effective value from the output signal. In this way, the effective value with a theoretical zero error can be obtained in real time. Such an effective value conversion circuit can be used, for example, when controlling a lamp exposure circuit in a copying machine.

Note that, as a method of taking out the output, it is also possible to take the S rms into the microcomputer through an AD converter at the timing of the sample output, or to hold it as a DC signal using a sampling and hold circuit.

In addition, although we have shown an example of a zero-cross circuit as a timing control circuit, if there is no zero level within the integration period or if there are two or more, a detection level other than zero can be used. It goes without saying that the integration period can be set to a period other than one period by, for example,

Furthermore, noise filters, adjustment circuits, etc. may be added to operate the circuit stably and absorb errors caused by the components.

Further, FIG. 4 shows an effective value conversion circuit of a second embodiment.

The configuration of this second effective value conversion circuit is approximately the same as that of the first effective value conversion circuit, but the configuration of the timing control circuit 7 allows the inversion output differentiating circuit to become one.
The points are tiered.

The configuration differs from the effective value conversion circuit of the first embodiment in that a Schmitt trigger circuit 8 is connected to the output side of the integrating circuit 6.

That is, in the effective value conversion circuit of this embodiment, the timing control circuit 7 includes a comparator A and one inverted output differentiating circuit 7b. In this timing control circuit 7, a signal identical to the input signal Sin input to the absolute value circuit 1 or another signal Tin having the same period as the input signal is sent to a comparator A configured as a zero cross circuit, and a square wave signal Further, the signal output from the comparator A is differentiated by the inverting output differentiating circuit 7b, and the rising edge of the signal is taken at step 9, and the resulting signal is inverted. This creates a reset signal. It becomes two.

Further, in the Schmitt trigger circuit 8, the output signal from the integrating circuit 6 is compared with a preset reference value, and when the output signal exceeds the reference value, a high level "H" signal is generated as a control signal. It looks like this.

Various devices are controlled by this high-level control signal.

Note that the other configurations are substantially the same as those in the first embodiment, so the same components are denoted by the same reference numerals and their explanations will be omitted.

Next, the operation of this effective value conversion circuit will be explained using the timing chart shown in FIG.

Timing control episode lol! At t7, signal 5
When in (FIG. 5(A)) crosses the zero level, a reset pulse Tz (FIG. 5(B)) is output. Then, the reset switch SW is closed during the reset pulse T2, and in the integrating circuit 6, the 6 charges MfJ applied to the capacitor C□ are discharged. As a result, the value of the output signal from the integrating circuit vt6 becomes zero. Next, when the reset switch SliV is opened, a charge corresponding to the effective value of the input signal is accumulated in the capacitor C1 in the integrating circuit 6, and an output signal 5rIIIs (Sth
Figure (c)) is output.

Then, in the Schmitt trigger circuit 8, the output signal S rvs from the integrating circuit 6 is successively compared with a preset reference value, and when the output signal S rms exceeds the reference value, a control signal (fifth (second) )) is output. As a result, power supply to an exposure lamp in a copying machine, which controls various devices, is stopped. This power supply stop is performed until the next reset pulse T2.

The second embodiment described above can also achieve the same effect as the first embodiment, but this embodiment also has the advantage of being able to roll to control 1 in real time according to the effective value. Can be done.

In addition, in the second embodiment, a detection level other than zero can be used if there is no zero level within the integration period or if there are two or more occurrences, etc., and so on. Needless to say, modification is possible.

[Effects of the Invention] As described above, the effective value conversion circuit according to the present invention includes an absolute value circuit that performs absolute value conversion of an input signal, and a logarithmic conversion of a signal from the absolute value circuit and converts the result into 2. A first logarithmic conversion circuit that multiplies the output signal, a second logarithmic conversion circuit that performs logarithmic conversion of the output signal, and a difference between the signal from the first logarithmic conversion circuit and the signal from the second logarithmic conversion circuit. A subtraction circuit to be obtained, an antilogarithm conversion circuit that antilogarithmically converts the signal from the subtraction circuit, an integration circuit that integrates the signal from the antilogarithm conversion circuit, and a sampling (go signal) for reading out the output signal from this integration circuit. and a reset (3) to cancel the integration operation of the integration circuit and start the next integration operation.
Since the present invention includes a timing control circuit that outputs a signal and a timing control circuit, it is possible to inexpensively realize a circuit that outputs an effective value with theoretically zero error in real time for any period of any input signal.

In addition, there is an absolute value circuit that performs absolute value conversion of the input signal, and a logarithmic conversion of the signal from the absolute value circuit, and the results are converted into 2
A first logarithmic conversion circuit that multiplies the output signal, a second logarithmic conversion circuit that performs logarithmic conversion of the output signal, and a difference between the signal from the first logarithmic conversion circuit and the signal from the second logarithmic conversion circuit. A subtraction circuit to be obtained, an antilogarithm conversion circuit that performs antilogarithmic conversion of the signal from the subtraction circuit, an integration circuit that integrates the signal from the antilogarithm conversion circuit, and canceling the integration operation of this integration circuit and starting the next integration operation. Since it is equipped with a timing control circuit that outputs a reset signal for starting and a timing control circuit that outputs, it goes without saying that it is possible to obtain the same effect as above, but also the effect that control according to the effective value can be performed in real time. be able to.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a first embodiment of the effective value conversion circuit according to the present invention, FIG. 2 is a timing chart for explaining the operation of the effective value conversion circuit of FIG. 1, and FIG. FIG. 2 is a block diagram for explaining the principle of the effective value conversion circuit shown in the figure. FIG. 4 is a circuit diagram of a second embodiment of the effective value conversion circuit according to the present invention, and FIG. 5 is a timing chart showing the operation timing of the effective value conversion circuit of FIG. 4. 1... Absolute value circuit, 2... First logarithmic conversion circuit, 3... Second logarithmic conversion circuit, 4... Subtraction circuit, 5... Anti-logarithmic conversion circuit. , 6...integrator circuit, 7
...Timing control circuit. 7. Figure 1 Figure 2 Figure 4oi-

Claims (1)

[Claims] 1. An absolute value circuit that performs absolute value conversion of an input signal, a first logarithmic conversion circuit that performs logarithmic conversion of a signal from the absolute value circuit and doubles the result, and an output signal a second logarithmic conversion circuit that performs logarithmic conversion; a subtraction circuit that calculates the difference between the signal from the first logarithmic conversion circuit and the signal from the second logarithmic conversion circuit; and a subtraction circuit that converts the signal from the subtraction circuit into an inverse logarithm. An anti-logarithmic conversion circuit for conversion, an integration circuit for integrating the signal from the anti-logarithm conversion circuit, a sampling signal for reading out the output signal from this integration circuit, and canceling the integration operation of the above-mentioned integration circuit and the next integration operation. An effective value conversion circuit comprising: a reset signal for starting; and a timing control circuit for outputting. 2. The integration operation time of the above integration circuit is the fundamental wave 1 of the input signal.
2. The effective value conversion circuit according to claim 1, wherein the effective value conversion circuit is configured to set the value for a period and read the final value of the output signal at that time. 3. An absolute value circuit that performs absolute value conversion of an input signal, a first logarithmic conversion circuit that performs logarithmic conversion of the signal from the absolute value circuit and doubles the result, and a second logarithmic conversion circuit that performs logarithmic conversion of the output signal. a subtraction circuit for calculating the difference between the signal from the first logarithmic conversion circuit and the signal from the second logarithmic conversion circuit, and an antilogarithmic conversion circuit for antilogarithmically converting the signal from the subtraction circuit. and a timing control circuit that outputs a reset signal for canceling the integration operation of this integration circuit and starting the next integration operation. Features an effective value conversion circuit.