JP2711282B2 - RMS conversion circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an effective value conversion circuit capable of reading an effective value in real time.

[Prior Art] There are the following three main methods for obtaining a conventional effective value.

The first method divides the square of the input by the feedback output,
It is a method of filtering the result.

The second method is a method of assembling a circuit that generates an approximate value and sampling the approximate value at a timing that minimizes an error.

The third method is a method in which an input signal is sampled at an arbitrary cycle, taken into the CPU through an AD converter, and the effective value is actually calculated by software.

[Problems to be Solved by the Invention] However, the above conventional method has the following problems.

The first method is effective when the time constant of the averaging (filtering) is sufficiently long with respect to the cycle of the lowest frequency, but is not suitable when a fast response is required.

Further, the second method can obtain a fast response, but has a disadvantage that an error is large in principle.

Further, in the third method, the load on the CPU increases, and a quantization error due to sampling synchronization and AD conversion occurs.

The present invention has been made in view of the above points, and has as its object to provide an effective value conversion circuit capable of outputting an effective value of zero theoretical error in real time.

[Means for Solving the Problems] A typical effective value conversion circuit according to the present invention is as follows.

That is, the effective value conversion circuit according to the present invention includes an absolute value circuit that performs an absolute value conversion of an input signal, and a first logarithmic conversion circuit that performs a logarithmic conversion of a signal from the absolute value circuit and doubles the result. A second logarithmic conversion circuit for performing logarithmic conversion of an output signal, a subtraction circuit for obtaining a difference between a signal from the first logarithmic conversion circuit and a signal from the second logarithmic conversion circuit, An antilogarithmic conversion circuit for performing antilogarithmic conversion of a signal,
An integration circuit for integrating the signal from the antilogarithmic conversion circuit, a sampling signal for reading out an output signal from the integration circuit, and a reset signal for canceling the integration operation of the integration circuit and starting the next integration operation. And a timing control circuit for outputting the same.

An absolute value circuit for performing an absolute value conversion of the input signal; a first logarithmic conversion circuit for performing logarithmic conversion of the signal from the absolute value circuit and doubling the result; and a second logarithmic conversion circuit for performing logarithmic conversion of the output signal. Logarithmic conversion circuit, a subtraction circuit for obtaining a difference between a signal from the first logarithmic conversion circuit and a signal from the second logarithmic conversion circuit, and an antilogarithmic conversion circuit for performing an inverse logarithmic conversion on a signal from the subtraction circuit And an integration circuit for integrating a signal from the antilogarithmic conversion circuit, and a timing control circuit for outputting a reset signal for canceling the integration operation of the integration circuit and starting the next integration operation. It is.

[Operation] According to the above means, a signal obtained by dividing the square of the input signal by the output signal is output from the antilogarithmic conversion circuit. The integration circuit outputs a signal obtained by integrating the signal from the antilogarithmic conversion circuit. Here, the signal from the integration circuit is proportional to the effective value. Therefore, the effective value can be immediately obtained from the signal (output signal) from the integration circuit. As a result, it is possible to obtain an effective value with zero error in real time and theoretically.

Embodiment An embodiment of an effective value conversion circuit according to the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of an effective value conversion circuit according to the first embodiment.

This effective value conversion circuit includes an absolute value circuit 1, a first logarithmic conversion circuit 2, a second logarithmic conversion circuit 3, a subtraction circuit 4, an antilogarithm conversion circuit 5, an integration circuit 6, and a timing control circuit 7. I have.

The absolute value circuit 1 includes an operational amplifier A ₁ and diodes D ₁ and D ₂ , and the absolute value circuit converts an input signal to an absolute value.

First logarithmic conversion circuit 2 is an operational amplifier A ₂ and the transistor
Q ₁ , Q ₂ and the logarithmic conversion circuit 2
In, the logarithmic conversion of the signal output from the absolute value circuit 1 is performed.

The second logarithmic conversion circuit 3 is adapted is configured to include an operational amplifier A ₄ and the transistor Q _3, the logarithmic converter logarithmic conversion of the signal output from the 3 in the integrating circuit 6 is performed I have.

The subtraction circuit 4 comprises a transistor Q ₄ (more precisely, a base and an emitter of the transistor Q ₄ ). In the subtraction circuit 4, the signal from the first logarithmic conversion circuit 2 and the second logarithmic conversion are used. The difference from the signal from the circuit 3 is determined.

Inverse logarithmic conversion circuit 5 is configured to include an operational amplifier A _4, in the inverse logarithmic conversion circuit 5, the inverse logarithmic conversion of the signal output from the arithmetic circuit 4 is to be carried out.

The integrating circuit 6 includes an operational amplifier A ₃ , a capacitor C _1, and a transistor Q _{4. In the} integrating circuit 6, a signal output from the antilogarithmic conversion circuit 5 is operated by the function of the capacitor C ₁ . Integration is performed.

On the other hand, the timing control circuit 7 is a comparator
A ₅ two stages of inverted output differentiating circuit 7a, and is configured to include a 7b. Here, the pulse widths T ₁ and T ₂ of the outputs of the inverters A ₆ and A ₇ , which are the components of the inverted output differentiating circuits 7 a and 7 b, can be freely set by the time constant of CR. The pulse widths T ₁ and T ₂ are set to be extremely short with respect to the integration operation time. In this embodiment, a timing control circuit to which a zero cross circuit is applied is used as the timing control circuit.

Timing control circuit 7 thus configured
Then, the same signal as the input signal Sin entering the absolute value circuit 1 or another signal Tin having the same cycle as the input signal
There is converted to a square wave signal by the comparator A ₅ which is configured as a zero-cross circuit. Further, the resulting signal with the inverted output differentiating circuit 7a in taking place differential signal output from the comparator A ₅ is the rising edge of the signal taken is inverted. This produces a sampling signal. Further, in the inverted output differentiating circuit 7b, the sampling signal is differentiated, the rising of the signal is taken, and the signal obtained as a result is inverted. This will generate a reset signal. The reset signal controls the integration circuit 6 through the control of the reset switch SW composed of a junction type FET. That is, when the reset signal is at the high level “H”, the reset switch SW is opened. While the reset switch SW is open, the integration circuit 6 stores the electric charge corresponding to the signal from the antilogarithmic conversion circuit 5 in the capacitor. It is adapted to be stored in C _1. On the other hand, when the reset signal is at the low level “L”, the reset switch SW is closed, and the integration operation of the integration circuit 6 is released.

Next, the operation of the effective value conversion circuit will be described with reference to a timing chart shown in FIG.

In the timing control circuit 7, the signal Sin
When (FIG. 2 (A)) crosses the zero level, a sampling pulse T ₁ (FIG. 2 (B)) is output, and a reset pulse T ₂ (FIG. 2 (C)) follows the sampling pulse T ₁ . Is output. The closed reset switch SW between the reset pulse T _2, the accumulated charge is discharged to the capacitor C ₁ in the integrator circuit 6. As a result, the value of the output signal from the integrating circuit 6 becomes zero. Next, reset switch SW
When opened, charges corresponding to the effective value of the input signal to the capacitor C ₁ in the integrator circuit 6 is stored, the output signal SRMS (FIG. 2 (d)) corresponding to the stored charge from the integrating circuit 6 Is output. Then, the output signal Srms is sampled at the next sampling pulse T _1.
Thus, an effective value of one cycle of the fundamental wave of the input signal can be obtained.

Next, the principle of the effective value conversion circuit of the embodiment will be described with reference to the block diagram of FIG.

When, for example, an AC input voltage Sin enters the absolute value circuit 1, the absolute value circuit 1 performs an absolute value conversion, and the absolute value circuit 1 outputs a signal | Sin |. In the first logarithmic conversion circuit 2, the signal | Sin | from the absolute value circuit 1 is logarithmically converted and the result is doubled. The first logarithmic conversion circuit 2 outputs 2Log | Sin | as a signal. On the other hand, the output signal Sout from the integration circuit 4 is logarithmically converted by the second logarithmic conversion circuit 3. Then, the difference between the signal 2Log | Sin | from the first logarithmic conversion circuit 2 and the signal Log | Sout | Input to the circuit 5. In this antilogarithmic conversion circuit 5,
2 The logarithm of Log | Sin | −Log | Sout | is obtained. And
The signal is input to the integration circuit 6. Then, the integration circuit 6 integrates the signal. At this time, the integration operation of the integration circuit 6 is performed only while the reset switch SW controlled by the timing control circuit 7 is open.

The AC input voltage Vin is used as the input signal Sin in the effective value conversion circuit as described above, and the output voltage at that time is Vout, C ₁
If the current flowing through is I ₁ , the current I ₁ is the output Log ⁻¹ (2Log | Sin | −Log | Sout |) of the antilogarithmic conversion circuit 5, that is, Vin ² / Vout
Therefore, it can be expressed as I ₁ = KVin ² / Vout (1). Here, K is a proportional constant.

Also, Vout is because is obtained by integrating the current I _1, the _{Vout = 1 / C 1 ∫I 1} dt ...... (2).

(1), if (2) Vout = K / C 1 ∫ from Equation (Vin ² / Vou _T) dt This solved using a differential _{equation, Vout = √2K / C 1 ∫} (Vin 2) dt = √ 2KT / C ₁ Vin · rms …… (3) T: Integration time.

Therefore, Vout by selecting the K and C ₁ appropriately
Represents the true effective value of Vin, and Vout (integrated waveform of Srms) traces the effective value of Vin in real time. Therefore, Vout at any time represents the effective value up to that time. If the integration time is taken as one cycle of the fundamental wave of the input signal Vin and the final value of Vout is sampled, the effective value for that cycle can be obtained.

Although the case where the AC voltage signal Vin is used as the input signal Sin has been described above, the situation is the same when the AC current signal is used.

According to the effective value conversion circuit of the embodiment configured as described above, the following effects can be obtained.

That is, according to the effective value conversion circuit of the above embodiment, the signal from the antilogarithm conversion circuit 5 is equal to the value obtained by dividing the square of the input signal by the output signal, and the output signal from the integration circuit 6 is the inverse signal. This is proportional to the value obtained by integrating the signal from the logarithmic conversion circuit 5. Thus, the effective value can be immediately obtained from the output signal. In this way, a theoretical effective value of zero error can be obtained in real time.
Such an effective value conversion circuit can be used, for example, when controlling the exposure circuit of a lamp in a copying machine.

As a method of extracting the output, Srms can be taken into a microcomputer through an AD converter at the timing of sampling output, or can be held as a DC signal by a sampling and holding circuit.

Although a zero-cross circuit has been described as an example of the timing control circuit, a detection level other than zero can be used when there is no zero level or two or more times during the integration period. It goes without saying that the integration period can be set to a period other than one cycle by the above-mentioned method.

Furthermore, a nozzle filter, an adjustment circuit, and the like can be added to operate the circuit stably and absorb errors due to components.

FIG. 4 shows an effective value conversion circuit according to the second embodiment.

Although the configuration of the second effective value conversion circuit is substantially the same as the configuration of the first effective value conversion circuit, the configuration of the timing control circuit 7 makes the inverted output differentiating circuit one stage. This is different from the configuration of the effective value conversion circuit of the first embodiment in that the Schmitt trigger circuit 8 is connected to the output side of the integration circuit 6.

That is, in the effective value conversion circuit of this embodiment, the timing control circuit 7 is configured to include a comparator A ₅ and one inverting output differentiating circuit 7b. Then, in the timing control circuit 7, the square wave signal by the comparator A ₅ another signal Tin is configured as a zero-cross circuit having the same signal or the input signal having the same period as the input signal Sin into the absolute value circuit 1 It is converted to, and in the inverted output differentiating circuit 7b, the resulting signal with conducted derivative of the signal output from the comparator a ₅ is the rising edge of the signal taken is adapted to be inverted. This will generate a reset signal.

In the Schmitt trigger circuit 8, the output signal from the integration circuit 6 is compared with a preset reference value, and when the output signal exceeds the reference value, a high-level "H" signal is issued as a control signal. It has become.
Various devices are controlled by the high-level control signal.

The other components are substantially the same as those in the first embodiment, and thus the same reference numerals are given to the same components, and the description thereof will be omitted.

Next, the operation of the effective value conversion circuit will be described with reference to a timing chart shown in FIG.

In the timing control circuit 7, the signal Sin
When (FIG. 5 (A)) crosses the zero level, a reset pulse T ₂ (FIG. 5 (B)) is output. The closed reset switch SW between the reset pulse T _2, the accumulated charge is discharged to the capacitor C ₁ in the integrator circuit 6. As a result, the value of the output signal from the integrating circuit 6 becomes zero.
Then, opening the reset switch SW, charges corresponding to the effective value of the input signal to the capacitor C ₁ in the integrator circuit 6 is stored, the output signal SRMS (Fifth corresponding to the charges accumulated from the integrating circuit 6 ((C)) is output. Then, the output signal Sr from the integration circuit 6 is output from the Schmitt trigger circuit 8.
ms is sequentially compared with a preset reference value, and the output signal Sr
When ms exceeds the reference value, the control signal (5th
((D)) is output. Thereby, various devices are controlled. For example, power supply to an exposure lamp in a copying machine is stopped. Stop the feeding is performed until the next reset pulse T _2.

Although the same effects as in the first embodiment can be obtained by the above-described second embodiment, further, in this embodiment, an effect that control according to the effective value can be performed in real time can be obtained.

In the second embodiment, various detection levels other than zero can be used in the case where there is no zero level during the integration period or when there are two or more times, for example, as in the first embodiment. It goes without saying that deformation is possible.

[Effects of the Invention] As described above, the effective value conversion circuit according to the present invention
An absolute value circuit for performing an absolute value conversion of an input signal, a first logarithmic conversion circuit for performing logarithmic conversion of a signal from the absolute value circuit and doubling the result, and a second logarithmic conversion circuit for performing logarithmic conversion of an output signal
Logarithmic conversion circuit, a subtraction circuit for obtaining a difference between a signal from the first logarithmic conversion circuit and a signal from the second logarithmic conversion circuit, and an antilogarithmic conversion circuit for performing an inverse logarithmic conversion on a signal from the subtraction circuit An integration circuit for integrating a signal from the antilogarithmic conversion circuit, a sampling signal for reading an output signal from the integration circuit, and a reset for canceling the integration operation of the integration circuit and starting the next integration operation Since the circuit includes the timing control circuit for outputting the signal and the signal, the circuit for outputting the effective value of the theoretically zero error in an arbitrary period of an arbitrary input signal in real time can be realized at low cost.

An absolute value circuit for performing an absolute value conversion of the input signal; a first logarithmic conversion circuit for performing logarithmic conversion of the signal from the absolute value circuit and doubling the result; and a second logarithmic conversion circuit for performing logarithmic conversion of the output signal. Logarithmic conversion circuit, a subtraction circuit for obtaining a difference between a signal from the first logarithmic conversion circuit and a signal from the second logarithmic conversion circuit, and an antilogarithmic conversion circuit for performing an inverse logarithmic conversion on a signal from the subtraction circuit And an integration circuit that integrates a signal from the antilogarithmic conversion circuit, and a timing control circuit that releases an integration operation of the integration circuit and outputs a reset signal for starting the next integration operation. As a matter of course, the same effect as described above can be obtained, and further, an effect that control according to the effective value can be performed in real time can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the effective value conversion circuit according to the present invention, FIG. 2 is a timing chart for explaining the operation of the effective value conversion circuit of FIG. 1, and FIG. FIG. 4 is a block diagram for explaining the principle of the effective value conversion circuit shown in FIG. 4. FIG. 4 is a circuit diagram of a second embodiment of the effective value conversion circuit according to the present invention. FIG. 5 is an effective value conversion circuit shown in FIG. 5 is a timing chart showing the operation timing of FIG. 1 ... absolute value circuit, 2 ... first logarithmic conversion circuit, 3 ...
2nd logarithmic conversion circuit, 4 ... subtraction circuit, 5 ... antilogarithmic conversion circuit, 6 ... integration circuit, 7 ... timing control circuit.

Claims (3)

(57) [Claims] 1. An absolute value circuit for performing an absolute value conversion of an input signal, a first logarithmic conversion circuit for performing logarithmic conversion of a signal from the absolute value circuit and doubling the result, and a logarithmic conversion of an output signal. A second logarithmic conversion circuit, a subtraction circuit for calculating a difference between a signal from the first logarithmic conversion circuit and a signal from the second logarithmic conversion circuit, and an inverse logarithmic conversion of a signal from the subtraction circuit. A logarithmic conversion circuit, an integration circuit for integrating a signal from the antilogarithmic conversion circuit, a sampling signal for reading out an output signal from the integration circuit, canceling the integration operation of the integration circuit, and starting the next integration operation And a timing control circuit that outputs a reset signal for resetting. 2. The effective value according to claim 1, wherein the integration operation time of the integration circuit is set to one cycle of the fundamental wave of the input signal, and the final value of the output signal at that time is read. Conversion circuit. 3. An absolute value circuit for performing an absolute value conversion of an input signal, a first logarithmic conversion circuit for performing logarithmic conversion of a signal from the absolute value circuit and doubling the result, and a logarithmic conversion of an output signal. A second logarithmic conversion circuit, a subtraction circuit for calculating a difference between a signal from the first logarithmic conversion circuit and a signal from the second logarithmic conversion circuit, and an inverse logarithmic conversion of a signal from the subtraction circuit. A logarithmic conversion circuit, an integration circuit for integrating the signal from the antilogarithmic conversion circuit, and a timing control circuit for releasing the integration operation of the integration circuit and outputting a reset signal for starting the next integration operation. Effective value conversion circuit characterized by the above-mentioned.