JPH0238646U - - Google Patents
Info
- Publication number
- JPH0238646U JPH0238646U JP11580388U JP11580388U JPH0238646U JP H0238646 U JPH0238646 U JP H0238646U JP 11580388 U JP11580388 U JP 11580388U JP 11580388 U JP11580388 U JP 11580388U JP H0238646 U JPH0238646 U JP H0238646U
- Authority
- JP
- Japan
- Prior art keywords
- bus
- data
- circuit system
- latch means
- clock pulse
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 1
Landscapes
- Information Transfer Systems (AREA)
Description
第１図は従来の計時機能付小型電子式計算機の
回路構成を示すブロツク図、第２図は第１図の回
路におけるタイムチヤート、第３図および第４図
はこの考案の一実施例を示すもので、第３図はこ
の考案を適用した計時機能付小型電子式計算機の
要部の回路構成を示す図、第４図は第３図の回路
におけるタイムチヤートである。
１…第１の回路系、２…第２の回路系、３…キ
ー入力部、４…制御部、５…記憶部、６…演算部
、７…表示部、８…第１発振回路、９…クロツク
タイミング発生部、１０…計時部、１１…第２発
振回路、１２…計時用クロツクタイミング発生部
、１３…非同期データ転送制御装置。
Fig. 1 is a block diagram showing the circuit configuration of a conventional small electronic calculator with a timekeeping function, Fig. 2 is a time chart of the circuit of Fig. 1, and Figs. 3 and 4 show an embodiment of this invention. FIG. 3 is a diagram showing the circuit configuration of the essential parts of a small electronic calculator with a timekeeping function to which this invention is applied, and FIG. 4 is a time chart of the circuit of FIG. 3. DESCRIPTION OF SYMBOLS 1... First circuit system, 2... Second circuit system, 3... Key input section, 4... Control section, 5... Storage section, 6... Arithmetic section, 7... Display section, 8... First oscillation circuit, 9 . . . clock timing generation unit, 10 . . . time measurement unit, 11 . . . second oscillation circuit, 12 .
Claims (1)
と、上記第１のクロツクパルスより高速の第２の
クロツクパルスで動作する第２の回路系とを有す
る電子機器において、 上記第１の回路系からのバスのデータを夫々異
なるタイミングで一時記憶する第１および第２の
ラツチ手段と、 この第１のラツチ手段に一時記憶されたデータ
と第２のラツチ手段に一時記憶されたデータとを
比較する比較手段と、 この比較手段からの出力に応じて上記第１のラ
ツチ手段または第２のラツチ手段からのバスと上
記第１の回路系からのバスの何れか一方を選択す
るバス選択手段と、 このバス選択手段により選択されたバスのデー
タを記憶する記憶手段と を具備したことを特徴とする非同期データ転送
制御装置。[Claims for Utility Model Registration] An electronic device having a first circuit system that operates with a first clock pulse and a second circuit system that operates with a second clock pulse faster than the first clock pulse, First and second latch means temporarily store bus data from the first circuit system at different timings, and data temporarily stored in the first latch means and data temporarily stored in the second latch means. a comparison means for comparing the data from the first latch means or the second latch means, and a bus from the first circuit system according to the output from the comparison means; What is claimed is: 1. An asynchronous data transfer control device comprising: bus selection means for selecting a bus; and storage means for storing data on a bus selected by the bus selection means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11580388U JPH0238646U (en) | 1988-09-02 | 1988-09-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11580388U JPH0238646U (en) | 1988-09-02 | 1988-09-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0238646U true JPH0238646U (en) | 1990-03-14 |
Family
ID=31357782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11580388U Pending JPH0238646U (en) | 1988-09-02 | 1988-09-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0238646U (en) |
-
1988
- 1988-09-02 JP JP11580388U patent/JPH0238646U/ja active Pending
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