JPH0238640U - - Google Patents

Info

Publication number
JPH0238640U
JPH0238640U JP11404088U JP11404088U JPH0238640U JP H0238640 U JPH0238640 U JP H0238640U JP 11404088 U JP11404088 U JP 11404088U JP 11404088 U JP11404088 U JP 11404088U JP H0238640 U JPH0238640 U JP H0238640U
Authority
JP
Japan
Prior art keywords
data
system memory
storing
input
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11404088U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP11404088U priority Critical patent/JPH0238640U/ja
Publication of JPH0238640U publication Critical patent/JPH0238640U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案に係るデータの記憶保護装置の
一実施例を示すブロツク構成図、第２図はこの記
憶保護装置においてそのデータの書き込み処理動
作を示すフローチヤート、第３図は通常考えられ
るデータの記憶保護方式の一例を示すブロツク構
成図である。 １……ＣＰＵ、４……システムメモリ、５……
ＲＡＭパツク、４―１，５―１……パリテイビツ
ト記憶部、６……ＥＥＰＲＯＭパツク、７，８…
…バツフア。 Fig. 1 is a block configuration diagram showing an embodiment of the data storage protection device according to the present invention, Fig. 2 is a flowchart showing the data write processing operation in this storage protection device, and Fig. 3 is a normally considered one. FIG. 2 is a block configuration diagram showing an example of a data storage protection method. 1...CPU, 4...System memory, 5...
RAM pack, 4-1, 5-1... Parity bit storage section, 6... EEPROM pack, 7, 8...
...Batsuhua.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 供与されるデータをそれに付加されるパリテイ
ビツトと共に記憶するシステムメモリと、このシ
ステムメモリへの供与データを第１のバツフアを
介して分岐入力してその分岐入力データをそれに
付加されるパリテイビツトと共に記憶するＲＡＭ
パツクと、前記システムメモリへの供与データを
第２のバツフアを介して分岐入力しその分岐入力
データを記憶するプグラマブルＲＯＭパツクとを
備えてなるデータの記憶保護装置。 a system memory for storing supplied data together with parity bits appended thereto; and a RAM for branching input of supplied data to the system memory via a first buffer and storing the branched input data together with parity bits appended thereto.
1. A data storage protection device comprising a programmable ROM pack for branching input of data provided to the system memory via a second buffer and storing the branched input data.
JP11404088U 1988-09-01 1988-09-01 Pending JPH0238640U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11404088U JPH0238640U (en) 1988-09-01 1988-09-01

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11404088U JPH0238640U (en) 1988-09-01 1988-09-01

Publications (1)

Publication Number Publication Date
JPH0238640U true JPH0238640U (en) 1990-03-14

Family

ID=31354424

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11404088U Pending JPH0238640U (en) 1988-09-01 1988-09-01

Country Status (1)

Country Link
JP (1) JPH0238640U (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5998399A (en) * 1982-11-27 1984-06-06 Casio Comput Co Ltd Automatic backup system
JPS6366797A (en) * 1986-09-09 1988-03-25 Oki Electric Ind Co Ltd Memory control system
JPS6385952A (en) * 1986-09-30 1988-04-16 Canon Inc Data processor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5998399A (en) * 1982-11-27 1984-06-06 Casio Comput Co Ltd Automatic backup system
JPS6366797A (en) * 1986-09-09 1988-03-25 Oki Electric Ind Co Ltd Memory control system
JPS6385952A (en) * 1986-09-30 1988-04-16 Canon Inc Data processor

Similar Documents

Publication Publication Date Title
JPH0238640U (en)
JPS59214352A (en) Data transmission system
JP2562486B2 (en) Data processing device error handling method
JPS61168439U (en)
JPS6184955U (en)
Maher Representation of case memory for structural design
JPS6178385U (en)
JPS6353192U (en)
JPH044311U (en)
JPS62138271U (en)
JPS63151007U (en)
JPH0267437U (en)
JPS63103188U (en)
JPS63114302U (en)
JPS614242U (en) Image information processing device
JPH03121447U (en)
JPS6325575U (en)
JPS6389143U (en)
JPS62112742U (en)
JPS6380694U (en)
JPH0382440U (en)
JPS63175203U (en)
JPH02149165U (en)
JPS6130107U (en) Flowchart programmable controller
JPS63163543U (en)