JP2562486B2 - Data processing device error handling method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] In a data processing device having a cache memory, a local read / write processor is capable of reading / writing the cache memory when executing error processing.
Regarding the error processing method of the data processing device used as the memory, the data processing device generally uses the instruction from the processor for the purpose of enabling correct error processing when an error occurs in the main storage device. Department is P
The cache memory composed of kilobytes N ways is configured so that it can be used as N × P kilobytes local memory, that is, 1 way of N × P kilobytes local memory, and the error processing is performed by the cache memory. Configured to run.

[Industrial applications]

The present invention has a ROM that stores an error processing program so that the cache memory can be used as a local memory that can be read / written by a processor when executing error processing in a data processing device having a cache memory. The present invention relates to a data processing device error processing method.

When there is a possibility that an error exists in the main storage device, it is not preferable to execute the error processing using the main storage device.

[Conventional technology]

Although error processing is performed to deal with an error, in a data processing device in which a processor has only a main storage device and a cache memory as read / write memory, the error processing is performed as described above. There is no choice but to use the main memory.

[Problems to be Solved by the Invention]

In performing the error processing, even when an error occurs in the main storage device, the main storage device is used as a data area. For this reason, the correctness of the data cannot be guaranteed, and the error processing executed cannot guarantee normal operation.

An object of the present invention is to enable error processing to be correctly executed when an error occurs in the main storage device.

[Means for solving the problem]

FIG. 1 shows the principle configuration of the present invention. In the figure, reference numeral 1 is a processor, 2 is a main storage device, 3 is a ROM, 4 is a cache memory, 5 is a flag, and 6 is a mode setting unit.

ROM3 stores at least an error processing program. The flag 5 is set by the processor 1 by a program. The mode setting unit 6 uses the flag 5
If, for example, is set, the cache memory 4 shown in FIG.
B) RAM--referred to herein as local memory) to be present and accessible to processor 1.

[Work]

When the flag 5 is not set, the mode setting unit 6 uses the illustrated cache memory 4 as a 4-way cache memory, for example. As a result, the processor 1 advances the processing while accessing the cache memory 4. And cache memory 4
When a mis-hit occurs, the main memory 2 is accessed.

However, if the processor 1 sets the flag 5 in the program in executing the error processing, the mode setting unit 6 sets the illustrated cache memory 4 to 8 × 4.
It can be used as [KB] RAM (local memory) (of course, when this use is made, the contents that were present as cache memory are destroyed). That is, the storage area on the illustrated cache memory 4 is used as a data area for executing error processing.

〔Example〕

FIG. 2 shows an address supply mode in one embodiment of the present invention, and FIG. 3 shows an enable signal supply mode in the same case.

Reference numerals 1, 5, and 6 in FIG. 2 correspond to those in FIG. 1, 7-0 to 7-3 are tag portions in the cache memory, and 8 is a data portion in the cache memory (referred to as SRAM in the drawing). Reference numerals 9-0 to 9-3 denote comparison and collation units, and 10 denotes a decoder. Reference numeral 100 in FIG. 2 indicates the format of the address on the address bus. Reference numerals 1, 5, and 6 in FIG. 3 correspond to those in FIG. 1, 11 is a decoder, and 12 is an OR logic circuit.

In the case shown in FIG. 2, 32-bit address information is prepared. Then, under the condition that the flag 5 is not set (the condition used as the cache memory), it operates as follows.

That is, the tag portions 7-i are simultaneously accessed by the 9 bits corresponding to the address 100. The 19-bit data output from each of the tag units 7-0 to 7-3 is collated with the 19-bit content indicated by the address 100 in the comparison and collation units 9-0 to 9-3. If none of them match, a mistake or
It becomes a hit. For example, if the comparison and collation unit 9-1 performs collation, the decoder 10 encodes the data into 2-bit data, and the data is guided to the mode setting unit 6. In the present case, since the flag 5 is not set, the above decoder
The output of 10 is merged with the 11 bits indicated by at address 100 to form a 13-bit address,
The data part (SRAM) 8 of the memory is accessed. Ie 8
If there are four areas in units of [KB], the comparison and collation unit 9
One 8 [KB] unit corresponding to -1 collation is accessed (one word 32 bits).

On the other hand, when the flag 5 is set, the mode setting unit 6 selects the 2 bits indicated by the address 100. As a result, SRAM8 has address 100
It is accessed with 13 bits given by # 2 bit to # 14 bit in. That is, by appropriately giving the 2 bits indicated by the address 100,
The processor 1 can read / write anything on the SRAM 8 given by 8 × 4 [KB].

,, shown in FIG. 3 correspond to the outputs of the comparing and collating units 9-0 to 9-3 shown in FIG. 2, and FIG. 3 corresponds to FIG. ing. 3 shows an enable signal for SRAM when accessing as a cache memory, an enable signal for SRAM when accessing as a local memory, and an enable signal for SRAM. Also shown is # 1 at address 100 shown in FIG.
Represents 5 bits to # 31 bits.

[Effect of the Invention] As described above, according to the present invention, the memory used as the cache memory can be used as the RAM that can be accessed by the processor as appropriate.

[Brief description of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 shows an address supply mode in one embodiment of the present invention, and FIG. 3 shows an enable signal supply mode in the same case. In the figure, 1 is a processor, 2 is a main storage device, 3 is a ROM, 4 is a cache memory, 5 is a flag, and 6 is a mode setting unit.

Claims (1)

(57) [Claims] 1. A main memory (2) and a processor (1)
In a data processing device having a ROM (3) in which at least an error processing program is stored and a cache memory (4) configured in a plurality of ways, the processor (1) can set a flag ( 5), the first mode in which the cache memory (4) is used as a cache memory that operates under the original multiple ways, and the cache memory (4) based on the content of the flag (5). A mode setting section (6) for operating the entire data section of (4) as a one-way memory and giving a second mode for the processor to use as a readable and / or writable local memory is provided. In the error processing for reading and executing the error processing program stored in the ROM (3), Data processor error handling method, characterized in that the error processing, and executable constructed by using the local memory.