JPS5998399A - Automatic backup system - Google Patents

Abstract

PURPOSE:To eliminate the need for a battery for backup by saving the content of an RAM when a power supply is turned off, transferring the storage content of an EPROM to the RAM when the power supply is turned on, and then erasing the EPROM. CONSTITUTION:The turning on/off of a power supply switch SW are detected respectively by circuit 18, 19. The storage content of the RAM12 for user is read out by a detecting signal of power-off and written in the EPROM13 for backup. Further, the content stored in the EPROM13 is read out by the detecting signal of power-on and transferred to the RAM12, and then the content of the EPROM 13 is erased by an ultraviolet ray.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an automatic backup system for backing up memory in an information processing device.

[Prior art and its problems]

In conventional 'information processing devices, the C-M
It uses OS RAM and is backed up by a battery. However, when performing memory bank amplification using a battery as in the conventional method described above, the battery voltage decreases over time, so if the system power is not restored within a certain period of time, the contents of the RAM will be erased. Put it away.

Furthermore, in order to extend the consumption time of the battery, it is necessary to increase the capacity of the battery, and there is a problem that the battery volume increases. Furthermore, since a C-MOS RAM with a large capacity has not yet been put into practical use, there is a problem in that the number of elements increases significantly compared to when a dynamic RAM is used.

[Purpose of the invention]

The present invention has been made in view of the above points, and it is possible to store the memory contents without changing the backup amplifier's storage capacity, and to continue the backup operation even if the system is powered off for a long time. The purpose is to provide an automatic backup system that can.

[Key points of the invention]

The present invention saves the contents of the user memory to an erasable EPROM by turning off the power switch, transfers the contents held in the EP ROMK to the user memory when the power switch is turned on, and then saves the contents of the user memory to an erasable EPROM.
The contents of ROVL are erased to prepare for the next write.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. In the figure, 11 is a CPU, and this CPU 11 is connected via a data bus DB to a dynamic memory I2 and a gPROM (Erasable PROM) for bank up.
13 are connected. And this EPROM1I 1
An ultraviolet m-generating tube 14 is placed close to 3. This ultraviolet generating tube I4 is driven by an ultraviolet driving section 15,
Generates ultraviolet light to erase the memory contents of the EPROM 13.

Further, the CPUIN outputs address data to the address bus AB, and sends the address data to the RA via the address selector 16.
Specify the addresses of MZ2 and EPROVLZ3.

Furthermore, the above C'P U Z Z is the output line lla,
A read command R or a write command W is output from the llb side and applied to the RAM 72 via the selector 17. Also, S
W is a power switch, and the on/off operation of this power switch SW is detected by a power-on detection circuit 18 and a power-off detection circuit 19. The detection signals of the detection circuits 18 and 19 are input to AND circuits 20 and 21, respectively, and are sent via an OR circuit 22 to selectors 26 and 17 as switching signals. The above power-off detection circuit 19
In addition to detecting that the power switch SW is turned off and outputting a detection signal, the controller has a function of maintaining the power of the system until the data transfer process, which will be described later, is completed. Then, the detection signal of the blow-off detection circuit 19 is sent to the write collapse pressure generation circuit 23. This write voltage generation circuit 23 generates a write operation voltage while a detection signal is applied from the power-off detection circuit 19, and
It is supplied to the write enable terminal WE of PRcll3. This nPROVLl 3 is the write enable terminal W
Data can be written while the EK replacement operating voltage is applied. Furthermore, the transfer lock output from the timing signal generation circuit 24 to the output line 24a is input to the AND circuits 20 and 21. The output of the AND circuit 20 is sent to the transfer counter 25 as a count amplifier signal, and the output of the AND circuit 21 is sent to the transfer counter 25 as a countdown signal. This transfer counter 2
The count contents of 5 are sent to R via the address selector 16.
Sent as address data to Alvt[Z2 and PPROlv(J,?).

The above transfer run 25 transfers the memory contents of the RAM 12 to E.
It is used to transfer the contents of the EPROM 13 to the PR card 113 or to the RAM 12, and its count base number is set corresponding to the final address of the RAMZ 2 and the EPROM 13. Further, the transfer counter 25 outputs a read/write instruction signal in synchronization with the counting operation, and the R/? 7 timing signal generation circuit 26. Further, a read/write timing clock output from the timing signal generation circuit 24 to the output line 24b is input to the timing signal generation circuit 26. The R/W timing signal generation circuit 26 is synchronized with the signal from the transfer counter 25, and sets the time and generates a read/write signal according to the signal from the timing signal generation circuit 24. .28. Furthermore, the detection signal of the power-on detection circuit 18 is input to the AND circuit 27, and the detection signal of the power-off detection circuit 19 is input to the AND circuit 28. The outputs of the AND circuits 27 and 28 are output from the selector 17.
The read/write command is input to the RAM 72 via the read/write command. The carry signal output from the transfer counter 25 to the output line 25EL is input to the pivoting section 15 as a drive command, and is also input to the power-on detection circuit 18 as a power-on Jul 4q completion signal. The signal is inputted and further inputted to the K CPU 11 as a reset signal. Further, the borrow signal outputted from the transfer counter 25 to the output input 25b is inputted to the power suit detection circuit 19 as No. 4 indicating the end of the power-off process.

Next, the operation of the above example A will be explained. When the R source switch SW is turned on, the state is detected by the power-on detection circuit 18.
detects and outputs a detection signal. This detection signal is input to the AND circuit 20.27, and is also sent to the selector 16.17 via the OR circuit 22, switching the selector 16 to the transfer counter 25 side, and switching the selector 17 to the AND circuit 27, 2811'! Switch to jl. Since the gate of the AND circuit 20 is opened by the detection signal from the power-on detection circuit 18, the transmission/lid clock output from the timing signal generation circuit 24 to the output line 24a is sent to the I transmission counter 25 by the count amplifier. Input as a signal. Therefore, the count contents of the transfer counter 25 are transferred to the RAM 19 via the address selector 16.
! and is sent to the EPROM 13 as address data. Further, since the AND circuit 270 gate is opened by the detection signal of the power-on detection circuit 18, the signal output from the R/'W timing signal generation circuit 26 is sent from the AND circuit 27 via the selector 17 to the RAIJZ2 as a write command. sent as. On the other hand, since the write operation voltage is not applied to the EPROMZJ from the write α pressure generation circuit 23, it is in the bladder release mode. Accordingly, the contents of the EPROM 123 are sequentially read out according to address data sent from the transfer counter 25 via the address selector 16 and written into the RAMz 2. Then, the contents of the +ll transfer counter 25 are counted up to the final address of RAMZ2 and EPROM13, and when all the contents of the EPROM123 are written to RAMZ2, the output line 25a of the transfer counter 25 is
A carry signal is output from. When the carry signal is output from the transfer counter 25, the ultraviolet ray/magic circuit 15 operates, drives the ultraviolet generator tube 14, and generates ultraviolet rays.
Erase the contents of the EPROM 13. Further, the carry signal output from the transfer counter 25 resets the power-on detection circuit 18 and also resets and starts the CPU I. Above power-on detection 10 path 1
8 is reset, its detection signal becomes "0", closing the gates of AND circuits 20 and 27, and switching selectors 16 and 17 to the CPU II side. Therefore, from now on, RAMZ 2 can be accessed by CPU II.

After finishing the data processing, the power switch S
When W is turned off, the power-off detection circuit 19 detects this state and outputs a detection signal. Furthermore, when the power-off detection circuit 19 detects that the power switch SW is turned off, it maintains the power of the system in a normal state until a borrow signal is sent from the transfer counter 25. The detection signal of the power-off detection circuit 19 is input to the AND circuit 21.28 and the write voltage generation circuit 23, and is also input to the selector 16.17 via the OR circuit 22.
The selector 16 is switched to the transfer counter 25 side, and the selector 17 is switched to the AND circuit z7.28 side. According to the above power-off detection signal, the cyand circuit 28
When the gate of R/W timing signal generation circuit 26 is opened, a signal outputted from R/W timing signal generation circuit 26 is sent to RAV 7.12 via AND circuit 28 and selector 17 as a read command. Also, at this time, the write voltage generation circuit 23 is supplied with the power-off detection signal and supplies the write operation voltage to the write enable terminal WE of the EPROM 13. Therefore, the EPROM 13 enters the write mode.

Furthermore, the AND circuit 2
Since the gate of 1 is tj'A, the transfer lock outputted from the timing signal generation circuit 24 on the output line 24a& is inputted to the transfer counter 25 as a countdown signal. Therefore, the transfer counter 25 performs a primary countdown from the maximum value in synchronization with the transfer lock. Top 8 Kyuun Ha counter 25! Carry F (issue) is cleared by the countdown operation of the Saitama 4 swords, and CPU II and the ffi of the ultraviolet gland ringing unit 15 and 1 work are suspended.
The count contents of the transmission counter 25 are transmitted as address data to RA k, f via the address selector 16.
12 and gPROVLl 3. Therefore, the stored contents of the RA lvi 22 are sequentially P&ed out according to the above address data, and preferential treatment is given to the EPROM 13. Then, the contents of the transfer counter 25 are counted down to "0", and all the contents of the RkM12 are transferred to the gPROM1.
3, a borrow signal is then output from the transfer counter 25 to the output line 25'O and sent to the power-off detection circuit 19. This power-off detection circuit 19 turns off the power of the entire system when the borrow signal is input. When the power switch SW is turned off as described above, note 1 of RkM12. All contents of the mouse are transferred to the EPROM 13 and held until the next power switch SW is turned on.

In addition, in the actual example, EP is used as backup memory.
I changed the ROM once, but other than that, lli:EPHOy/
Electrically Jlrasable PR
OM) may also be used. When this EEFROM is used, ultraviolet;
becomes unnecessary.

〔Effect of the invention〕

As described above, according to the present invention, when the power switch is turned off, the contents of the RAM are saved to the EPROI (or gEPROM), and when the power switch is turned on, the contents held in the FROM are transferred to the RAM. ,
After that, the contents of the EPROM"! or EEPROM were erased to prepare for the next write, so there was no need for a battery for the back-up amplifier, and the g P R'OM father was E E
p ROM vc The stored contents can be retained at any time.

In addition, since the RAV is backed up using an EPROIJ or a BEP ROM, a large-capacity dynamic RA17 can be conveniently used as the RAIJ.

Therefore, even when considering the use of EFROM or EEPROM, the number of memory elements can be reduced compared to the case of using C-MOS RAIJ, making it possible to reduce the cost and make TFL
can be made. Furthermore, FR for back amplifier
By replacing the OM, you can simply change the steel and bank up the same. In other words, EPRO for bank amplifier
By replacing M with EpP, ○V, on which some application software has already been written, the application program starts at the same time as the power is turned on, so that the package software also has other functions.

[Brief explanation of drawings]

The drawing is a circuit diagram showing an embodiment of the present invention. 11...CPU, 12...Dynamic RAM,
13...EPROJ 14...UV generator tube, 1
6゜17... Selector, 18... Power-on detection circuit, 19... Power-off detection circuit, 25... Transfer counter.

Claims (1)

[Claims] In an information processing device, a power-off detection circuit detects that a power switch is turned off, a power-off detection circuit detects that the power switch is turned on, and an erasable gFROM back-amplifies a user memory. , a means for reading out the stored contents of the user memory in response to the power-off detection signal outputted from the power-off detection circuit and writing it into the gPROVLK for the back amplifier; 'i: means for reading out the retained contents and transferring them to the user memory; J) After transferring the contents of EFROM to the user memory by this means
A dead weight rectification system characterized by comprising means for erasing the memory contents of the EFROM.