JPH096747A - Flash memory controller - Google Patents

Abstract

PURPOSE: To provide a flash memory controller with which the erasure sequence of a flash memory can be executed without increasing the load of a CPU. CONSTITUTION: Concerning a microprocessor system for which the flash memory having the specified erasure sequence is arranged in the memory space of the CPU, this system is provided with an erasure start register 51, to which an erasure start flag is set when erasing the flash memory, to be accessed by the CPU, flash memory erasure sequence executing means B for generating an address, data and control signal for executing the erasure sequence of the flash memory, and control means A for turning the CPU to a hold state by outputting a bus request signal to the CPU and for controlling the operating timing of the flash memory erasure sequence executing means B when the erasure start flag of the erasure start register 51 is set.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microprocessor system having a flash memory in a memory space, and more particularly to controlling the flash memory.

[0002]

2. Description of the Related Art Flash memory (flash EEPR
OM: Batch erase type EEPROM) is an ultraviolet erase type EP
It is possible to electrically erase all of the ultraviolet rays in the ROM at once, and it is necessary to apply a voltage higher than a normal 5V power source to erase and write program data, and a circuit for generating such a program voltage is provided. ing. Then, unlike a normal memory access to a RAM or the like, a special erasing or program sequence that requires time for erasing or writing is required.

[0003]

As described above, in the microprocessor system having the flash memory in the memory space, the erasing operation of the flash memory is different from the normal memory access, and the address, data and read / write signals are different. It is necessary to execute a specific erase sequence by a control signal such as. This erasing sequence can be executed by the system software of the CPU, but it takes time as compared with normal memory access such as RAM.

Similarly, in a microprocessor system having a flash memory in a memory space, the program operation of the flash memory is different from a normal memory access, and is specified by an address, data and a control signal such as a read signal and a write signal. The program sequence needs to be executed. This program sequence is C
It can be executed by the system software of the PU, but it takes longer time than the normal memory access such as RAM.

Therefore, there is a problem that the load of the CPU becomes heavy and the CPU is monopolized, so that the throughput of the system is lowered.

Further, in Japanese Patent Laid-Open No. 4-267454, a direct memory access device (DMA controller) capable of automatically transferring complicated data is used to
However, if this technique is applied to a flash memory, it must be compatible with both normal DMA transfer and flash memory DMA transfer. The control of lines and the like becomes complicated and the circuit scale increases.

Therefore, the present invention has been made in order to solve such a problem, and provides a flash memory control device capable of performing an erase sequence of a flash memory without increasing the load on the CPU. The purpose is.

It is another object of the present invention to provide a flash memory control device capable of executing a flash memory program sequence without increasing the load on the CPU.

A further object of the present invention is to provide a flash memory control device having a DMA controller, which can perform a program sequence of a flash memory by transfer between memories without increasing the load and circuit scale of the CPU. It is a thing.

[0010]

According to a first aspect of the present invention, in a microprocessor system in which a flash memory having a specific erase sequence is arranged in the memory space of the CPU, the flash memory is accessed by the CPU and the flash memory is accessed. Erase start register in which an erase start flag is set at the time of erasing, flash memory erase sequence executing means for generating address, data and control signals for performing the erase sequence of the flash memory, and erase start flag of the erase start register Is set, a bus request signal is output to the CPU and C
A control means for controlling the operation timing of the flash memory erase sequence execution means is provided while the PU is in the hold state.

According to a second aspect of the present invention, in a microprocessor system in which a flash memory having a specific program sequence is arranged in the memory space of the CPU, the program is accessed by the CPU and a program start flag is set when the flash memory is programmed. Has a program start register and a register which is accessed by the CPU to set the program data and its program destination address, respectively, and stores the address, data and control signal for performing the program sequence of the flash memory. When the flash memory program sequence executing means to be generated and the program start flag of the program start register are set,
And a control means for outputting a bus request signal to the CPU to put the CPU in a hold state and controlling the operation timing of the flash memory program sequence execution means.

According to a third aspect of the present invention, a flash memory having a specific erase and program sequence is a CP.
In a microprocessor system provided in a memory space of U and provided with a DMA controller, a program start register which is accessed by the CPU and a program start flag is set when programming the flash memory, and accessed by the CPU, An address for performing a program sequence of the flash memory, which has a source address storing program data and a destination address storing the program data and has a register that is incremented for each 1-byte program operation , A flash memory program sequence executing means for generating data and control signals, and a 1-byte program accessed by the CPU to set the number of program bytes When the program byte number register decremented for each operation and the program start flag of the program start register are set, a DMA request signal is output to the DMA controller and the operation timing of the flash memory program sequence execution means is controlled. And a control means for programming the program data at the source address into the flash memory indicated by the destination address by DMA transfer.

[0013]

According to the first aspect of the invention, the flash memory is erased at high speed by performing the erase sequence of the flash memory by hardware, not by software of the CPU.

According to the second aspect of the present invention, program data is written in the flash memory at high speed by executing the program sequence of the flash memory by hardware instead of software of the CPU.

According to the third aspect of the invention, the program data is written into the flash memory at high speed by erasing the flash memory and performing the program sequence by hardware instead of software of the CPU. Therefore, in addition to the effects of the first and second aspects, the control of the address bus, the data bus and the control signal line is facilitated by making the erase and program sequences independent of other DMA transfers.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a main part of a microprocessor system according to an embodiment of the present invention.

In FIG. 1, 1 is a CPU (central processing unit), 2 is a ROM (read-only memory), 3 is a flash memory, 4 is a RAM (readable / writable memory), and 5 is a flash memory controller.

The CPU 1 is a central processing unit that controls the entire apparatus according to a system program stored in the ROM 2 or the flash memory 3. When the flash memory controller 5 asserts the bus request signal, the address bus, the data bus, and the read signal RD
Each control signal line such as B and the write signal WRB is put into high impedance (called hold).

The ROM 2 stores in advance a program that does not change among the system programs that control the entire apparatus.

The flash memory 3 is internally divided into a plurality of memory blocks, has a block array architecture capable of individually erasing each memory block, and determines whether or not the erase or program operation is normally completed. The status register 3a is read. A circuit for generating a high-voltage program voltage required for erasing and programming is also provided. The flash memory 3 stores a program that may be changed or rewritten among the system programs.

The RAM 4 is composed of DRAM and SRAM and serves as a work area used by the system program.

The flash memory controller 5 erases the flash memory 3 and executes a program sequence by hardware, which is conventionally performed by software executed by the CPU 1.

FIG. 2 is a block diagram showing an embodiment of the flash memory controller 5. In the figure,
51 is an erase / program start register, 52 is a timing generator, 53 is a status register decoder, 54 is a program data register, 55 is a data generator, 56
Is an erase / program address register, 57 is a strobe generator, and 55a to 57a are three-state buffers.

The erase / program start register 51 serves as an erase start register in the first embodiment, and serves as a program start register in a second embodiment described later. The register 51 can be accessed by the CPU 1, and each operation is started when the start bit (flag) of the register 51 is asserted.

The timing generator 52 is provided with the register 5 described above.
Generation timing of data, address, strobe signal (read signal, write signal), etc. is generated based on the start bit of 1. Also, it generates a bus request signal that sets the address bus, data bus, and control signal line of the CPU 1 to high impedance.

The status register decoder 53 executes the erase and program sequence to execute the status register 3a.
Content is decoded and the next processing is performed in the timing generation unit 52.
Pass to.

The program data register 54 is a CPU
1 to temporarily store the program data of the second embodiment described later.

The data generator 55 is used for the flash memory 3
And command data for interfacing with the program data of the second embodiment.

Erase / Program Address Register 56
Is accessed by the CPU 1, stores the address of the erase block in the first embodiment, stores the program destination address in the second embodiment, sets the command to the flash memory 3, reads the status register 3a,
An address is generated when a program data write operation is performed.

The strobe generator 57 generates a read signal RDB and a write signal WRB for the flash memory 3.

Three-state buffers 55a, 56a,
Reference numeral 57a controls the outputs of the data generator 55, the address register 56, and the strobe generator 57, and the electrical connection between the data bus, the address bus, and the control signal line. Controlled.

Here, the timing generating section 52 and the status register decoder 53 are used to set claim 1 of the present application.
The control means A of claim 2 is realized. In addition, the data generator 55, the erase address register 56, the strobe generator 57, and the three-state buffers 55a and 56a.
The flash memory erase sequence executing means B of claim 1 is realized by a and 57a. Further, the program data register 54, the data generator 55, the program address register 56, the strobe generator 57 and the three-state buffers 55a, 56a and 57a implement the flash memory program sequence executing means C of claim 2.

Next, the operation of the flash memory controller 5 thus configured will be described with reference to the flowchart of FIG.

In the case of collectively erasing a memory block in the flash memory 3, first the software of the CPU 1 sets the erase block address of the flash memory 3 in the erase address register 56, and the erase start register 5
When the erase start bit of 1 is enabled (turned on), the flash memory controller 5 starts processing according to FIG. 3 (decision 101).

When the erase start bit is enabled, the timing generator 52 generates a bus request signal and C
The address bus, data bus, and control signal line of PU1 are set to high impedance (hold state) (Processing 10)
2).

The timing generator 52 outputs a timing control signal to the data generator 55, the erase address register 56, and the strobe generator 57.
With this control signal, the three-state buffers 55a-5
7a becomes conductive. As a result, the contents of the erase address register 56 set above are output to the address bus, the data generator 55 outputs the erase setup command to the data bus, and the strobe generator 57 generates the write signal WRB to erase. The setup command is written in the flash memory 3 (process 103).

Similarly, the data generator 55 outputs an erase command to the data bus, the strobe generator 57 generates a write signal WRB, and the erase command is written in the flash memory 3 (process 104).

Then, the timing generator 52 releases the bus request signal and opens each bus and control signal line to the CPU 1 (process 105). As a result, the CPU 1 can perform other processing using each bus and the control signal line.

After that, the timing generator 52 counts a predetermined erase operation time, and the flash memory 3
When the erasing operation time necessary for the lapse of time elapses, the timing generation unit 52 generates a bus request signal, and sets each bus of the CPU 1 and the control signal line to high impedance (decision 106 → process 107) as in the case of the above process 102.

Then, the address set in the address register 56 is output to the address bus, the strobe generator 57 generates the read signal RDB, and the flash memory 3
The contents of the status register 3a are read from (processing 1
08).

Thereafter, the timing generator 52 releases the bus request signal and opens each bus and the control signal line to the CPU 1 as in the process 105 (process 109).

Here, the status register decoder 53
The contents of the status register 3a are checked by means of, and if the erasing is completed, the timing generation unit 52 generates a bus request signal and CP
Each bus of U1 and the control signal line are set to high impedance (decision 110 → process 111).

Next, the data generator 55 outputs the read array command to the data bus, the strobe generator 57 generates the write signal WRB, writes the read array command in the flash memory 3, and sets the read mode (process 112). .

Finally, the timing generator 52 releases the bus request signal and opens each bus and the control signal line to the CPU 1 similarly to the process 105 (process 113).

If it is judged in the above decision 110 that the erasing is not completed, the above processing 107 to decision 110 are repeated.

As described above, the flash memory 3 can be erased at high speed by performing the erase sequence of the flash memory 3 by the flash memory controller 5 regardless of the software of the CPU 1. Further, while the flash memory controller 5 is performing the erase sequence, the CPU 1 can perform other processing in parallel, which significantly improves the throughput of the microprocessor system.

Next, the operation of the second embodiment of the flash memory controller 5 will be described with reference to the flowchart of FIG.

When writing program data to an arbitrary address of the flash memory 3, first, the CPU 1
The program destination address of the flash memory 3 is set in the program address register 56 by the software of
And the program start bit of the program start register 51 is enabled, the flash memory controller 5 starts processing according to FIG.
1).

When the program start bit is enabled, the timing generator 52 generates a bus request signal, and sets each bus of the CPU 1 and the control signal line to high impedance (process 202).

The timing generator 52 outputs a timing control signal to the data generator 55, the program address register 56, and the strobe generator 57, and the three-state buffer 55 is generated by this control signal.
a to 57a become conductive. As a result, the contents of the program address register 56 set above are output to the address bus, the data generation unit 55 outputs the program setup command to the data bus, and the strobe generation unit 57 generates the write signal WRB and the program The setup command is written in the flash memory 3 (process 203).

Next, the data generator 55 outputs the contents of the program data register 54 set above to the data bus, the strobe generator 57 generates the write signal WRB, and the program data is written in the flash memory 3 ( Process 204).

Then, the timing generator 52 releases the bus request signal and opens each bus and control signal line to the CPU 1 (process 205). As a result, similarly to the above-described embodiment, the CPU 1 can perform other processing using each bus and the control signal line.

After that, the timing generator 52 counts a predetermined program operation time, and when the program operation time required for the flash memory 3 has elapsed, the timing generator 52 generates a bus request signal in the same manner as the processing 202. Then, each bus of the CPU 1 and the control signal line are set to high impedance (decision 206 → process 207).

Then, the address set in the address register 56 is output to the address bus, the strobe generator 57 generates the read signal RDB, and the flash memory 3
The contents of the status register 3a are read from (processing 2
08).

After that, the timing generator 52 releases the bus request signal and opens each bus and control signal line to the CPU 1 as in the process 205 (process 209).

Here, the status register decoder 53
The contents of the status register 3a are checked by, and if the program is completed, the timing generation unit 52 generates a bus request signal as in the above process 202,
Each bus of the CPU 1 and the control signal line are set to high impedance (decision 210 → process 211).

Next, the data generator 55 outputs the read array command to the data bus, the strobe generator 57 generates the write signal WRB, writes the read array command in the flash memory 3, and sets the read mode (process 212). .

Finally, like the processing 205, the timing generator 52 releases the bus request signal and opens each bus and control signal line to the CPU 1 (processing 213).

If the program is not completed in the judgment 210, the processes 207 to 210 are repeated.

As described above, by executing the program sequence of the flash memory 3 by the flash memory controller 5 regardless of the software of the CPU 1, the program data can be written in the flash memory 3 at high speed. While the flash memory controller 5 is performing the above program sequence, the CP
U1 can perform other processing in parallel, and the throughput of the system including the address bus and the data bus is significantly improved.

FIG. 5 is a block diagram showing a main part of a microprocessor system according to a third embodiment of the present invention. The same reference numerals as those in FIG. 1 indicate the same or corresponding parts. In the figure, 1 is a CPU, 2 is a ROM, 3 is a flash memory, 4 is a RAM, 5 is a flash memory controller, and 6 is a DMAC (direct memory access controller).

The flash memory controller 5 erases the flash memory 5 conventionally performed by the CPU 1 and performs a program sequence by hardware. In the present embodiment, the flash memory controller 5 is cascade-connected to the DMAC 6. DMA transfer related to the flash memory 5 is performed.

As is well known, the DMAC 6 performs data transfer without passing through the CPU 1, and performs DMA transfer other than that performed by the flash memory controller 5.

FIG. 6 is a block diagram showing an embodiment of the flash memory controller 5. In the figure,
51 is a program start register, 52 is a timing generator, 53 is a status register decoder, 54 is a program data register, 55 is a data generator, 56a is a source address register, 56b is a destination address register, 57 is a strobe generator, 58 Is an address generator, and 55a, 57a and 58a are three-state buffers.

The program start register 51 is the CPU 1
The operation is started when the start bit of this register 51 is asserted.

The timing generating section 52 uses the register 5
The generation timing of data, address, and strobe signal is generated based on the start bit of 1. Also, the DMAC
6, the DMA request signal DREQ is generated.

The status register decoder 53 operates in the erase and program sequence to execute the status register 3a.
Content is decoded and the next processing is performed in the timing generation unit 52.
Pass to.

The program data register 54 is a DMA
This is a data register that is accessed during transfer and temporarily holds transfer data in order to perform memory-to-memory DMA transfer.

The data generator 55 is used for the flash memory 3
Command data for interfacing with the above and the above program data are generated.

The source address register 56a is a CPU
It is accessed by 1 and stores the source address (transfer source address) at the time of DMA transfer. This register 56a is incremented every time one memory → memory DMA transfer is completed.

Destination address register 56
b is accessed by the CPU 1 and stores a destination address (transfer destination address) at the time of DMA transfer. This register 56b also has one memory → D between memory
It is incremented each time MA transfer is completed.

The address generator 58 generates the above addresses for command setting to the flash memory 3, reading of the status register 3a, and memory-to-memory DMA transfer operation.

The strobe generator 57 generates a read signal RDB and a write signal WRB for the flash memory 3.

Three-state buffers 55a, 57a,
Reference numeral 58a controls the output of the data generator 55, strobe generator 57, and address generator 58 and the electrical connection between the data bus, the address bus, and the control signal line, respectively. Controlled by.

The program byte number register 59 is
It stores the number of bytes of program data accessed by U1 and DMA-transferred. This register 59 is decremented every time one memory → memory DMA transfer is completed.

Here, the timing generator 52 and the status register decoder 53 implement the control means D according to claim 3 of the present application. In addition, the program data register 54, the data generator 55, the source address register 56a, the destination address register 56.
b, the strobe generator 57, the address generator 58, and the three-state buffers 55a, 57a, and 58a implement the flash memory program sequence executing means E of claim 3.

Next, the operation of the flash memory controller 5 thus configured will be described with reference to the flowcharts divided and shown in FIGS.

To transfer the program data from the storage address to the program destination address of the flash memory 3, first, the software of the CPU 1 sets the program destination address of the flash memory 3 in the destination address register 56b and stores the program data. When the address is set in the source address register 56a, the number of program bytes is set in the program byte number register 59, and the program start bit of the program register 51 is enabled, the flash memory controller 5 starts the processing according to FIGS. (Decision 301 in FIG. 7).

When the program start bit is enabled, the timing generator 52 causes the DMA request signal DR
Generates EQ (process 302), DMA from DMAC6
When the acknowledge DACK is enabled, the flash memory controller 5 can use each bus and control signal line (decision 303Y). The address generator 58 outputs the contents of the destination address register 56b set above to the address bus, and the data generator 5
5 outputs the erase setup command to the data bus,
The strobe generator 57 generates the write signal WRB and writes the erase setup command in the flash memory 3 (process 304).

Similarly, the data generator 55 outputs an erase command to the data bus, the strobe generator 57 generates a write signal WRB, and the erase command is written in the flash memory 3 (process 305).

Then, the timing generator 52 releases the DMA request signal DREQ and opens each bus and control signal line to the CPU 1 (process 306). Thereby, the CP
U1 can perform other processing using each bus and control signal line.

Thereafter, the timing generating section 52 counts a predetermined erase operation time, and when the erase operation time required for the flash memory 3 has elapsed, the DMA request signal DREQ is generated in the same manner as the above-mentioned processing 302 (determination 30).
7 → process 308), when the DMA acknowledge DACK is enabled from the DMAC 6, the contents of the destination address register 56b are output to the address bus,
The strobe generator 57 generates a read signal and reads the contents of the status register 3a from the flash memory 3 (decision 309 → process 310).

Then, similarly to the process 306, the DMA request signal DREQ is released, and each bus and control signal line are opened to the CPU 1 (process 311).

Here, the status register decoder 53
Thereby, the status register 3a is checked (decision 312), and if the erasing is completed, the process proceeds to the next process, and if the erasing is not completed, the above processes 308 to 312 are repeated.

Next, the DMA request signal DREQ is generated in the same manner as the above-mentioned processing 302 (processing 313 in FIG. 8), and D
When the DMA acknowledge DACK from the MAC 6 is enabled, the read array command is written in the flash memory 3 and the read mode is set (decision 314 → process 315) in the same manner as the above-mentioned process 304.

The address generator 58 outputs the contents of the source address register 56a set above to the address bus, and the strobe generator 57 outputs the read signal RDB.
And the source data is stored in the program data register 5
Then, DMA transfer is performed to No. 4 (process 316).

Further, the address generator 58 has the destination address register 56b set as described above.
Output to the address bus, the data generator 55 outputs the program setup command to the data bus,
The strobe generator 57 generates the write signal WRB and writes the program setup command in the flash memory 3 (process 317).

Thereafter, the data generator 55 outputs the contents of the program data register 54 to the data bus, the strobe generator 57 generates the write signal WRB, and the program data is written in the flash memory 3 (process 31).
8).

Then, similarly to the process 306, the DMA request signal DREQ is released and each bus and control signal line are opened to the CPU 1 (process 319).

Further, the timing generating section 52 counts a predetermined program operation time, and when the program operation time required for the flash memory 3 has elapsed, the DMA request signal DREQ is generated similarly to the process 302 (decision 320 → FIG. Process 321 of 9).

DMA Acknowledge DA from DMAC6
When the CK is enabled, the status register 3a is read from the flash memory 3 in the same manner as the above-mentioned process 310 (decision 322 → process 323).

Thereafter, the DMA request signal DREQ is released and the buses and control signal lines are opened to the CPU 1 in the same manner as in the process 306 (process 324).

Then, similarly to the judgment 312, the contents of the status register 3a are checked (decision 32).
5) If the program is completed, proceed to the next process. If the program is not completed, the above process 321 to judgment 325.
repeat.

If the program is completed, the above processing 302
Similarly to, a DMA request signal DREQ is generated (process 326). DMA Acknowledge DA from DMAC6
When the CK is enabled, the read array command is written in the flash memory 3 and the read mode is set (decision 327 → process 328) as in the above process 315.

Then, similarly to the process 306, the DMA request signal DREQ is released, and each bus and control signal line are opened to the CPU 1 (process 329).

Next, the program byte number register 59 is decremented, and the source address register 56a and the destination address register 56b are incremented (step 330).

When the program byte number register 59 becomes 0, the processing is terminated, and otherwise the above processing 316 to judgment 331 are repeated.

As described above, the program data can be written in the flash memory 3 at high speed by erasing the flash memory 3 and executing the program sequence by the flash memory controller 5 regardless of the software of the CPU 1. Furthermore, by making the erase and program sequences independent of other normal DMA transfers, the control of the address bus, data bus and control signal lines becomes easy, and the circuit scale can be reduced.

[0100]

As described above, according to the first aspect of the present invention, the erase start register which is accessed by the CPU and in which the erase start flag is set when the flash memory is erased, and the erase sequence of the flash memory are performed. Flash memory erase sequence executing means for generating the address, data and control signals, and when the erase start flag of the erase start register is set, a bus request signal is output to the CPU to put the CPU in a hold state, and And a control means for controlling the operation timing of the flash memory erase sequence execution means,
The flash memory is erased by performing the erase sequence of the flash memory by hardware regardless of the software of U. Therefore, since the flash memory erasing sequence is not performed by software, the flash memory can be erased at high speed. Also, while the erase sequence is being performed by hardware, C
The PU can perform other processing in parallel, which has the effect of improving the system throughput.

According to the invention described in claim 2, CP
The flash memory has a program start register which is accessed by U and in which a program start flag is set when programming the flash memory, and a register which is accessed by the CPU and in which program data and its program destination address are respectively set. When a flash memory program sequence executing means for generating an address, data and a control signal for performing a program sequence and a program start flag of the program start register are set, a bus request signal is output to the CPU and the CPU is held. And a control means for controlling the operation timing of the flash memory program sequence execution means,
The program data is written in the flash memory by performing the program sequence of the flash memory by hardware instead of the software of the CPU. Therefore,
Since the program sequence of the flash memory is not executed by software, the program data can be written into the flash memory at high speed. Further, while the above program sequence is being performed by hardware, the CPU can perform other processing in parallel, which has the effect of improving the throughput of the system including the address bus and the data bus.

Further, according to the invention of claim 3, D
In a system having an MA controller, a program start register which is accessed by a CPU and sets a program start flag when programming a flash memory, a source address which is accessed by the CPU and stores program data, and a destination which stores the program data A flash memory program sequence executing means for generating an address, a data and a control signal for performing a program sequence of the flash memory, which has a register to which a nonation address is set and which is incremented for each 1-byte program operation. A program byte number register which is accessed by the CPU, sets a program byte number, and is decremented for each 1-byte program operation; When the program start flag of the start register is set, DM to the DMA controller
A request signal is output, the operation timing of the flash memory program sequence execution means is controlled, and the program data at the source address is programmed into the flash memory indicated by the destination address by DMA transfer.
The program data is written to the flash memory by erasing the flash memory and executing the program sequence by hardware instead of the software of the PU. Therefore, in addition to the same effects as those of claims 1 and 2, elimination,
By making the program sequence independent of other DMA transfers, it is easy to control the address bus, the data bus, and the control signal line, and the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of a microprocessor system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing first and second embodiments of the flash memory controller of FIG.

FIG. 3 is a flowchart showing the operation of the first embodiment of the flash memory controller.

FIG. 4 is a flowchart showing an operation of the second embodiment of the flash memory controller.

FIG. 5 is a block diagram showing a main part of a microprocessor system according to a third embodiment of the present invention.

FIG. 6 is a block diagram showing an embodiment of the flash memory controller of FIG.

FIG. 7 is a flowchart showing a part of the operation of the flash memory controller of FIG.

8 is a flowchart showing a part of the operation of the flash memory controller of FIG.

9 is a flowchart showing a part of the operation of the flash memory controller shown in FIG.

[Explanation of symbols] 1 CPU 2 ROM 3 Flash memory 4 RAM 5 Flash memory controller 6 DMAC 51 Erase / program start register 52 Timing generator 53 Status register decoder 54 Program data register 55 Data generator 56 Erase / program address register 56a Source Address register 56b Destination address register 57 Strobe generator 58 Address generator 59 Program byte count register 55a to 58a Three-state buffer A, D Control means B Flash memory erase sequence execution means C, E Flash memory program sequence execution means

Claims (3)

[Claims] 1. In a microprocessor system in which a flash memory having a specific erase sequence is arranged in a memory space of a CPU, an erase start register which is accessed by the CPU and an erase start flag is set when the flash memory is erased. A flash memory erase sequence executing means for generating an address, data and control signal for performing an erase sequence of the flash memory; and a bus request signal to the CPU when an erase start flag of the erase start register is set. Output and CPU
And a control means for controlling the operation timing of the flash memory erasing sequence executing means. 2. In a microprocessor system in which a flash memory having a specific program sequence is arranged in a memory space of a CPU, a program start register which is accessed by the CPU and a program start flag is set when programming the flash memory. And a flash memory program sequence execution for generating an address, data, and control signal for performing a program sequence of the flash memory, which has a register which is accessed by the CPU and in which program data and a program destination address thereof are set, respectively. And a program start flag of the program start register is set, a bus request signal is output to the CPU to put the CPU in a hold state and the flash And a control means for controlling the operation timing of the memory program sequence execution means. 3. In a microprocessor system having a flash memory having a specific erase and program sequence arranged in the memory space of the CPU and having a DMA controller, the flash memory is accessed by the CPU and a program is started when the flash memory is programmed. A program start register in which a flag is set, a source address in which the program data is stored and a destination address in which the program data is stored are set by the CPU, and are incremented for each 1-byte program operation A flash memory program sequence executing means for generating an address, data and control signal for performing a program sequence of the flash memory, When the program byte number register that is accessed by the PU, sets the program byte number, and is decremented for each 1-byte program operation, and the program start flag of the program start register are set, the DMA request signal is sent to the DMA controller. And controlling the operation timing of the flash memory program sequence executing means to program the program data at the source address into the flash memory indicated by the destination address by DMA transfer. Flash memory controller.