JPH0237740A - Device for visual comparison and check of wafer - Google Patents

Device for visual comparison and check of wafer

Info

Publication number
JPH0237740A
JPH0237740A JP18744188A JP18744188A JPH0237740A JP H0237740 A JPH0237740 A JP H0237740A JP 18744188 A JP18744188 A JP 18744188A JP 18744188 A JP18744188 A JP 18744188A JP H0237740 A JPH0237740 A JP H0237740A
Authority
JP
Japan
Prior art keywords
wafer
chip
image
signals
comparator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18744188A
Other languages
Japanese (ja)
Inventor
Mamoru Nakahira
中平 守
Ikutarou Wakao
育太朗 若生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP18744188A priority Critical patent/JPH0237740A/en
Publication of JPH0237740A publication Critical patent/JPH0237740A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To perform correctly the visual comparing check of a wafer by putting marks on the wafer by means of signal output for errors in a comparator which outputs differential signals out of image signals. CONSTITUTION:A comparator 10 which compares image output signals given by video cameras 6 and 7 leaves a differential mode as it is and a control device 12 observes the whole region of chips by moving wafer chucks 1 and 2 in parallel on a pedestal 3 by means of control signals 13. When visually defective places are detected, the control device 12 gives control signals 15 to a laser marker 1 6 to put marks on a chip. If no defective places are found after checking the whole surface of its chip, the other chip is checked. In this case, this device makes the wafer chuck 1 move to return to the initial position of such a superior chip and then, the wafer chuck 2 operates independently of the chuck 1 to move to the same position that another superior chip holds. The visual check of a wafer is thus carried out correctly at great speed as well.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体集積回路の製造における拡散を終えたウ
ェハの外観検査に関し、特に良品チップと比較すること
で外観検査を自動的に行うウェハ外観比較検査装置に関
する。
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to the visual inspection of wafers that have completed diffusion in the manufacture of semiconductor integrated circuits, and in particular to the visual inspection of wafers that automatically performs visual inspection by comparing with non-defective chips. This invention relates to a comparative inspection device.

〔従来の技術〕[Conventional technology]

半導体集積回路が製品となり、市場に出荷され、使用さ
れている間に故障する場合がある(以下、これを市場不
良と称す)。市場不良を起こした製品を解析すると3〜
4割程度、集積回路表面に外観上の不良が発見される。
A semiconductor integrated circuit may become a product, be shipped to the market, and break down while being used (hereinafter, this will be referred to as a market defect). Analysis of products that caused market defects shows 3~
Approximately 40% of the time, defects in appearance are found on the surface of the integrated circuit.

−例としては、フォトレジスト工程において、ゴミ、異
物等によって絶縁11’Jの一部が正常に形成されない
ような場合である。この部分には段差が発生するので、
その上の金属配線は段差のところで薄くなってしまう。
- For example, in a photoresist process, a part of the insulation 11'J is not formed properly due to dust, foreign matter, etc. There will be a step in this part, so
The metal wiring above it becomes thinner at the step.

製造当初この金属配線は1を気的につながっているので
、検査をパスするが市場では使用されているうちに、温
度変化等によって起こる機械的ストレスによって断線し
、故障に至る。従来の外観検査は目視によって行ってい
た。
At the time of manufacture, this metal wiring is electrically connected, so it passes inspection, but while it is being used on the market, it breaks due to mechanical stress caused by temperature changes, leading to failure. Conventional appearance inspections were performed visually.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の目視による外観検査では、フォトレジス
ト工程での大雑把な検査(再工事の要否)には良いが、
完成したウェハに対する細い検査はできない。もしそれ
を行うとすれば多大な工数がかかり非現実的なものとな
る。
The conventional visual inspection described above is good for rough inspections during the photoresist process (to determine whether rework is necessary), but
Fine inspection of completed wafers is not possible. If this were to be done, it would require a large amount of man-hours and would be unrealistic.

本発明の目的は前記課題を解決したウェハ外観比較検査
装置を提供することにある。
An object of the present invention is to provide a wafer appearance comparison inspection apparatus that solves the above problems.

〔課題を解決するための手段〕[Means to solve the problem]

前記目的を達成するため1本発明に係るウェハ外観比較
検査装置においては、半導体集積回路が形成されたウェ
ハを装着し、移動及び回転機能を有するウェハ装着装置
と、前記ウェハの表面のパタンを画像信号に変換する装
置と画像信号の差分信号を出力する比較装置と、該比較
装置の誤差分信号出力によってウェハ上に印を付ける手
段とを備えたものである。
In order to achieve the above object, the wafer appearance comparison inspection apparatus according to the present invention mounts a wafer on which a semiconductor integrated circuit is formed, and uses a wafer mounting device having a movement and rotation function to image a pattern on the surface of the wafer. The apparatus includes a device for converting into a signal, a comparison device for outputting a difference signal between image signals, and means for marking a wafer by outputting an error signal from the comparison device.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

(実施例1) 第1図(a)は本発明の実施例1のブロック図、(b)
は台座を示す平面図である。第1図(a)において、1
及び2はウェハを装着するウェハチャック、3はウェハ
チャック1及び2を乗せて移動回転させる台座である。
(Example 1) Figure 1 (a) is a block diagram of Example 1 of the present invention, (b)
is a plan view showing the pedestal. In Figure 1(a), 1
and 2 are wafer chucks on which wafers are mounted, and 3 is a pedestal on which the wafer chucks 1 and 2 are placed and moved and rotated.

4は比較基準用の良品ウェハ、5は被検査用ウェハであ
る。6及び7はウェハ表面を拡大して写し出すビデオカ
メラ、8及び9がそれぞれの画像信号である。lOはコ
ンパレータでビデオカメラ6及び7からの画像出力信号
を比較するコンパ、レータであり、11は比較後の差分
出力信号である。12は制御装置であり、13は台座3
への制御信号でウェハチャック1及び2の回転、移動の
制御用のものである。14はコンパレータへの制御信号
で、コンパレータの13作を制御するものであり、この
信号に基づいてコンパレータ1oは中側像信号8と9の
差分を出力するモード、(の画像信号8をマスクして画
像信″−f9を出力するモード、(,3)両像信号9を
マスクして画像信号8を出力するモードの3モードの内
ひとつを選択する。16は外観比較検査結果が不良と判
定されたチップに印を付けるレーザマーカである。】5
は制御装置612がらレーザマーカ16への制御信号で
ある。
4 is a good wafer for comparison reference, and 5 is a wafer to be inspected. 6 and 7 are video cameras that enlarge and photograph the wafer surface, and 8 and 9 are respective image signals. 10 is a comparator which compares the image output signals from the video cameras 6 and 7, and 11 is a differential output signal after comparison. 12 is a control device, 13 is a pedestal 3
This control signal is used to control the rotation and movement of the wafer chucks 1 and 2. 14 is a control signal to the comparator, which controls the 13 operations of the comparator. Based on this signal, the comparator 1o outputs the difference between the middle image signals 8 and 9, and masks the image signal 8 of (). Select one of the following three modes: (, 3) a mode in which both image signals 9 are masked and the image signal 8 is output. It is a laser marker that marks the chip that has been removed.】5
is a control signal sent from the control device 612 to the laser marker 16.

次に4’l+作について説明する。Next, I will explain the 4'l+ work.

(1)軸合せ 台座−ヒのY軸及びY軸(第1図参照)にウェハの方向
を合せる。制御装置12は制御信号14によってコンパ
レータ10を画像(3号8のみ出力するモードを選択し
てウェハ4の画像をみる。制御信号13によってウェハ
チャック1を回転してウェハ4上のチップ境界線をY軸
及びY軸に平行になるように合せる。次に制御信号14
によって画像信号9を出力するモードを選択してウェハ
5の軸合せをウェハ4の場合と同様に行う。
(1) Align the direction of the wafer with the Y-axis and Y-axis of the pedestal (see FIG. 1). The control device 12 uses the control signal 14 to select the mode in which the comparator 10 outputs an image (No. 3 and 8 only) to view the image of the wafer 4. The control device 12 rotates the wafer chuck 1 based on the control signal 13 to detect the chip boundary line on the wafer 4. Align it so that it is parallel to the Y axis and the Y axis.Next, control signal 14
The mode for outputting the image signal 9 is selected, and the axis alignment of the wafer 5 is performed in the same manner as for the wafer 4.

(2)位置合せ pめjji択しである比較基準用ウェハ4の中の良品チ
ップと被検査ウェハ5の中の−っのチップと位置合せを
行う。先ず、制御装置】2は制御信号14によってコン
パレータ10に画像信号8(ウェハ4の画像)を出力す
るモードにし、ウェハチャンク1を移動して上述の良品
チップの角を探す。次に、画像信号9(ウェハ5の画像
)を出力するモードに切替えてウェハチャック2を移動
して被検査ウェハのチップの角(良品チップと同様の角
)に合せる。
(2) Alignment The non-defective chip in the comparison reference wafer 4, which is selected by p, is aligned with the chip in the wafer to be inspected 5. First, the control device 2 is set to a mode in which the image signal 8 (image of the wafer 4) is output to the comparator 10 by the control signal 14, and the wafer chunk 1 is moved to search for the corner of the above-mentioned good chip. Next, the mode is switched to output the image signal 9 (image of the wafer 5), and the wafer chuck 2 is moved to match the corner of the chip of the wafer to be inspected (the same corner as the good chip).

さらにコンパレータを差分を取るモードに切替えて差分
出力力いO′になるようにウェハチャック2を微調整す
る。
Further, the comparator is switched to a mode for taking a difference, and the wafer chuck 2 is finely adjusted so that the difference output force becomes O'.

(3)比較検査 比較基準の良品チップと被検査チップの画像の差分から
不一致箇所(外観不良)の有無を検査する。
(3) Comparison Inspection The presence or absence of a mismatch (defect in appearance) is inspected based on the difference between the images of the non-defective chip of the comparison standard and the chip to be inspected.

コンパレータは差分のモードのままにし、制御装置61
2は制御信号13によって台座3上のウェハチャック1
及び2を平行移動してチップ全域を見る。
The comparator remains in the differential mode and the controller 61
2 is a wafer chuck 1 on a pedestal 3 by a control signal 13.
and 2 in parallel to view the entire chip area.

途中の様子は第2図に示すようになる。第2図において
4は比較基準用のウェハで、4aはその中の良品チップ
である。5は被検査用ウェハ、5aはその中のチップで
ある。4b及び5bはそれぞれビデオカメラ6及び7(
第1図参照)の画像である。5cは被検査チップでの外
観不良である。12は第1図と同じコンパレータであり
、1bが画像4b及び5bの差分画像であり、外観不良
箇所16aのみが検出される。こうした不良を発見する
と、制御装置12は制御信号15をレーザマーカ16に
発して、そのチップに印を付ける。チップ全面を検査し
て何にもなければ、次のチップに移る。その際、ウェハ
チャック1を移動して良品チップの最初の位置(前述の
角の位置)に戻し、ウェハチャック2はウェハチャック
1とは独立に次のチップの良品チップと同様の位置に移
動する。以降は(2)から同様に行う。
The situation along the way is shown in Figure 2. In FIG. 2, 4 is a wafer for comparison reference, and 4a is a good chip among the wafers. 5 is a wafer to be inspected, and 5a is a chip therein. 4b and 5b are video cameras 6 and 7 (
(See Figure 1). 5c is an appearance defect in the chip to be inspected. 12 is the same comparator as in FIG. 1, 1b is a difference image between images 4b and 5b, and only the defective appearance portion 16a is detected. Upon discovering such a defect, the controller 12 issues a control signal 15 to the laser marker 16 to mark the chip. The entire surface of the chip is inspected, and if nothing is found, move on to the next chip. At this time, wafer chuck 1 is moved and returned to the initial position of the good chip (the corner position described above), and wafer chuck 2 is moved independently of wafer chuck 1 to the same position as the next good chip. . From then on, perform the same steps starting from (2).

上記(2)及び(3)を繰返して、被検査ウェハ5上の
全チップについて検査を行う。
By repeating (2) and (3) above, all chips on the wafer 5 to be inspected are inspected.

(実施例2) 第3図は本発明の実施例2のブロック図である。(Example 2) FIG. 3 is a block diagram of a second embodiment of the present invention.

第3図において、17はウェハチャック、3は台座でウ
ェハチャックI7の回転・移動を行う。18はウェハで
ある。 19はビデオカメラ、23はその画像信号出力
である。20は画像信号を記憶する画像記憶装置である
。2Iはその出力信号である。10はコンパレータ、1
1はその出力である。、12は制御装置、24は台座;
3への制御信号、22は画像記憶装置20への制御信号
、14はコンパレータIOへの制御(M 号である。1
Gはレーザマーカ、15は制御装置12からレーザマー
カ16への制御信号である。この実施例2では画像記憶
′!Ai+¥20を設置し、ビデオカメラ及びウェハチ
ャックをそれぞれ1台づつにしたことが特徴である。動
作は次のようになる。
In FIG. 3, 17 is a wafer chuck, and 3 is a pedestal for rotating and moving the wafer chuck I7. 18 is a wafer. 19 is a video camera, and 23 is its image signal output. 20 is an image storage device that stores image signals. 2I is its output signal. 10 is a comparator, 1
1 is its output. , 12 is a control device, 24 is a pedestal;
3, 22 is a control signal to the image storage device 20, 14 is a control signal to the comparator IO (No. M. 1
G is a laser marker, and 15 is a control signal sent from the control device 12 to the laser marker 16. In this second embodiment, image memory'! It is characterized by the installation of Ai + ¥20, one video camera and one wafer chuck. The operation is as follows.

(1)  比較基準チップの画像記憶 先ずウェハチャック17に比較基準用のウェハを置く。(1) Image memory of comparison reference chip First, a wafer for comparison is placed on the wafer chuck 17.

第1の実施例と同様に軸合せを行う。次に制御装置12
は制御信号24及び22によってウェハチャック17を
移動しながら良品チップの全面にわたって画像を画像記
憶装置20に記憶する。
Axis alignment is performed in the same manner as in the first embodiment. Next, the control device 12
While moving the wafer chuck 17 according to the control signals 24 and 22, an image is stored in the image storage device 20 over the entire surface of the good chip.

(2)  比較検査 比較基準用のウェハに替えて被検査ウェハをウェハチャ
ック17に置く。(1)と同様に軸合せを行う。
(2) Comparative Inspection Place the wafer to be inspected on the wafer chuck 17 instead of the wafer for comparison reference. Perform axis alignment in the same way as in (1).

位1(合せは、良品チップの直接の画像に替って画像記
憶装置20に記憶した画像になるだけで、他は第1の実
施例と同様である。次に制御信号24及び22によって
ウェハチャック17を移動しながら、被検査ウェハ上の
チップの画像と画像記憶装置20に記憶された比較基準
の良品チップの画像とを比較して外観検査を行う。第2
図に示すような不良が検存されれば制御装置12は制御
信号■5を発してレーザマーカ16によってチップに印
を付けて1次のチップに移る。不良がなければチップ全
面を検査後、次のチップに移る。
1 (the alignment is the same as in the first embodiment except that the image stored in the image storage device 20 is used instead of the direct image of the good chip. Next, control signals 24 and 22 are used to While moving the chuck 17, an external appearance inspection is performed by comparing the image of the chip on the wafer to be inspected with the image of a good chip as a comparison standard stored in the image storage device 20.Second.
If a defect as shown in the figure is detected, the control device 12 issues a control signal 5, marks the chip with the laser marker 16, and moves on to the first chip. If there are no defects, the entire surface of the chip is inspected and then the next chip is moved on.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は上述の構成をとることによ
り、ウェハの外観検査を正確に、速くできるようになる
。したがって、外観不良が起因の市場不良が発生しなく
なり、市場不良を3〜5割、低減することができる効果
がある。また、この外観検査の歩留りをモニタすること
により、拡散上のゴミの程度、フォトレジスト工程の様
子を知ることができ、拡散の管理にも役立てることがで
きる効果がある。
As explained above, by adopting the above-described configuration, the present invention can accurately and quickly perform visual inspection of wafers. Therefore, market defects due to poor appearance will not occur, and there is an effect that market defects can be reduced by 30 to 50%. Moreover, by monitoring the yield of this visual inspection, it is possible to know the extent of diffusion dust and the state of the photoresist process, which has the effect of being useful for controlling diffusion.

【図面の簡単な説明】[Brief explanation of the drawing]

第1f4(a)は本発明の実施例1を示すブロック図、
(b)は台座を示す平面図、第2図は検査過程を説明す
る図、第33図は本発明の実施例2を示すブロック図で
ある。 1.2・・・ウェハチャック   3・・・台座4 、
5 =、ウェハ       6,7.19・・・ビデ
オカメラ10・・・コンパレータ    J2・・・制
御装置16・・レーザマーカ    13,14.15
・・・制御信号20・・・画像記憶装置
1f4(a) is a block diagram showing Embodiment 1 of the present invention,
(b) is a plan view showing the pedestal, FIG. 2 is a diagram explaining the inspection process, and FIG. 33 is a block diagram showing Embodiment 2 of the present invention. 1.2... Wafer chuck 3... Pedestal 4,
5 =, Wafer 6,7.19...Video camera 10...Comparator J2...Control device 16...Laser marker 13,14.15
...Control signal 20...Image storage device

Claims (1)

【特許請求の範囲】[Claims] (1)半導体集積回路が形成されたウェハを装着し、移
動及び回転機能を有するウェハ装着装置と、前記ウェハ
の表面のパタンを画像信号に変換する装置と画像信号の
差分信号を出力する比較装置と、該比較装置の誤差分信
号出力によってウェハ上に印を付ける手段とを備えたこ
とを特徴とするウェハ外観比較検査装置。
(1) A wafer mounting device that mounts a wafer on which a semiconductor integrated circuit is formed and has a movement and rotation function, a device that converts the pattern on the surface of the wafer into an image signal, and a comparison device that outputs a difference signal between the image signals. 1. A wafer external appearance comparison inspection apparatus comprising: and a means for marking a wafer on the basis of an error signal output from the comparison apparatus.
JP18744188A 1988-07-27 1988-07-27 Device for visual comparison and check of wafer Pending JPH0237740A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18744188A JPH0237740A (en) 1988-07-27 1988-07-27 Device for visual comparison and check of wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18744188A JPH0237740A (en) 1988-07-27 1988-07-27 Device for visual comparison and check of wafer

Publications (1)

Publication Number Publication Date
JPH0237740A true JPH0237740A (en) 1990-02-07

Family

ID=16206118

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18744188A Pending JPH0237740A (en) 1988-07-27 1988-07-27 Device for visual comparison and check of wafer

Country Status (1)

Country Link
JP (1) JPH0237740A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI608584B (en) * 2016-02-15 2017-12-11 Eo科技股份有限公司 Apparatus and method for calibrating a marking position

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI608584B (en) * 2016-02-15 2017-12-11 Eo科技股份有限公司 Apparatus and method for calibrating a marking position
US10867828B2 (en) 2016-02-15 2020-12-15 Eo Technics Co., Ltd. Marking position correcting apparatus and method

Similar Documents

Publication Publication Date Title
US4938600A (en) Method and apparatus for measuring registration between layers of a semiconductor wafer
US5978078A (en) System and method for detecting particles on substrate-supporting chucks of photolithography equipment
US20020085746A1 (en) Semiconductor wafer on which recognition marks are formed and method for sawing the wafer using the recognition marks
WO2020008838A1 (en) Dicing-tip inspection apparatus
JPH0237740A (en) Device for visual comparison and check of wafer
JPS59154305A (en) Apparatus for cleaning detector head
JPH02170549A (en) Device for comparative inspection of wafer appearance
US20070087274A1 (en) Wiring correction method
JP2005217062A (en) Photo lithography process device and defect inspection device
JPS60120519A (en) Photomask automatic defect inspection device
JPH03135045A (en) External-view comparison inspection apparatus of wafer
JPH07209203A (en) Method and apparatus for inspecting appearance
US20050084778A1 (en) Reticle alignment procedure
JPH06232229A (en) Defect inspection method and device thereof
JPH05259700A (en) Circuit board inspecting apparatus
JPH04340740A (en) Automatic inspection equipment for major defect foreign matter and inspection method
JP2003152037A (en) Method and apparatus for inspecting wafer as well as inspecting infrared imaging unit
JPH05281151A (en) Inspection apparatus for wafer pattern
JPH10246951A (en) Method and device for inspecting defect of reticle
JPS604219A (en) Inspection of mask
JPH06275686A (en) Method and device for manufacturing semiconductor device
KR100509826B1 (en) In-situ pattern inspectable developer and method thereof
JPH036842A (en) Detection of position of lead and bump in tape bonding
JPS596536A (en) Defect inspector
JPH01244304A (en) Outside defect checking method