JP2005217062A - Photo lithography process device and defect inspection device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a photo lithography process device 11 in a photo lithography process step that can specify a cause of fault when a fault is generated in a semiconductor wafer. <P>SOLUTION: The photo lithography process device 11 conducts a photo lithography processing to a substrate through a plurality of steps. An inspection part 17 inspects the presence or absence of fault in a provided substrate, and a conveyance part 15 conveys the substrate processed in the instructed step to the inspection part 17. A control unit 19 controls the conveyance part 15 during normal operation to provide the processed substrate in a step before a specified step to the inspection part 17, in case when only the substrate processed in the specified step among a plurality of steps is provided to the inspection part 17 for inspection, and the inspection part 17 judges that the processed substrate in the specified step has any fault. A fault specifier 49 specifies a step generating a fault on the basis of the decision results of a decision part in a fault finding mode. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a photolithography process apparatus, and more particularly to a photolithography process apparatus used for photolithography.

  Photolithography technology is used for processing a fine pattern when manufacturing a semiconductor device such as an IC or LSI. Photolithography generally refers to a process in which a fine circuit pattern is baked onto the surface of a semiconductor wafer using photographic technology.

  FIG. 6 is a flowchart showing processing steps of a conventional typical photolithography process. First, in step S301, the semiconductor wafer is transferred to the loader portion of the resist coater. Then, the process proceeds to the next step S303.

  In step S303, a resist is applied to the surface of the semiconductor wafer. Then, the process proceeds to the next step S305. In step S305, a necessary circuit pattern is transferred onto the resist surface by an exposure device such as a stepper. Then, the process proceeds to the next step S307.

  In step S307, development processing is performed. Specifically, the resist unnecessary for forming the resist pattern is removed from the semiconductor wafer to which the circuit pattern is transferred. After a series of photolithography process operations, the semiconductor wafer is transferred to the unloader unit.

  Product inspection is performed on the semiconductor wafer manufactured through the photolithography process as described above in order to check for defects. The inspection of a semiconductor wafer is generally performed after completion of development or after completion of wiring pattern formation. The inspection is, for example, a sampling inspection, in which a predetermined number of semiconductor wafers are extracted from a plurality of processed semiconductor wafers, and the extracted semiconductor wafers are inspected. The inspection performed on the semiconductor wafer is generally a dimensional inspection using an optical microscope or SEM and an appearance inspection.

As an example of a photolithography apparatus used in such a photolithography process, a photolithography process monitor apparatus that monitors the development state of a resist has been proposed (Patent Document 1). According to this apparatus, defective products can be found in real time by sequentially monitoring products that have completed the development process.
JP-A-5-326391

  However, the photolithography process includes a plurality of processes such as a coating process, an exposure process, and a development process. Since the conventional photolithographic apparatus performs the inspection of the semiconductor wafer only at the time when the development process is completed, it cannot identify the cause of the abnormality in the semiconductor wafer, that is, the process in which the abnormality has occurred.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a photolithography process apparatus that can identify the cause of an abnormality when an abnormality occurs in a semiconductor wafer in the photolithography process step.

  The photolithography process apparatus of the present invention includes a substrate inspection unit, a substrate providing unit, a control unit, and an abnormality specifying unit. The substrate inspection unit inspects whether the provided substrate is defective. The substrate providing unit causes the substrate inspection unit to inspect the substrate by transporting and providing the substrate processed in the instructed step to the substrate inspection unit among the plurality of steps. In the normal operation mode, the control unit provides only the substrate processed in a predetermined process to the substrate inspection unit among a plurality of processes and inspects the substrate, and the substrate processed in the predetermined process has a defect. In the abnormality detection mode determined by the substrate inspection unit, the substrate providing unit is controlled so that the substrate processed in the step existing before the predetermined step is provided to the substrate inspection unit and inspected. The abnormality identification unit identifies in which process the defect has occurred based on the inspection result of the substrate inspection unit in the abnormality detection mode.

  Further, the control unit may include an inspection process instruction unit, and the abnormality specifying unit may include an abnormal process specifying unit. In the abnormality detection mode, the inspection process instruction section provides the substrate inspection section with the substrates processed in each process in the abnormality detection mode, in order, going back in the processing order of the substrates. Instruct the board provider. If the substrate inspection unit determines that the substrate is not defective, the abnormal process identification unit determines that there is an abnormality in the process immediately after the step determined to be free of defects, and sends the control unit to the substrate inspection unit. Stop providing the board.

  The photolithography process apparatus may further include a recovery process execution unit. The recovery process execution unit performs recovery measures for recovering the process in the process specified by the abnormality specifying unit.

  Further, the predetermined process may be located in the final process among a plurality of processes having a possibility of occurrence of abnormality.

  Further, the present invention is directed not only to a photolithography process apparatus but also to a substrate inspection method. The substrate inspection method includes a first inspection step, a second inspection step, and an abnormality specifying step. In the first inspection step, the substrate processed in a predetermined process among the plurality of processes is inspected for defects. In the second inspection step, when it is determined in the first inspection step that the substrate processed in the predetermined process is defective, the substrate processed in the process existing before the predetermined process is inspected. The abnormality specifying step specifies in which process the defect has occurred based on the inspection result of the second inspection step.

  The photolithographic process apparatus of the present invention normally inspects a substrate processed in a predetermined process and inspects a substrate processed in a process existing before the predetermined process when a defect is found in the substrate. Therefore, it is possible to identify the process that caused the abnormality.

  In addition, if the control unit includes an inspection process instruction unit and the abnormality specifying unit includes an abnormal process specifying unit, the number of substrates to be inspected is minimized as compared with the case of inspecting substrates for all processes, The process that is the cause of the abnormality can be identified efficiently.

  Further, if the photolitho process apparatus further includes a recovery process execution unit, it is possible to perform a recovery process for the process identified as the cause of the abnormality.

  With reference to the block diagram shown in FIG. 1, the structure of the photolithographic process apparatus 11 which concerns on one Embodiment of this invention is demonstrated. The photolithography process apparatus 11 includes a production operation unit 13, an inspection unit 17, a control unit 19, and a resist stripping unit 21, and performs photolithography processing and inspection on a semiconductor wafer.

  The production operation unit 13 includes a loader unit 31, a plurality of photolithography processing units 33, and an unloader unit 35. Hereinafter, the case where the photolithography process apparatus 11 includes the application unit 33a, the exposure unit 33b, and the development unit 33c as the photolithography processing unit 33 will be described. In the case where it is not necessary to distinguish the application unit 33a, the exposure unit 33b, and the development unit 33c, these are collectively referred to as the photolithographic processing unit 33. In general, in a photolithography process, a semiconductor wafer is processed in the order of a loader unit 31, a coating unit 33a, an exposure unit 33b, a developing unit 33c, an inspection unit 17, and an unloader unit 35.

  In FIG. 1, solid arrows indicate the flow of signals output from each unit, and dotted arrows indicate the transfer path of the semiconductor wafer. The photolithographic processing unit 33 (the coating unit 33a, the exposure unit 33b, and the developing unit 33c), the inspection unit 17, and the resist stripping unit 21 are connected by the transport unit 15, and the semiconductor wafer is transported to each unit by the transport unit 15. The Hereinafter, each part of the photolithography process apparatus 11 will be described in detail.

  In the loader unit 31, a semiconductor wafer to be processed by the photolithography process apparatus 11 is installed. The semiconductor wafer installed in the loader unit 31 is transferred to the coating unit 33a through the transfer unit 15. The transfer unit 15 is, for example, an extendable arm type transfer machine, and transfers the semiconductor wafer to a predetermined position. The application unit 33a is, for example, a coater, and applies a resist to the semiconductor wafer. The semiconductor wafer coated with the resist is transferred to the exposure unit 33b via the transfer unit 15.

  The exposure unit 33b is an exposure machine that performs exposure using, for example, a stepper method, and transfers a mask pattern onto a semiconductor wafer coated with a resist. The semiconductor wafer onto which the pattern has been transferred is transferred to the developing unit 33c via the transport unit 15. The developing unit 33c develops the resist pattern exposed by the exposure unit 33b. The semiconductor wafer that has been developed is transferred to the inspection unit 17 via the transfer unit 15.

  The inspection unit 17 will be described in detail with reference to FIG. The inspection unit 17 includes an imaging unit 41, a storage unit 45, an image comparison unit 43, a determination unit 47, an abnormality identification unit 49, and a signal generation unit 51. The inspection unit 17 inspects the semiconductor wafer processed in each of the coating unit 33a, the exposure unit 33b, and the development unit 33c, and when an abnormality occurs in the semiconductor wafer, the photolitho processing unit 33 that causes the abnormality. Is identified. Until an abnormality is found in the semiconductor wafer, that is, when the operation of the photolithography process apparatus 11 is normally performed, the inspection unit 17 inspects the semiconductor wafer processed by the developing unit 33c.

  The storage unit 45 is a storage device such as a memory, for example, and stores a model pattern indicating a normal resist pattern after being processed by the developing unit 33c. In addition to this, the storage unit 45 also stores in advance an imaging model pattern of a predetermined portion of the semiconductor wafer immediately after resist application and immediately after exposure. The model data stored in the storage unit 45 is appropriately read and used by the image comparison unit 43 described later. The imaging unit 41 is typically a CCD camera, and images a predetermined portion of the semiconductor wafer. The imaging pattern captured by the imaging unit 41 is passed to the image comparison unit 43.

  FIG. 3A is a diagram schematically illustrating an example of the model pattern 55 stored in the storage unit 45. After development, a wiring pattern 57 similar to the model pattern 55 is formed on a normal semiconductor wafer.

  Returning to the description of FIG. 2, when receiving the imaging pattern from the imaging unit 41, the image comparison unit 43 reads the model pattern 55 from the storage unit 45, compares the imaging pattern with the model pattern 55, and extracts a mismatched portion. Data indicating the mismatched portion extracted by the image comparison unit 43 is output to the determination unit 47. In addition, when the determination unit 47 described later determines that there is an abnormality in the semiconductor wafer, the image comparison unit 43 captures an imaging pattern obtained by imaging the semiconductor wafer after resist coating and after exposure, and an imaging stored in the storage unit 45 in advance. Compare with the model pattern and extract the mismatched part. In this case, particles present in the resist applied to the semiconductor wafer and organic foreign matters in the resist are extracted as inconsistent portions.

  FIG. 3B is a diagram schematically illustrating an example of the imaging pattern 59. In the resist, for example, an abnormal portion 61 such as a particle or a bridge of the resist may occur. When the abnormal portion 61 occurs, a normal resist pattern is not formed in the development process. Therefore, when a wiring is formed by etching or sputtering after development, a normal wiring pattern cannot be formed.

  FIG. 3C is a diagram schematically illustrating an example of the extraction pattern 63 extracted by the image comparison unit 43. The image comparison unit 43 compares the model pattern 55 shown in FIG. 3A with the imaging pattern 59 shown in FIG. 3B to extract the mismatched portion 65 and generate an extraction pattern 63.

  Returning to the description of FIG. 2 again, the determination unit 47 determines whether there is an abnormality in the semiconductor wafer based on the extracted pattern 63 received from the image comparison unit 43. If the determination unit 47 determines that there is no abnormality in the semiconductor wafer, the determination unit 47 instructs the signal generation unit 51 to generate a continuation instruction signal for causing the photolithography process apparatus 11 to continue production. On the other hand, if the determination unit 47 determines that there is an abnormality in the semiconductor wafer, the determination unit 47 instructs the signal generation unit 51 to generate a stop instruction signal for stopping production in the photolithographic process apparatus 11.

  The determination unit 47 determines the determination result when the extraction pattern 63 received from the image comparison unit 43 is extracted based on the imaging pattern 59 obtained by imaging the semiconductor wafer processed by the coating unit 33a or the exposure unit 33c. Is notified to the abnormality specifying unit 49.

  The abnormality identification unit 49 identifies the photolithographic processing unit 33 in which an abnormality has occurred based on the determination result received from the determination unit 47. Specifically, the abnormality specifying unit 49 causes the abnormality to occur in the application unit 33a when there is an abnormality in the semiconductor wafer processed in the application unit 33a and no abnormality exists in the semiconductor wafer processed in the exposure unit 33b. Is identified. In addition, when there is no abnormality in the semiconductor wafer processed by the application unit 33a and there is an abnormality in the semiconductor wafer processed by the exposure unit 33b, the abnormality specifying unit 49 specifies that the exposure unit 33b is the cause of the abnormality. When there is no abnormality in both the semiconductor wafer processed by the coating unit 33a and the semiconductor wafer processed by the exposure unit 33b, the abnormality specifying unit 49 specifies that the developing unit 33c is the cause of the abnormality. When the abnormality identification unit 49 identifies the cause of the abnormality, the abnormality identification unit 49 instructs the signal generation unit 51 to generate a restoration instruction signal for performing the restoration process in the identified photolithography processing unit 33.

  The signal generation unit 51 generates a continuation instruction signal or a stop instruction signal in accordance with an instruction from the determination unit 47. In addition, the signal generation unit 51 generates a recovery signal in accordance with an instruction from the abnormality identification unit 49. The signal generated by the signal generation unit 51 is passed to the control unit 19.

  Returning to the description of FIG. 1, the control unit 19 controls the operation of each photolithography processing unit 33 of the photolithography process apparatus 11 in accordance with the signal received from the signal generation unit 51. Specifically, when the control unit 19 receives a continuation instruction signal, the control unit 19 continues the processing in each photolithography processing unit 33. Moreover, the control part 19 stops the process in each photolitho process part 33, when a stop instruction | indication signal is received.

  The control unit 19 receives the stop instruction signal, stops the processing in each photolithography processing unit 33, and then transfers the semiconductor wafer processed in the coating unit 33 a and the exposure unit 33 b to the inspection unit 17 so as to transfer the semiconductor wafer. Instruct. In this embodiment, after the processing of each photolithography processing unit 33 is stopped, the control unit 19 transfers the semiconductor wafers to the inspection unit 17 in the order after the exposure processing and after the coating processing. That is, after the processing of each photolithographic processing unit 33 is stopped, the semiconductor wafer after the exposure processing is first transferred to the inspection unit, and then the semiconductor wafer after the coating processing is transferred to the inspection unit 17.

  The unloader unit 35 stores a semiconductor wafer on which a series of photolithography processes (here, resist coating, exposure, and development) have been completed. The resist stripping unit 21 regenerates the semiconductor wafer received from the transport unit 15. The semiconductor wafer determined by the determining unit 47 as having an abnormality is transferred to the resist stripping unit 21. The resist stripping unit 21 strips the resist from the semiconductor wafer. The semiconductor wafer that has been subjected to the regeneration process in the resist stripping unit 21 is transferred to the loader unit 31 through the transport unit 15.

  With reference to FIG. 4, the operation of the photolithography process apparatus 11 having the above configuration will be described. In step S <b> 101, after developing the resist of the semiconductor wafer, the semiconductor wafer is placed on the inspection unit 17 by the transport unit 15. Then, the process proceeds to the next step S103.

  In step S103, imaging of the semiconductor wafer after the development processing is performed. The imaging unit 41 images a resist pattern at a predetermined location on the semiconductor wafer. The imaging unit 41 outputs the captured imaging pattern 59 to the image comparison unit 43. Then, the process proceeds to the next step S105.

  In step S105, the images are compared. The image comparison unit 43 reads the model pattern 55 from the storage unit 45, compares the model pattern 55 with the imaging pattern 59 received from the imaging unit 41, and extracts a mismatched portion 65. Then, the process proceeds to the next step S107.

  In step S107, the abnormality of the semiconductor wafer is determined. The determination unit 47 receives the extraction pattern 63 from the image processing unit. Then, the process proceeds to the next step S109.

  In step S109, it is determined whether there is an abnormality in the semiconductor wafer. The determination unit 47 determines whether there is an abnormality in the semiconductor wafer. If No in step S109, that is, if there is no abnormality in the semiconductor wafer, the process proceeds to step S119.

  In step S119, the inspection unit 17 outputs a process continuation instruction to the application unit 33a, the exposure unit 33b, and the development unit 33c. The determination unit 47 instructs the signal generation unit 51 to generate a continuation instruction signal for continuing production as it is. The signal generation unit 51 passes the generated continuation instruction signal to the control unit 19. The continuation instruction signal is transferred by the control unit 19 to the coating unit 33a, the exposure unit 33b, and the developing unit 33c, and the processing in the photolithography process apparatus 11 is continued.

  On the other hand, if Yes in step S109, that is, if there is an abnormality in the resist pattern, the process proceeds to step S111. In step S111, a process stop instruction is output. The determination unit 47 instructs the signal generation unit 51 to generate a stop instruction signal for stopping production. The stop instruction signal generated by the signal generation unit 51 is passed to the control unit 19. When the control unit 19 receives the stop instruction signal, the control unit 19 stops the production of the photolithography process apparatus 11. That is, the processing in the application unit 33a, the exposure unit 33b, and the development unit 33c is stopped. The semiconductor wafer in which the abnormality is found is transferred to the resist stripping unit 21. Then, the process proceeds to the next step S113. In step S113, cause identification processing is performed.

  Details of the subroutine step S113 in FIG. 5 will be described with reference to the flowchart shown in FIG. When the process is stopped, the semiconductor wafer is stopped in each of the coating unit 33a, the exposure unit 33b, and the development unit 33c of the photolithographic processing unit 33, but in step S201, first exposure before the development is performed. Later semiconductor wafer inspection is performed. The control unit 19 instructs the transfer unit 15 to pass the semiconductor wafer on which the exposure process has been completed to the inspection unit 17. When the inspection unit 17 receives the semiconductor wafer after the exposure processing from the transport unit 15, the inspection unit 17 inspects the semiconductor wafer. The inspection is basically the same as the processing performed in steps S <b> 103 and S <b> 105, and the imaging pattern 59 captured by the imaging unit 41 is processed by the image comparison unit 43. The image comparison unit 43 verifies the imaging pattern 59 received from the imaging unit 41, and extracts a mismatched portion 65 if foreign matter is mixed in the resist. Then, the process proceeds to the next step S203.

  In step S203, it is determined whether an abnormality has been detected. The determination unit 47 outputs the determination result to the abnormality specifying unit 49. The abnormality specifying unit 49 determines whether there is an abnormality in the exposure unit 33b. If No in step S203, that is, if no abnormality is detected from the exposed semiconductor wafer, the process proceeds to step S205.

  Since no abnormality was detected immediately after the exposure, in step S205, the location where the abnormality occurred is identified as the developing unit 33c, which is a portion that performs the next process of exposure. On the other hand, if Yes in step S203, that is, if an abnormality is detected from the semiconductor wafer immediately after exposure, the process proceeds to step S207.

  In step S207, the coated semiconductor wafer is inspected. The control unit 19 instructs the transfer unit 15 to pass the semiconductor wafer on which the coating process has been completed to the inspection unit 17. When the inspection unit 17 receives the semiconductor wafer after the coating process from the transport unit 15, the inspection unit 17 inspects the semiconductor wafer. Since the semiconductor wafer inspection method in step S207 is the same as the semiconductor wafer inspection method in step S201, detailed description thereof is omitted. Then, the process proceeds to the next step S209.

  In step S209, it is determined whether or not an abnormality immediately before exposure has been detected. The determination unit 47 passes the determination result to the abnormality specifying unit 49. The abnormality specifying unit 49 determines whether there is an abnormality in the exposure unit 33b. If No in step S209, that is, if no abnormality is detected from the semiconductor wafer after coating, the process proceeds to the next step S211. In step S211, the cause of the abnormality is identified as the exposure unit 33b.

  On the other hand, in step S209, it is determined whether an abnormality has been detected. If YES in step S209, that is, if an abnormality is detected from the coated semiconductor wafer, the process proceeds to step S213. In step S213, the cause of the abnormality is identified as the application unit 33a. The cause identifying process is completed by the above steps S201 to S213.

  Returning to the description of FIG. 4 again, a recovery process is performed in step S115. The abnormality specifying unit 49 instructs the signal generating unit 51 to generate a recovery instruction signal for executing the recovery process on the photolithographic processing unit 33 that has specified the abnormality. The restoration instruction signal generated in the signal generation unit 51 is output to the photolithography processing unit 33 identified as the cause of abnormality via the control unit 19. For example, when the application unit 33a is identified as the cause of the abnormality, the application unit 33a performs a recovery process upon receiving an instruction from the control unit 19. The restoration work performed by the application unit 33a is, for example, removal of foreign matters by cleaning each part such as a nozzle. Then, the process proceeds to the next step S117.

  In step S117, the production operation is resumed. The control unit 19 instructs the photolithography processing unit 33 (the coating unit 33a, the exposure unit 33b, and the developing unit 33c) to start production again. Each photolithographic processing unit 33 starts processing the semiconductor wafer again.

  As described above, according to the present embodiment, when an abnormality occurs in a semiconductor wafer, the above causes can be specified. In addition, since the photolithography processing unit 33 identified as the cause of the abnormality performs the reproduction process, it is possible to reduce the time during which the photolithography process is stopped due to the abnormality.

  In the present embodiment, when there is no abnormality in the semiconductor wafer, the photolithography process apparatus 11 generates a continuation instruction signal that instructs to continue production. Here, the photolitho process apparatus 11 may not generate a continuation instruction signal when it is determined to continue production, but may generate a stop instruction signal only when it is determined to stop production.

  In the present embodiment, the inspection unit 17 inspects whether there is an abnormality based on imaging data obtained by imaging a semiconductor wafer. Here, the semiconductor wafer inspection method may be any method that can detect an abnormality of the semiconductor wafer, and may be an inspection method other than image processing.

  The photolithography process apparatus according to the present invention is useful for identifying the cause of an abnormality when an abnormality occurs in a semiconductor wafer in the photolithography process step.

The block diagram which shows the structure of the photolitho process apparatus 11 which concerns on one Embodiment of this invention. The block diagram which shows the detailed structure of the test | inspection part 17 Diagram showing an example of model pattern The figure which shows an example of the imaged image typically The figure which shows typically an example of the mismatching location 65 extracted when FIG. 3A and FIG. 3B are compared. A flowchart showing the operation of the photolithography process apparatus 11 Flowchart showing details of subroutine step S113 Flow chart showing processing performed in a conventional photolithography process

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Photolitho process apparatus 13 Production operation part 15 Conveyance part 17 Inspection part 19 Control part 21 Resist peeling part 31 Loader part 33 Photolitho process part 35 Unloader part 41 Imaging part 43 Image comparison part 45 Storage part 47 Determination part 49 Abnormality specification part 51 Signal Generation unit 55 Model pattern 57 Wiring pattern 59 Imaging pattern 61 Abnormal location 63 Extracted pattern 65 Unmatched location

Claims (5)

A photolithography process apparatus that performs photolithography processing on a substrate through a plurality of steps,
A substrate inspection unit for inspecting whether or not the provided substrate is defective;
A substrate providing unit for inspecting the substrate by the substrate inspection unit by transporting and providing the substrate processed in the instructed step to the substrate inspection unit among the plurality of steps;
In the normal operation mode, only the substrate processed in a predetermined step among the plurality of steps is provided to the substrate inspection unit and inspected, and the substrate processed in the predetermined step has a defect. In the abnormality detection mode determined by the inspection unit, a control unit that controls the substrate providing unit so that the substrate processed in the step existing before the predetermined step is provided to the substrate inspection unit and inspected,
A photolithographic process apparatus comprising: an abnormality identification unit that identifies in which step the defect has occurred based on an inspection result of the substrate inspection unit in the abnormality detection mode. In the abnormality detection mode, the control unit provides the substrate processing unit with the substrates processed in each step among the steps existing before the predetermined step while tracing the substrate processing step order. Including an inspection process instruction unit for instructing the substrate providing unit,
When the substrate inspection unit determines that the substrate is not defective, the abnormality specifying unit determines that there is an abnormality in the process immediately after the step determined to be free of defects, and the control unit performs substrate inspection. The photolithographic process apparatus according to claim 1, further comprising an abnormal process specifying unit that stops providing the substrate to the unit.   The photolithography process apparatus according to claim 1, further comprising a recovery processing execution unit that performs a recovery measure for recovering the process in the process specified by the abnormality specifying unit.   The photolithography process apparatus according to claim 1, wherein the predetermined process is located in a final process among a plurality of processes having a possibility of occurrence of abnormality. In a photolithography process in which a photolithography process is performed on a substrate in a plurality of steps, a method for detecting that a defect has occurred in the substrate in the processing in the plurality of steps,
A first inspection step for inspecting whether or not there is a defect with respect to the substrate processed in a predetermined process among the plurality of processes;
A second inspection step for inspecting a substrate processed in a process existing before the predetermined process when it is determined in the first inspection step that the substrate processed in the predetermined process is defective;
A defect inspection method comprising: an abnormality identification step that identifies in which process the defect has occurred based on an inspection result of the second inspection step.

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