TWI762039B - Wafer defect detecting system in semiconductor photolithography process - Google Patents

Abstract

Provided is a wafer defect detection system in a semiconductor photolithography process. The wafer defect detection system includes photolithography equipment, an equipment controller configured to control an operation of the photolithography equipment, a plurality of camera units installed inside a cooling unit constituting the photolithography equipment to have different angles with respect to a wafer, a plurality of lighting units installed inside the cooling unit and operating to provide lighting when the plurality of camera units start photographing, and a wafer defect detector configured to obtain a lot identification (ID) and process recipe information of wafers to be processed by hooking communication between the equipment controller and a host server provided at a remote location, control the plurality of camera units and the plurality of lighting units to be sequentially operated, synthesize a plurality of images received from the plurality of camera units to obtain a detected image, and compare the detected image to a reference image to detect a defect of the wafer.

Description

Wafer Defect Inspection System in Semiconductor Lithography Process

The present invention relates to a wafer defect detection system in a semiconductor lithography process. More specifically, the present invention relates to a wafer defect detection system in a semiconductor lithography process, wherein defects in a wafer are detected in a cooling unit, and a cooling process (which is a semiconductor microlithography process) is performed in the cooling unit. The final process of the film process) to simplify a process and a device configuration required for wafer defect detection and improve the accuracy of wafer defect detection.

Generally speaking, a semiconductor lithography process includes a coating process, a hard bake process, an exposure process, a post-exposure bake process, a development process and a cooling process.

At the same time, a process of checking whether defects are generated in a wafer on which a lithography process is performed is basically performed. Specifically, a process of inspecting a coating process-related defect, an exposure defocusing process-related defect, a developing process-related defect, or the like is performed.

However, according to the related art, in order to detect whether a defect is generated in a wafer after performing coating, hard bake, exposure, post-exposure bake, development and cooling processes, it is basically necessary to use a transfer unit to unload the wafer from a corresponding unit circle and load the wafer onto a separate inspection unit for a process of wafer inspection. Therefore, there is a problem of decreased overall productivity due to the fact that the continuity of the lithography process is interrupted, a process time is increased, the device configuration is complicated, and the like. [Related technical documents]

(Patent Document 1) Korean Patent Laid-Open Application No. 10-2006-0117032 (published on November 16, 2006, title: WAFER DEFECT DETECTION METHOD)

(Patent Document 2) Korean Patent Publication Application No. 10-2003-0005956 (published on January 23, 2003, title: PHOTOLITHOGRAPHY PROCESS SYSTEM AND METHOD THEREOF)

(Patent Document 3) Korean Patent Publication Application No. 10-2016-0068228 (published on June 15, 2016, title: WAFER DEFECT INSPECTION DEVICE)

technical problem

The present invention aims to provide a wafer defect detection system in a semiconductor lithography process, wherein defects in a wafer are detected in a cooling unit, and a cooling process (which is the last step of the semiconductor lithography process) is performed in the cooling unit. process) to simplify a process and a device configuration required for wafer defect detection and improve the accuracy of wafer defect detection. solution to problem

According to an aspect of the present invention, there is provided a wafer defect detection system in a semiconductor lithography process, which is a system for detecting a defect of a wafer in a cooling process, the cooling process being the semiconductor microlithography process. The final process of the film production process. The wafer defect inspection system includes: lithography equipment, which includes a coating unit, a hard bake unit, an exposure unit, a post-exposure bake unit, a development unit, a cooling unit and a transfer unit, the A unit is a processing unit in which a plurality of detailed processes that constitute a lithography process are performed; an equipment controller is configured to control an operation of the lithography equipment; a plurality of camera units, etc. are installed inside the cooling unit to have different angles relative to the wafer; a plurality of illumination units, etc. mounted inside the cooling unit and operative to provide illumination when the plurality of camera units begin to photograph; and a wafer defect detector assembled state to obtain a lot identification (ID) and process plan information for the wafers to be processed, control the plurality of The camera unit and the plurality of illumination units operate sequentially, synthesizing a plurality of images received from the plurality of camera units to obtain an inspection image and comparing the inspection image with a reference image to detect a defect of the wafer.

In the wafer defect inspection system in the semiconductor lithography process according to the present invention, the wafer defect inspector may preset an initial wafer of the wafers corresponding to the batch ID of an initial input The inspection area performs image inspection, and due to the image inspection, the wafer defect detector can determine an image of the original wafer as the reference image when it is determined that there are no defects in the original wafer.

In the wafer defect detection system in the semiconductor lithography process according to the present invention, the number of initial wafers identical to the initial wafer may be one or more, and the wafer defect detector may The image inspection is repeated for the wafers such as the original wafer until the reference image is determined.

In the wafer defect inspection system in the semiconductor lithography process according to the present invention, the wafer defect inspector can remove noise contained in the plurality of images to the A plurality of images are subjected to histogram equalization, and the plurality of images on which the histogram equalization is performed are synthesized to obtain a detection image.

In the wafer defect inspection system in the semiconductor lithography process according to the present invention, the wafer defect inspector can obtain a difference image between the inspection image and the reference image and by setting a predetermined threshold Values are applied to the difference image to detect defects contained in the inspection image.

In the wafer defect inspection system in the semiconductor lithography process according to the present invention, the wafer defect inspector can transmit inspection information about the defect of the wafer to a defect inspection classification and management device, and the The defect inspection classification and management apparatus may store and manage the inspection information received from the wafer defect inspector. Advantageous Effects of the Invention

According to the present invention, a wafer defect detection system in a semiconductor lithography process can be provided, wherein defects in a wafer are detected in a cooling unit, and a cooling process (which is a part of the semiconductor lithography process) is performed in the cooling unit. Final process) to simplify a process and a device configuration required for wafer defect detection and improve the accuracy of wafer defect detection.

1 is a block diagram illustrating a wafer defect inspection system in a semiconductor lithography process according to an embodiment of the present invention, and FIG. 2 is an example of a lithography apparatus 10 in an embodiment of the present invention FIG. 3 is a conceptual diagram illustrating an exemplary structure of a cooling unit 600 constituting a lithography apparatus 10 in an embodiment of the present invention, and FIG. 4 is a diagram illustrating an implementation of the present invention. A conceptual diagram of an exemplary planar structure in the example in which the plurality of camera units 31 , 32 , 33 and 34 and the plurality of illumination units 41 , 42 , 43 and 44 are mounted inside the cooling unit 600 constituting the lithography apparatus 10 .

Referring to FIGS. 1 to 4 , a wafer defect detection system in a semiconductor lithography process according to an embodiment of the present invention includes a lithography apparatus 10 , an apparatus controller 20 , a plurality of camera units 31 , 32 , 33 and 34 , a plurality of lighting units 41 , 42 , 43 and 44 and a wafer defect detector 50 .

The lithography apparatus 10 includes a processing unit in which a plurality of detailed processes that constitute a lithography process are performed.

The lithography apparatus 10 includes a coating unit 100 , a hard bake unit 200 , an exposure unit 300 , a post-exposure bake unit 400 , a developing unit 500 , a cooling unit 600 and a transfer unit 700 .

The coating unit 100 is a component of a process that performs a process of applying a photoresist (PR) to a wafer, and the coating unit 100 can be applied by a spin coating method, which is a method of spinning the wafer. A photoresist film having a desired thickness is uniformly formed on the entire wafer.

Hard bake unit 200 is a component of a process that performs heating and drying of the wafer to remove a residual solvent along with the PR applied to the wafer.

Exposure unit 300 is a component of a process that performs a process of forming a desired pattern by applying light to a photoresist film on the wafer aligned with the mask pattern.

The post-exposure bake unit 400 performs heating and drying of the photoresist film at a temperature of, for example, 100° C. or lower after exposure and before development, and diffuses the photoresist film contained in the photoresist film through the post-exposure bake unit 400 A photoreactive compound (PAC) is a component of a process that smoothes a surface of a photoresist film.

The developing unit 500 is an element of a process that performs a photoresist film pattern by removing unnecessary portions of the photoresist film using a developer.

Cooling unit 600 is one of the last steps in the lithography process and is a component of a process that performs a process of cooling wafers immediately prior to unloading the wafers into a loading pod, which is referred to as a front opening pod (FOUP) .

The transfer unit 700 is an assembly that loads or unloads wafers between units, and the transfer unit 700 may be configured in the form of a robotic arm or the like.

In the embodiment of the present invention, a plurality of camera units 31 , 32 , 33 and 34 and a plurality of illumination units 41 , 42 , 43 and 44 are installed inside the cooling unit 600 to obtain a wafer image.

As described above, according to the related art, in order to detect whether a defect is generated in a wafer after coating, hard bake, exposure, post-exposure bake, development and cooling, it is basically required in which the wafer is unloaded from the corresponding unit and a transfer is used unit 700 to load wafers onto a separate inspection unit for a process of wafer inspection. Therefore, there is a problem of decreased overall productivity due to the fact that the continuity of the lithography process is interrupted, a process time is increased, the device configuration is complicated, and the like.

However, according to the embodiment of the present invention, the plurality of camera units 31, 32, 33, and 34 and the lighting units 41, 42, 43, and 44 are installed inside the cooling unit 600, and the cooling process (which is a semiconductor microcomputer) is performed in the cooling unit 600. The final process of the filming process) is used to inspect the wafer image, so that a process and a device configuration required for wafer defect inspection can be simplified and the accuracy of wafer defect inspection can be improved.

Device controller 20 is a component that controls an operation of lithography device 10 . For example, the equipment controller 20 may receive from a remote host server 60 a lot identification (ID) and process plan information of the wafer to be processed, control the execution of a corresponding process, and send information about the execution status of the process Provided to the host server 60 .

A plurality of camera units 31 , 32 , 33 and 34 are mounted inside the cooling unit 600 at a plurality of points spaced apart from each other to have different angles relative to the wafer.

The plurality of lighting units 41 , 42 , 43 and 44 are installed inside the cooling unit 600 and operate to provide lighting when the plurality of camera units 31 , 32 , 33 and 34 start photographing.

Each of the individual cameras constituting the plurality of camera units 31 , 32 , 33 and 34 and each of the individual illuminations constituting the plurality of lighting units 41 , 42 , 43 and 44 are formed to operate in pairs.

As shown in FIG. 4, in the case where four cameras and four lighting units are provided, first, a first camera unit 31 and a first lighting unit 41 may be formed in pairs to operate simultaneously, then, a first Two cameras 32 and a second lighting unit 42 may be formed in pairs to operate simultaneously, then, a third camera 33 and a third lighting unit 43 may be formed in pairs to operate simultaneously, and then, a fourth camera 34 and a The fourth lighting units 44 may be formed in pairs to operate simultaneously. The sequential operation of the plurality of camera units 31 , 32 , 33 and 34 and the plurality of illumination units 41 , 42 , 43 and 44 can be controlled by the wafer defect detector 50 . According to the sequential operation, in a wafer imaging process, noise and image distortion caused by the backlight, which can be caused by the operation of the illumination units 41, 42, 43 and 44 facing each other, can be reduced.

The wafer defect detector 50 is one of the following components: obtaining the lot ID of the wafer to be processed by enabling communication between the equipment controller 20 and a host server 60 provided at a remote location and The process plan information controls the plurality of camera units 31, 32, 33 and 34 and the plurality of lighting units 41, 42, 43 and 44 to operate in sequence, and synthesizes the plurality of images received from the plurality of camera units 31, 32, 33 and 34 to An inspection image is obtained, and the inspection image is compared with a reference image to inspect a defect of the wafer.

For example, with further reference to FIG. 5, which illustrates an example of an inspection area set on an initial wafer to determine a reference image, the wafer defect detector 50 may respond to the initial input of the wafer corresponding to a batch ID. Image inspection is performed on a predetermined inspection area of the initial wafer. Due to the image inspection, the wafer defect detector 50 can determine one of the images of the original wafer as the reference image when it is determined that there are no defects in the original wafer. In this case, the inspection area may be designated in units of wafer units, ten or more areas may be set as inspection areas, and the inspection areas may be input and output by a manager through one connected to the wafer defect detector 50 interface device to set or reset. For example, when the respective cells are identical, the wafer can be considered defect free and the image of the wafer can be set as the reference image. In this method, errors on the wafer can even be detected in the initial wafer during the inspection process used to generate the reference image.

For example, the number of initial wafers that are the same as the initial wafer may be one or more, the wafer defect detector 50 may repeatedly perform image inspection on the wafers constituting the initial wafer until the reference image is determined, and the number of initial wafers It can be set or reset by the administrator through the input and output interface devices connected to the wafer defect detector. As a specific example, in the case where the number of initial wafers is set to 3, when there is no defect in one of the initial input wafers, an image of the first wafer can be determined as the reference image and used to determine the reference An additional process of the image can be configured not to be performed.

FIG. 6 is a diagram illustrating an exemplary configuration in which the wafer defect detector 50 obtains an inspection image in one embodiment of the present invention. In FIG. 5, although it is disclosed that three images are used to obtain the detection image, this is only an example, and four or more images may be used.

With further reference to FIG. 6 , the wafer defect detector 50 1) can remove image distortion portions caused by noise, reflections, etc. contained in a plurality of images obtained sequentially, and 2) can remove therefrom the image distortion caused by noise Histogram equalization is performed on the plurality of images of the image distortion portion caused by , reflection, etc., and 3) the plurality of images on which the histogram equalization is performed may be synthesized to obtain a detection image.

7 and 8 are diagrams illustrating exemplary configurations in which wafer defect detector 50 detects defects included in an inspection image in one embodiment of the present invention.

With further reference to FIGS. 7 and 8 , the wafer defect detector 50 can obtain a difference image between the inspection image and the reference image and detect defects included in the inspection image by applying a predetermined threshold value to the difference image .

For example, at the same time as the process described above, feature points can be found by applying a Sobel edge algorithm for defect detection, and by interlocking the found feature points with the feature information of the wafer (ie, by comparing the found feature points with the feature information of the wafer) to detect defects. The feature points may include specific patterns and colors according to the processing of the wafer.

For example, the wafer defect detector 50 may transmit inspection information about defects of the wafer to a defect inspection classification and management device 70 , and the defect inspection classification and management device 70 may store and manage the information received from the wafer defect inspector 50 . Check information.

As described in detail above, according to the present invention, a wafer defect detection system in a semiconductor lithography process can be provided, wherein defects in a wafer are detected in a cooling unit, and a cooling process (which is It is the final process of the semiconductor lithography process) to simplify a process and a device configuration required for wafer defect detection and improve the accuracy of wafer defect detection.

10: lithography equipment 20: Device Controller 31: Camera unit 32: Camera unit 33: Camera unit 34: Camera unit 41: Lighting unit 42: Lighting unit 43: Lighting unit 44: Lighting unit 50: Wafer Defect Detector 60: host server 70: Defect detection classification and management device 100: Coating unit 200: Hard bake unit 300: Exposure unit 400: Post-exposure bake unit 500:Development unit 600: Cooling unit 700: Transfer Unit

FIG. 1 is a block diagram illustrating a wafer defect inspection system in a semiconductor lithography process according to an embodiment of the present invention.

FIG. 2 is a diagram showing an exemplary configuration of a lithography apparatus in an embodiment of the present invention.

3 is a conceptual diagram illustrating an exemplary structure of a cooling unit constituting a lithography apparatus in an embodiment of the present invention.

4 is a conceptual diagram illustrating an exemplary planar structure in which a plurality of camera units and a plurality of lighting units are mounted inside a cooling unit constituting a lithography apparatus in an embodiment of the present invention.

5 is a diagram illustrating an example of an inspection area set on an initial wafer to determine a reference image in an embodiment of the present invention.

FIG. 6 is a diagram illustrating an exemplary configuration of a wafer defect detector to obtain an inspection image in an embodiment of the present invention.

7 and 8 are diagrams illustrating exemplary configurations in which a wafer defect detector detects defects included in an inspection image in one embodiment of the present invention.

10: lithography equipment

20: Device Controller

50: Wafer Defect Detector

60: host server

70: Defect detection classification and management device

Claims (6)

A wafer defect detection system in a semiconductor lithography process, which is a system for detecting a defect of a wafer in a cooling process, the cooling process being the final process of the semiconductor lithography process, the wafer The defect detection system includes: lithography equipment, which includes a coating unit, a hard bake unit, an exposure unit, a post-exposure bake unit, a developing unit, a cooling unit and a transfer unit, and these units are among the A processing unit that performs a plurality of detailed processes that constitute a lithography process; an equipment controller configured to control an operation of the lithography equipment; a plurality of camera units, etc., installed inside the cooling unit to have relative at different angles of the wafer; a plurality of illumination units, which are mounted inside the cooling unit and operate to provide illumination when the plurality of camera units begin to photograph; and a wafer defect detector configured to Obtaining a lot identification (ID) and process plan information for wafers to be processed, controlling the plurality of camera units, and The plurality of illumination units operate sequentially, synthesize the plurality of images received from the plurality of camera units to obtain an inspection image and compare the inspection image with a reference image to detect a defect of the wafer. The wafer defect inspection system of claim 1, wherein the wafer defect detector performs image inspection on a predetermined inspection area of an initial wafer of the initial input of the wafers corresponding to the lot ID, and due to the Image inspection, when the initial wafer is judged to be free of defects, the wafer is inspected for defects The controller determines an image of the initial wafer as the reference image. The wafer defect inspection system of claim 2, wherein the number of initial wafers identical to the initial wafer is one or more, and the wafer defect detector repeats for the wafers constituting the initial wafers The image verification is performed until the reference image is determined. The wafer defect inspection system of claim 1, wherein the wafer defect detector is configured to: remove noise contained in the plurality of images; perform on the plurality of images from which the noise is removed histogram equalization; and synthesizing the plurality of images on which the histogram equalization is performed to obtain the detection image. The wafer defect inspection system of claim 1, wherein the wafer defect detector is configured to: obtain a difference image between the inspection image and the reference image; and by applying a predetermined threshold to The difference image is used to detect a defect contained in the inspection image. The wafer defect inspection system of claim 1, wherein the wafer defect detector transmits inspection information about the defect of the wafer to a defect inspection classification and management device, wherein the defect inspection classification and management device stores and manages The inspection information received from the wafer defect inspector.

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