JPH0236570A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable the construction of a structure with its breakdown strength improved out of a substrate which is neither thick nor high in resistivity by a method wherein a lattice defect region is formed, bridging an anode region and a high resistivity region, at the junction between the anode region and the high resistivity region. CONSTITUTION:A P-N-P-N four layer thyristor has a cathode region (N<+>-layer) 4 located at one side of a semiconductor substrate 1 and an anode region (p<+>-layer) 2 located at the other side of the same. Between said two regions 4 and 2, a high resistivity region (N<->-layer) 1' is provided, serving as a current path. A current controlling gate region (P<+>-layer) 3 is provided in the vicinity of the cathode region 4. A lattice defect region 6 is so provided as to bridge the anode region 2 and the high resistivity region 1' at a junction 8. With the lattice defect region 6 being apparently high in resistivity, electrons will not be easily absorbed when a depletion layer 7 reaches the anode region 2, which prevents punch-through. Accordingly, breakdown strength may be improved without using a thick semiconductor substrate or a high resistivity semiconductor substrate.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor device.

[Conventional technology]

One of the semiconductor devices is a so-called PNPN four-layer silicon. Figure 4 shows the conventional PNPN cyrisk.

This SiRisk has a cathode region (N" layer) 24 on one side of the semiconductor substrate 21 and an anode region (P" layer) 24 on the other side.
2, and a high resistivity region (N- layer) 21' serving as a current path is provided between these two regions. The gate region (P″ layer) 23 for current control is located immediately adjacent to the cathode region 24 (
(nearby).

In this case, when shutting off, as shown in FIG. 4, conduction between the cathode electrode 2K and the anode electrode 2A is blocked by the depletion layer 27 that spreads within the high resistivity region 21'; When a signal is applied, conduction occurs between the cathode electrode 2K and the anode electrode 28.

This SIRISK includes guard ring regions (P+ layers) 25a and 25b on the sides of the gate region 23 in order to improve the withstand voltage. Such a guard ring region for improving withstand voltage is disclosed in, for example, Japanese Patent Publication No. 12739/1983.

[Problem to be solved by the invention]

Attempts have been made to further improve the withstand voltage of the above-mentioned Cyrisk, but as will be seen below, none of the conventional measures (1) to (3) below can be said to be sufficiently practical.

In order to improve the withstand voltage, the following concrete measures can be considered.

■ Increase the resistivity of the semiconductor substrate.

■ Increase the thickness of the high resistivity region.

■ Increase the number of guard ring areas.

■ Deepen the diffusion depth of the guard ring area.

However, the above-mentioned measures (1) and (2) have disadvantages, such as increasing on-resistance. An increase in substrate thickness also affects substrate cost. The above measure (2) increases the chip area of the element and is disadvantageous in terms of cost.

The measure (2) above improves the withstand voltage in terms of alleviating the electric field concentration in the depletion layer. However, on the other hand, this does not substantially reduce the thickness of the high resistivity region, and the edge of the depletion layer reaches the anode region at a low voltage, reducing the so-called punch-through breakdown voltage, and eventually reducing the effective It is not possible to improve the withstand voltage. In particular, in the case of a thin semiconductor substrate, the on-resistance is low and it is advantageous in terms of cost, but since the thickness of the high resistivity region is originally thin, the above-mentioned measure for improving the withstand voltage is not suitable.

It is difficult to use.

In view of the above circumstances, it is an object of the present invention to provide a semiconductor device having a configuration that can improve the withstand voltage even if the semiconductor substrate is not thick or has high resistivity.

[Means to solve the problem]

In order to solve the above problem, in the semiconductor device of the present invention,
At the junction position of the anode region and the high resistivity region, a lattice defect region is provided spanning the anode region and the high resistivity region.

[For production]

The effect of improving the withstand voltage in the semiconductor device of the present invention will be explained with reference to FIG.

The gate electrode G (3') and the cathode electrode K (
A forward voltage is applied between the anode electrode A (2') and the cathode electrode while short-circuiting A (2') to prevent the SIRISK from conducting. Since the SiRisk is in a cutoff state, a depletion layer 7 spreads within the high resistivity region 1', as shown in FIG. As the voltage increases, the depletion layer 7 expands not only in the horizontal direction but also in the vertical direction, and at a certain voltage the end of the depletion layer 7 reaches the end of the anode region 2, that is, the junction 8 position.

Conventionally, when this state occurs, the electrons in the high resistivity region 1' are simultaneously attracted by the high electric field and sucked into the anode region 2. Immediately caused a punch-through. In the SIRISK of this invention, the anode region 2 has a lattice defect region 6, and since the region 6 has an apparent resistivity, even if the depletion N7 reaches the anode region 2, electrons can easily escape. Therefore, punch-through does not occur. Therefore, the withstand voltage can be improved without using a thick semiconductor substrate or a high resistivity semiconductor substrate.

In other words, even a thin substrate can have sufficient withstand voltage.

Although the formation of the lattice defect region 6 is accompanied by a slight increase in resistance, since the resistance only increases in a very thin layer portion, the rate of increase in resistance as a whole is small and has almost no effect.

In addition, as can be seen from the above explanation, theoretically there is no need for lattice defect regions on the high resistivity region side, but since lattice defect regions are distributed in such a way that the density is lower at the bottom of the region. , unless the lattice defect region 6 spans the high resistivity region 1' and the anode region 2, the end of the anode region 2 will not have a sufficient defect density. If the lattice defect region is formed only in the anode region, the second end of the anode region is at the tail of the distribution, so the defect density is small and a sufficient effect cannot be obtained.

〔Example〕

Hereinafter, one embodiment of the semiconductor device of the present invention will be described in detail with reference to the accompanying drawings.
N P N 4 N Sirisk has a cathode region (N'' layer) 4 on one side of the semiconductor substrate 1 and an anode region (N'' layer) on the other side.
A high resistivity region (N- layer) 1' serving as a current path is provided between these top regions.A gate region (P' layer) 3 for current control is a cathode region. 4. This silicon risk also includes guard ring regions (P" layers) 5a and 5b on the sides of the gate region 3 in order to improve the withstand voltage. When shutting off, as shown in Figure 1,
The depletion layer 7 spreading within the high resistivity region 1' prevents conduction between the cathode electrode K and the anode electrode A. However, when a trigger signal is applied to the gate electrode G, the conduction between the cathode electrode K and the anode electrode A is blocked. conducts, allowing current to flow.

The lattice defect region 6 is located in the anode region 2 at the junction 8 position.
As described above, the resistive layer is provided so as to straddle the high resistivity region 1', and has the effect of increasing the punch-through withstand voltage.

For example, in a case where the withstand voltage without the lattice defect region 6 is 900 μ, when the lattice defect region is formed by proton beam irradiation, the withstand voltage is improved by approximately 100 to 300 μ. It was confirmed. Of course, as shown in FIG. 3, the greater the dose of the proton beam, the greater the degree of improvement in withstand voltage.

Next, an example of the method for producing the above-mentioned Cyrisk will be explained.

An anode region 2, a gate region 3, an N-type semiconductor substrate 1,
Guard ring regions 5a and 5b are formed by thermal diffusion of impurities, and cathode regions 4 are formed on the surface of gate region 3 by thermal diffusion of impurities. Then, an anode electrode A, a cathode electrode K, and a gate electrode G are formed.

After forming the electrodes, a proton beam is irradiated from the front or back surface of the silice to form lattice defect regions 6.

It is preferable that the peak of the defect density of the lattice defect region 6 is located approximately at the junction 8 by adjusting the acceleration energy of the proton beam, for example. The dose amount is appropriately determined by taking into consideration the required withstand voltage and other characteristics. For example, 1XIQ"/cn! ~ 10 X 10"/cI
It is better to set it to Il. Since the lattice defect region 6 is recovered by heat treatment at about 350° C. or higher, it is desirable that the proton beam irradiation be performed after the electrode is formed without any heat treatment that has a defect repair effect.

Next, another embodiment will be explained. FIG. 2 shows an electrostatic induction sensor which is another example of the semiconductor device according to the present invention.

This electrostatic induction risk is caused by the surface side of the semiconductor substrate 1 (−
side), a cathode region (N'' layer) 4, and a gate region (P'' layer) 3 formed to sandwich this cathode region 4.
It is equipped with The anode region (P' layer) 2 is provided on the back side (other side) of the semiconductor substrate 1. Gate electrode G
Both the anode electrode A and the cathode electrode are provided on the front surface of the substrate 1, while the anode electrode A is provided on the back surface of the substrate.

A high resistivity region (N- layer) 1' serving as a current path is provided between the cathode region 4 and the anode region 2.

In this electrostatic induction thyristor, a current path formed between the cathode and the anode is controlled on/off by a voltage signal applied to the gate electrode G.

As described above, the lattice defect region 6 is provided at the junction 8 position so as to span the anode region 2 and the high resistivity region 1', and has the effect of increasing the punch-through withstand voltage.

This invention is not limited to the above embodiments. The semiconductor device may be of other types such as gate turn-off transistors, insulated gate bipolar transistors, static induction bipolar transistors, etc. For transistors, the cathode is usually referred to as the source and the anode as the drain. Furthermore, the semiconductor device of the embodiment may have a configuration in which the conductivity type is reversed (NP, P→N).

Furthermore, the semiconductor device may be a device that does not include a guard ring region.

The formation of the lattice defect region is not limited to proton beam irradiation, and other methods may also be used. For example, other charged particles (e.g. electrons)
The irradiation may be performed by irradiation with a line or the like.

〔Effect of the invention〕

As described above, in the semiconductor device of the present invention, the lattice defect region is provided at the junction position of the anode region and the high voltage resistance region, spanning the anode region and the high resistivity region. It has a structure that can improve withstand voltage even if it is not a high-resistivity semiconductor substrate.
Therefore, it is highly practical.

[Brief explanation of the drawing]

FIG. 1 shows a PNPN which is an example of a semiconductor device of the present invention.
FIG. 2 is a cross-sectional view of an electrostatically induced SI risk, which is another example of the semiconductor device of the present invention, and FIG. 3 shows the relationship between proton beam dose and withstand voltage improvement. The hail graph, FIG. 4, is a cross-sectional view of a conventional PNPN hail risk. 1...Semiconductor substrate 1'...High resistivity region 2...
・Anode region 3... Gate region 4... Cathode region 6... Lattice defect region 8... Bonding agent
Patent Attorney Takehiko Matsumoto Figure 2

Claims (1)

[Claims] 1. A semiconductor substrate has a cathode region on one side and an anode region on the other side, a high resistivity region that serves as a current path between these two regions, and a current control region near the cathode region. A semiconductor device comprising a gate region, wherein a lattice defect region is provided at a junction position between the anode region and the high resistivity region, spanning the anode region and the high resistivity region. .