JPH023534B2 - - Google Patents

Info

Publication number
JPH023534B2
JPH023534B2 JP59018056A JP1805684A JPH023534B2 JP H023534 B2 JPH023534 B2 JP H023534B2 JP 59018056 A JP59018056 A JP 59018056A JP 1805684 A JP1805684 A JP 1805684A JP H023534 B2 JPH023534 B2 JP H023534B2
Authority
JP
Japan
Prior art keywords
glaze layer
mask
layer
width
print head
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59018056A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60160122A (ja
Inventor
Shunji Nakada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP59018056A priority Critical patent/JPS60160122A/ja
Publication of JPS60160122A publication Critical patent/JPS60160122A/ja
Publication of JPH023534B2 publication Critical patent/JPH023534B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Electronic Switches (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
JP59018056A 1984-01-30 1984-01-30 サーマルプリントヘッドの製造方法 Granted JPS60160122A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59018056A JPS60160122A (ja) 1984-01-30 1984-01-30 サーマルプリントヘッドの製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59018056A JPS60160122A (ja) 1984-01-30 1984-01-30 サーマルプリントヘッドの製造方法

Publications (2)

Publication Number Publication Date
JPS60160122A JPS60160122A (ja) 1985-08-21
JPH023534B2 true JPH023534B2 (enExample) 1990-01-24

Family

ID=11961036

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59018056A Granted JPS60160122A (ja) 1984-01-30 1984-01-30 サーマルプリントヘッドの製造方法

Country Status (1)

Country Link
JP (1) JPS60160122A (enExample)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52144973A (en) * 1976-05-28 1977-12-02 Hitachi Ltd Positioning method of semiconductor wafers
JPS59208722A (ja) * 1983-05-13 1984-11-27 Oki Electric Ind Co Ltd 半導体集積回路装置用合せマ−ク
JPS6077421A (ja) * 1983-10-05 1985-05-02 Fujitsu Ltd 位置合わせ方法

Also Published As

Publication number Publication date
JPS60160122A (ja) 1985-08-21

Similar Documents

Publication Publication Date Title
EP0061536B1 (en) Method of manufacturing a semiconductor device having improved alignment marks and alignment marks for said method
CA1087384A (en) Method and apparatus for producing nozzle arrays for ink jet printers
US3542551A (en) Method of etching patterns into solid state devices
US3245794A (en) Sequential registration scheme
US6924090B2 (en) Method of recording identifier and set of photomasks
EP1291722B1 (en) Method of recording identifier and set of photomasks
JPH0450730B2 (enExample)
JPH023534B2 (enExample)
KR100668185B1 (ko) 박막 칩 저항기 제조방법
US3673018A (en) Method of fabrication of photomasks
JPH0578146A (ja) 感光性ガラスの加工方法及びこの方法によつて製造したインクジエツトヘツド
JPH0560584B2 (enExample)
JPH03209711A (ja) 半導体装置の製造方法
JPH01196822A (ja) 半導体集積回路装置
JPS6212618Y2 (enExample)
JPS6223862B2 (enExample)
JP2863283B2 (ja) サーマルヘッド及びその製造方法
JPH03106013A (ja) 位置合わせマーク作成方法
JPH01241461A (ja) サーマルヘッドのフォトリソ用マスク装置
JPS60224227A (ja) レジスト膜のパタ−ン形成方法
JPH07186427A (ja) サーマルプリントヘッドの製造方法
JPS6363383B2 (enExample)
JPH03207669A (ja) サーマルヘッド及びその製造方法
JPH08213302A (ja) 微細加工方法及びこの加工方法に用いる微細加工用フォトマスク
JPH04308769A (ja) サーマルプリントヘッド

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees