JPH0234205B2 - KAHENRITOKUSEIGYOKAIRO - Google Patents
KAHENRITOKUSEIGYOKAIROInfo
- Publication number
- JPH0234205B2 JPH0234205B2 JP23669583A JP23669583A JPH0234205B2 JP H0234205 B2 JPH0234205 B2 JP H0234205B2 JP 23669583 A JP23669583 A JP 23669583A JP 23669583 A JP23669583 A JP 23669583A JP H0234205 B2 JPH0234205 B2 JP H0234205B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- gain control
- operational amplifier
- resistor
- divider
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000010586 diagram Methods 0.000 description 6
- 230000003321 amplification Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 1
- 102220078862 rs77460377 Human genes 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45475—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers without distortion of the input signal
- H03G3/001—Digital control of analog signals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G7/00—Volume compression or expansion in amplifiers
- H03G7/002—Volume compression or expansion in amplifiers in untuned or low-frequency amplifiers, e.g. audio amplifiers
- H03G7/005—Volume compression or expansion in amplifiers in untuned or low-frequency amplifiers, e.g. audio amplifiers using discontinuously variable devices, e.g. switch-operated
Description
産業上の利用分野
本発明は、デイジタル制御により信号増幅の利
得を制御する可変利得制御回路に関する。
従来例の構成とその問題点
従来の可変利得制御回路は第１図に示すように
構成されており、信号増幅器Ａと可変抵抗Ｒ１１
とを組み合わせて利得を変化させる構成のものが
用いられている。なお第１図に示すように抵抗Ｒ
１１を変化させるもの以外に、抵抗Ｒ１２を変化
させるもの、あるいはＲ１１とＲ１２の双方を変
化させる構成が可能であるが、通常は第２図に例
示するようなＲ―２Ｒのはしご型抵抗網を採用し
たＲ１１可変型の構成が一般に用いられる。
上記Ｒ―２Ｒはしご型抵抗網は、入力デイジタ
ルデータに対して線型的な利得を実現でき、また
２種類の抵抗で構成可能なため製造上有利であ
る。すなわち現在、乗算型DA変換器として容易
に入手可能であるため、第２図に示した回路は乗
算型DA変換器と演算増幅器とのみにより構成す
ることができる。
この従来の回路において、バツフアとして示す
ブロツクBAは、単に入力デイジタル信号でアナ
ログスイツチを切換えることを示しているが、こ
の回路の場合利得Vp〜VIは
Vp／VI＝ｘ／2n（ｘ＝０〜（2n−１） ……１
で表わされる。
この特性は第３図のイに示すように、入出力特
性が線型なためdBリニア（対数リニア）な特性
からは大幅にずれている。従つて、低レベルの信
号を増幅する場合、入力デイジタル信号の制御分
解能が荒くなり、可変利得制御回路として適当で
はない。
この問題に対して従来より実施されている方式
として、対数変換を行うものがある。この方式
は、前記第２図のバツフアBAを対数変換を行う
論理回路に変更するものである。この変更を行な
うことによりその特性を第３図のロに示す如く対
数リニアにすることができる。
しかしながら、この対数変換論理回路はそれ自
体回路数が多く、また低レベル入力に対する制御
分解能を細かくするためにはＲ―２Ｒのはしご型
抵抗網とアナログスイツチの段数を多くする必要
があり、新たに製造上の不利な問題が生じる。
発明の目的
本発明は、上記のような従来の問題点を解消し
ようとするもので、回路規模がほぼ従来と同程度
で、しかも対数リニアな特性をもつ可変利得制御
回路を提供することを目的とする。
発明の構成
本発明は、割算器と加減算器とを組み合わせる
ことによつて上述の目的を達成せんとするもので
ある。すなわち本発明の可変利得制御回路は、演
算増幅器とその帰還回路とからなる割算器と、他
の演算増幅器と固定抵抗とからなる加減算器とを
設けてなるもので、該加減算器は前記割算器出力
に加減算を行つて出力するものである。
実施例の説明
本発明の方式は、以下の２式がｘ＝2n-1の近傍
で近似的に等しいという点を利用するものであ
る。
上記２式を実現する回路は、３式に比べて簡易
であるから、これに基いて具体的回路を構成す
る。
以下、実際の回路に基づき具体的に説明する。
第４図は、本発明による可変利得制御回路の１
実施例の概略構成を示すものである。１１は入力
電圧VIの加わる入力端子、１２は出力電圧Vp出
力される出力端子である。１３は、固定抵抗Ｒ４
４と可変抵抗Ｒ４５および演算増幅器A1により
構成された割算器である。１４は、固定抵抗Ｒ４
１，Ｒ４２，Ｒ４３と演算増幅器A2により構成
された加減算である。
上記実施例のさらに具体的な回路例を第５図に
示す。この回路では前記割算器１３の可変抵抗を
はしご型抵抗網により構成したものである。固定
抵抗Ｒ５４と、Ｒ―２Ｒはしご型抵抗網と、アナ
ログスイツチＳ（Ｓ１，Ｓ２……Sn）と、演算増
幅器A1とにより割算器１３が構成される。この
回路では、デイジタル入力としてｎビツトの値が
外部から設定されるものとする。このデイジタル
入力をｘとすれば、ｘ＝θ〜2n−１、割算器の増
幅度ADは
AD＝−（Ｒ／R54）・（2n／ｘ） ……４
一般には、Ｒ５４は乗算型DA変換器の内部抵
抗を使用するので、R54＝Ｒである。従つて、
AD＝−2n／ｘ ……５
次に、固定抵抗Ｒ５１，Ｒ５２，Ｒ５３により
割算器１３の出力と入力VIが加算され、全回路
の増幅度ATは
AT＝Vp／VI＝R53（１／R52＋AD／R51）
＝R53（１／R52−2o／（R51・ｘ）） ……６
この式６は、ｘ＝2n-1の近傍でexp（２−ｘ／2n-2）
に近似し、対数リニアな特性を示す。
この回路の特性を第６図に示す。この場合、
R51＝5KΩ，R52＝5KΩ，R53＝250Ωとし、加減
算器自身が−26dBの減衰効果をもつものとする。
図において、イは本回路の特性を、ロは（exp
（２−ｘ／2n-2）／20を、ハは
INDUSTRIAL APPLICATION FIELD The present invention relates to a variable gain control circuit that controls the gain of signal amplification by digital control. Configuration of conventional example and its problems A conventional variable gain control circuit is configured as shown in Fig. 1, and includes a signal amplifier A and a variable resistor R11.
A structure in which the gain is changed by combining these is used. Furthermore, as shown in Fig. 1, the resistance R
In addition to changing resistance R11, it is possible to change resistance R12, or to change both R11 and R12, but usually an R-2R ladder-type resistance network as shown in Fig. 2 is used. The adopted R11 variable type configuration is generally used. The R-2R ladder type resistor network described above is advantageous in manufacturing because it can realize a linear gain with respect to input digital data and can be configured with two types of resistors. That is, since a multiplication type DA converter is easily available at present, the circuit shown in FIG. 2 can be constructed only from a multiplication type DA converter and an operational amplifier. In this conventional circuit, the block BA shown as a buffer simply switches an analog switch with an input digital signal, but in this circuit the gain V p ~V I is V p /V I = x/2 n (x = 0 ~ (2 n -1) ...1) As shown in Figure 3 A, this characteristic is significantly different from the dB linear (logarithmically linear) characteristic because the input/output characteristic is linear. Therefore, when amplifying a low-level signal, the control resolution of the input digital signal becomes coarse, making it unsuitable as a variable gain control circuit. There is a method that performs conversion. This method changes the buffer BA shown in Figure 2 to a logic circuit that performs logarithmic conversion. By making this change, its characteristics can be changed to logarithm as shown in Figure 3 (B). However, this logarithmic conversion logic circuit itself has a large number of circuits, and in order to increase the control resolution for low-level inputs, the number of stages of the R-2R ladder resistor network and analog switches must be increased. Object of the Invention The present invention is an attempt to solve the above-mentioned conventional problems, and the circuit size is almost the same as that of the conventional one. It is an object of the present invention to provide a variable gain control circuit having logarithmically linear characteristics.Structure of the Invention The present invention aims to achieve the above object by combining a divider and an adder/subtractor. That is, the variable gain control circuit of the present invention is provided with a divider made up of an operational amplifier and its feedback circuit, and an adder/subtractor made up of another operational amplifier and a fixed resistor. It performs addition and subtraction on the output of the divider and outputs the results.Description of EmbodimentThe method of the present invention utilizes the point that the following two equations are approximately equal in the vicinity of x=2 n-1 . be. Since the circuit that realizes the above two equations is simpler than the third equation, a specific circuit will be constructed based on this. A detailed explanation will be given below based on an actual circuit. FIG. 4 shows one of the variable gain control circuits according to the present invention.
1 shows a schematic configuration of an example. Reference numeral 11 represents an input terminal to which an input voltage V I is applied, and reference numeral 12 represents an output terminal from which an output voltage V p is output. 13 is a fixed resistor R4
4, a variable resistor R45, and an operational amplifier A1 . 14 is a fixed resistor R4
1, R42, R43 and an operational amplifier A2 . A more specific circuit example of the above embodiment is shown in FIG. In this circuit, the variable resistor of the divider 13 is constructed from a ladder-type resistor network. The divider 13 is constituted by the fixed resistor R54, the R-2R ladder resistor network, the analog switch S (S1, S2...Sn), and the operational amplifier A1 . In this circuit, it is assumed that an n-bit value is set externally as a digital input. If this digital input is x, then x = θ ~ 2 n -1, and the amplification degree A D of the divider is A D = - (R/R54) · (2 n /x) ... 4 Generally, R54 uses the internal resistance of the multiplication type DA converter, so R54=R. Therefore, A D =-2 n /x ...5 Next, the output of the divider 13 and the input V I are added by fixed resistors R51, R52, and R53, and the amplification degree A T of the entire circuit is A T = V p /V I = R53 (1/R52 + AD/R51) = R53 (1/R52-2 o / (R51・x)) ...6 This equation 6 shows that exp(2 -x/2 n-2 ) and exhibits log-linear characteristics. The characteristics of this circuit are shown in FIG. in this case,
Assume that R51 = 5KΩ, R52 = 5KΩ, and R53 = 250Ω, and the adder/subtractor itself has a -26dB attenuation effect. In the figure, A indicates the characteristics of this circuit, and B indicates (exp
(2-x/2 n-2 )/20, Ha is
【式】
を表わしている。
第６図から見られるとおり、本回路の特性はｘ
＝２（-1）近傍では曲線２によく近似し、０から
−48dBまでは単調増幅性は保証されており、自
動利得制御装置（AGC）への応用が充分に可能
である。
発明の効果
上記実施例より明らかなように本発明によれば
簡単な回路によりほぼ対数リニアな特性が得られ
る可変利得制御回路を構成することができ、しか
も、フイードバツク抵抗は２種類の抵抗により作
成可能なため、LSIの作成上においても精度が高
めることができる。またこの本発明の構成を用い
た自動利得制御回路（AGC）は、各種の信号処
理装置に応用され、アナログ系回路を大幅に縮少
する効果を有するものである。[Formula] represents. As seen from Figure 6, the characteristics of this circuit are x
It closely approximates curve 2 near =2( -1 ), and monotonic amplification is guaranteed from 0 to -48 dB, making it fully possible to apply it to an automatic gain control device (AGC). Effects of the Invention As is clear from the above embodiments, according to the present invention, a variable gain control circuit that can obtain almost logarithmically linear characteristics can be constructed with a simple circuit, and the feedback resistor is made of two types of resistors. Since this is possible, accuracy can also be improved in LSI creation. Further, an automatic gain control circuit (AGC) using the configuration of the present invention is applied to various signal processing devices, and has the effect of significantly reducing the size of analog circuits.
第１図は従来の可変利得制御回路の結線図、第
２図は従来の可変利得制御回路の結線図、第３図
はその特性図、第４図は本発明の一実施例による
可変利得制御回路の結線図、第５図はその具体的
な構成を示す結線図、第６図はその特性図であ
る。
Ｒ１１，Ｒ４５……可変抵抗、Ｒ４４，Ｒ４
１，Ｒ４２，Ｒ４３，Ｒ５１，Ｒ５２，Ｒ５３，
Ｒ５４……固定抵抗、Ａ，A1，A2……演算増幅
器、Ｓ１，Ｓ２…Sn……アナログスイツチ、１
３……割算器、１４……加減算器。
Fig. 1 is a wiring diagram of a conventional variable gain control circuit, Fig. 2 is a wiring diagram of a conventional variable gain control circuit, Fig. 3 is its characteristic diagram, and Fig. 4 is a variable gain control according to an embodiment of the present invention. The wiring diagram of the circuit, FIG. 5 is a wiring diagram showing its specific configuration, and FIG. 6 is its characteristic diagram. R11, R45...variable resistor, R44, R4
1, R42, R43, R51, R52, R53,
R54...Fixed resistance, A, A1 , A2 ...Operation amplifier, S1, S2...Sn...Analog switch, 1
3...Divider, 14...Adder/subtractor.
Claims (1)
続された演算増幅器およびこの演算増幅器の出力
を可変抵抗器を介して前記演算増幅器の入力側に
フイードバツクする帰還回路から構成される割算
器と、前記入力アナログ信号の利得値を制御する
デイジタル制御信号を発生する利得制御手段と、
前記割算器の出力と前記入力アナログ信号との加
減算を行なう加減算器とを備え、前記可変抵抗器
は前記利得制御手段から発生したデイジタル制御
信号によつて制御されるスイツチ群に接続された
Ｒ―２Ｒはしご型抵抗網により構成したことを特
徴とする可変利得制御回路。1 a divider comprising an operational amplifier connected to an input analog signal terminal via a fixed resistor and a feedback circuit that feeds back the output of the operational amplifier to the input side of the operational amplifier via a variable resistor; gain control means for generating a digital control signal for controlling the gain value of the input analog signal;
an adder/subtracter for performing addition/subtraction between the output of the divider and the input analog signal, and the variable resistor is connected to a switch group controlled by a digital control signal generated from the gain control means. - A variable gain control circuit characterized by being configured with a 2R ladder-type resistor network.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23669583A JPH0234205B2 (en) | 1983-12-15 | 1983-12-15 | KAHENRITOKUSEIGYOKAIRO |
| US06/682,596 US4628276A (en) | 1983-12-15 | 1984-12-14 | Logarithmically linearly controlled variable gain amplifier |
| EP84308717A EP0146355B1 (en) | 1983-12-15 | 1984-12-14 | Logarithmically linearly controlled variable gain amplifier |
| DE8484308717T DE3478730D1 (en) | 1983-12-15 | 1984-12-14 | Logarithmically linearly controlled variable gain amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23669583A JPH0234205B2 (en) | 1983-12-15 | 1983-12-15 | KAHENRITOKUSEIGYOKAIRO |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60127811A JPS60127811A (en) | 1985-07-08 |
| JPH0234205B2 true JPH0234205B2 (en) | 1990-08-02 |
Family
ID=17004395
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23669583A Expired - Lifetime JPH0234205B2 (en) | 1983-12-15 | 1983-12-15 | KAHENRITOKUSEIGYOKAIRO |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0234205B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021066220A1 (en) | 2019-10-01 | 2021-04-08 | 엘지전자 주식회사 | Cleaner |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62200904A (en) * | 1986-02-28 | 1987-09-04 | Oki Electric Ind Co Ltd | Amplifier circuit |
-
1983
- 1983-12-15 JP JP23669583A patent/JPH0234205B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2021066220A1 (en) | 2019-10-01 | 2021-04-08 | 엘지전자 주식회사 | Cleaner |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60127811A (en) | 1985-07-08 |
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