JPH0127603B2 - - Google Patents
Info
- Publication number
- JPH0127603B2 JPH0127603B2 JP24868684A JP24868684A JPH0127603B2 JP H0127603 B2 JPH0127603 B2 JP H0127603B2 JP 24868684 A JP24868684 A JP 24868684A JP 24868684 A JP24868684 A JP 24868684A JP H0127603 B2 JPH0127603 B2 JP H0127603B2
- Authority
- JP
- Japan
- Prior art keywords
- resistor
- gain control
- control circuit
- circuit
- gain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/001—Digital control of analog signals
Landscapes
- Control Of Amplification And Gain Control (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は利得制御回路、特に可変利得増幅器の
利得をデイジタル信号によりデシベルリニアに制
御する回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a gain control circuit, and particularly to a circuit that linearly controls the gain of a variable gain amplifier using a digital signal in decibels.
従来より上記の目的を実現するため、本発明と
同一の発明者らおよび出願人によりなされた特許
出願（特願昭53−97209号、以下先願(1)と称する）
により、次の構成による利得制御回路が提案され
ている。すなわち、入出力端子間に一定の利得を
有する増幅器と可変抵抗回路を含む抵抗回路網と
を設け、上記可変抵抗回路網を複数の抵抗素子と
上記抵抗素子の選択切換えを行なう複数のスイツ
チとで構成し上記スイツチをデイジタル符号信号
によつて切換えて上記入力出端子間の利得をデシ
ベルリニア制御し、上記入出端子間の伝達関数を
Ｙ＋１／Ｙ−１＋（AG＋Ｂ）／Ｙ＋１／Ｙ−１−（AG
＋Ｂ）
（Ｙは１でない定数、Ａ、Ｂは０でない定数、Ｇ
は０≦Ｇ＜１の変数、−１＜AG＋Ｂ＜１）と設
定し、上記可変抵抗回路がｎビツトの２進デイジ
タル信号の各ビツト信号ｉ（ｉ＝０、１、２……
ｎ−１）によつて開閉される複数のスイツチSWi
と、上記各スイツチと直列に接続され
Ｒ／gi（gi＝2n-1-i／2n−１）の抵抗値を有する抵抗
を並
列に接続されR/Gの可変抵抗値を有する回路か、
または上記各スイツチに並列に接続されたgiＲの
抵抗値を有する抵抗を直列に接続されたGRの可
変抵抗値を有する回路のいずれか一方で構成され
た利得制御回路である。
In order to achieve the above object, a patent application (Japanese Patent Application No. 53-97209, hereinafter referred to as "Prior Application (1)") was filed by the same inventors and applicants as the present invention.
proposed a gain control circuit with the following configuration. That is, an amplifier having a constant gain and a resistance network including a variable resistance circuit are provided between input and output terminals, and the variable resistance network is formed by a plurality of resistance elements and a plurality of switches for selectively switching the resistance elements. The gain between the input and output terminals is controlled linearly in decibels by switching the switch using a digital code signal, and the transfer function between the input and output terminals is Y+1/Y-1+(AG+B)/Y+1/Y-1-. (A.G.
+B) (Y is a constant that is not 1, A and B are constants that are not 0, G
is set as a variable of 0≦G<1, -1<AG+B<1, and the variable resistor circuit inputs each bit signal i (i=0, 1, 2...) of the n-bit binary digital signal.
multiple switches SW i opened and closed by n-1)
and a resistor connected in series with each of the above switches and having a resistance value of R/g i (g i =2 n-1-i /2 n -1) is connected in parallel and has a variable resistance value of R/G. A circuit?
Alternatively, it is a gain control circuit configured with either a resistor having a resistance value of g i R connected in parallel to each of the above-mentioned switches, and a circuit having a variable resistance value of GR connected in series.
上記(1)式はＡ＝−２、Ｂ＝１とし、利得Ｇを０
〜１まで可変したとき、伝達関数ＶはＹ〜１／Ｙ
まで変化し、近似的にデシベルリニアな特性が得
られる。ここで、上記(1)式と理想特性Y-2G+1との
差すなわち誤差をデシベルで表わせば、第１図に
示す特性となる。この場合、同図の曲線Ａは利得
可変範囲が10dB（Ｙ＝1.78）、曲線Ｂは利得可変
範囲が20dB（Ｙ＝3.16）、曲線Ｃは利得可変範囲
が30dB（Ｙ＝5.62）、さらに曲線Ｄは利得可変範
囲が40dB（Ｙ＝10）の特性を示し、可変量Ｙを増
加すると誤差は飛躍的に増加する。
The above equation (1) assumes A=-2, B=1, and the gain G is 0.
When variable up to ~1, the transfer function V is Y~1/Y
Approximately linear decibel characteristics can be obtained. Here, if the difference or error between the above equation (1) and the ideal characteristic Y -2G+1 is expressed in decibels, the characteristic shown in FIG. 1 is obtained. In this case, curve A in the figure has a gain variable range of 10 dB (Y = 1.78), curve B has a gain variable range of 20 dB (Y = 3.16), curve C has a gain variable range of 30 dB (Y = 5.62), and D exhibits a characteristic in which the gain variable range is 40 dB (Y=10), and as the variable amount Y increases, the error increases dramatically.
本発明は上記(1)式の特性を有する利得制御回路
（以下、第１の利得制御回路と称する）に、誤差
の生じない利得制御回路（以下、第２の利得制御
回路と称する）を付加することにより、可変量Ｙ
を減少させることなく、誤差を減少させることを
特徴とするものである。
The present invention adds a gain control circuit that does not cause an error (hereinafter referred to as a second gain control circuit) to a gain control circuit having the characteristic of the above formula (1) (hereinafter referred to as a first gain control circuit). By doing so, the variable amount Y
This method is characterized by reducing the error without reducing the error.
ここで、第１の利得制御回路としては前記先願
(1)に示されたもののほか、同じく本発明と同一考
案者および出願人による実用新案登録出願（実願
昭55−102814号、以下先願(2)と称する）があり、
これらによれば比較的可変範囲の狭い範囲で容易
にデシベルリニア特性が得られる。
Here, as the first gain control circuit, the first gain control circuit is
In addition to what is shown in (1), there is also an application for utility model registration (Utility Model Application No. 102814/1989, hereinafter referred to as Prior Application (2)) by the same inventor and applicant as the present invention.
According to these, decibel linear characteristics can be easily obtained in a relatively narrow variable range.
次に第２の利得制御回路、すなわち誤差を生じ
ることなく広範囲に利得を切換えうる回路として
は第２図に示すように、抵抗回路網およびこれを
切換えるアナログスイツチよりなる回路により目
的を達成することができる。 Next, as a second gain control circuit, that is, a circuit that can switch the gain over a wide range without causing errors, the purpose is achieved by a circuit consisting of a resistor network and an analog switch that switches it, as shown in Figure 2. Can be done.
同図において、入力端子１と出力端子２の間に
設けた抵抗３と、アナログスイツチ（以下スイツ
チと略記する）４，５および抵抗６，７，８，９
を備え、スイツチ４，５を切換えることにより、
(1) 抵抗６と７を抵抗３に並列接続する。 In the figure, a resistor 3 provided between an input terminal 1 and an output terminal 2, analog switches (hereinafter abbreviated as switches) 4, 5, and resistors 6, 7, 8, 9
By switching switches 4 and 5, (1) resistors 6 and 7 are connected in parallel to resistor 3;
(2) 抵抗７を抵抗３に並列接続すると共に、抵抗
８を通じて出力端子２を接地する。(2) Resistor 7 is connected in parallel to resistor 3, and output terminal 2 is grounded through resistor 8.
(3) 抵抗６を抵抗３に並列接続すると共に、抵抗
９を通じて出力端子２を接地する。(3) Connect the resistor 6 in parallel to the resistor 3, and ground the output terminal 2 through the resistor 9.
(4) 入出力端子１，２間には抵抗３のみが接続さ
れると共に、抵抗８，９を並列に通じて出力端
子２を接地する。(4) Only a resistor 3 is connected between the input/output terminals 1 and 2, and the output terminal 2 is grounded through resistors 8 and 9 in parallel.
という４通りの状態が得られるようにする。なお
各抵抗およびスイツチに付記したように、上記抵
抗３，６，７，８，９はそれぞれコンダクタンス
がg0，ga0，ga1，gb0，gb1なるものとする。また、
スイツチ４の状態をa0で表わし、抵抗６側に接続
したときa0＝０、抵抗８側に接続したときa0＝１
とする。また、同じくスイツチ５の情態をa1で表
わし、抵抗７側に接続したときa0＝０、抵抗９側
に接続したときa1＝１とする。The following four states are obtained. As noted above for each resistor and switch, the conductances of the resistors 3, 6, 7, 8, and 9 are g 0 , g a0 , g a1 , g b0 , and g b1 , respectively. Also,
The state of switch 4 is represented by a 0. When connected to the resistor 6 side, a 0 = 0, and when connected to the resistor 8 side, a 0 = 1.
shall be. Similarly, the state of the switch 5 is expressed by a 1 , and when connected to the resistor 7 side, a 0 =0, and when connected to the resistor 9 side, a 1 =1.
かくすれば、第２図の回路の伝達関数は次式で
表わされる。 Thus, the transfer function of the circuit of FIG. 2 is expressed by the following equation.
この場合、スイツチ４，５の切換状態すなわち
a0，a1の状態に応じて伝達関数V0／Vnが１、
１／K1、１／K2、１／K3なる４ステツプの値を
とるものとし、次式が成立するg0，ga0，ga1，
gb0，gb1を求める。 In this case, the switching state of switches 4 and 5, i.e.
Depending on the state of a 0 and a 1 , the transfer function V 0 /V n is 1,
Assume that the values of 4 steps are 1/K 1 , 1/K 2 , and 1/K 3 , and g 0 , g a0 , g a1 , and the following equation holds true:
Find g b0 and g b1 .
a0gb0＋a1gb1＝（Kn−１）（g0＋0ga0＋1ga1）
……(3)
ただし、ｍ＝１〜３
第２図の回路で１ステツプ当りの減衰量を
XdBとし、誤差のないデシベルリニアな構成と
するためには、Knを次の形とすればよい。 a 0 g b0 + a 1 g b1 = (K n -1) (g 0 + 0 g a0 + 1 g a1 )
...(3) However, m = 1 to 3 In the circuit shown in Figure 2, the attenuation per step is
In order to obtain a linear configuration in decibels with no error, K n may be set to the following form.
上記(3)式から、各コンダクタンスは次のように
求められる。 From the above equation (3), each conductance is calculated as follows.
なお、gb0に対する条件は、各コンダクタンス
が正でければならないことから、
（K3−K2）g0≧gb0≧（K1−１）g0 ……(6)
が成立するようにgb0を選ぶことが必要である。 Note that the condition for g b0 is that each conductance must be positive, so that (K 3 − K 2 ) g 0 ≧ g b0 ≧ (K 1 − 1) g 0 ...(6) holds. It is necessary to choose g b0 .
ここで、ga0＝０として上記(3)式を解けば、
ga1＝（K1 2−１）g0
gb0＝K1 2（K1−１）g0
gb1＝（K1 2−１）g0
となり、コンダクタンスga1，gb1は同一素子で実
現でき、第２図の回路は第３図ａのようになる。
ただし、図示のように抵抗１１は
K1 2（K1−１）g0
抵抗１２は
（K1 2−１）g0
なるコンダクタンスを有する。 Here, if we solve the above equation (3) with g a0 = 0, g a1 = (K 1 2 - 1) g 0 g b0 = K 1 2 (K 1 - 1) g 0 g b1 = (K 1 2 -1) g 0 , and the conductances ga1 and g b1 can be realized by the same element, and the circuit of FIG. 2 becomes as shown in FIG. 3a.
However, as shown in the figure, the resistor 11 has a conductance of K 1 2 (K 1 -1)g 0 and the resistor 12 has a conductance of (K 1 2 -1)g 0 .
また、コンダクタンスga1＝０とおけば、同様
に(3)式より、
ga0＝（K1−１）g0
gb0＝（K1−１）g0
gb1＝K1（K1 2−１）g0
となり、コンダクタンスga0，gb0は同一素子で実
現でき、第２図の回路は第３図ｂの形となる。た
だし、抵抗１３は（K1−１）g0、抵抗１４はK1
（K1 2−１）g0なるコンダクタンスを有する。 Also, if the conductance g a1 = 0, similarly from equation (3), g a0 = (K 1 - 1) g 0 g b0 = (K 1 - 1) g 0 g b1 = K 1 (K 1 2 -1) g 0 , and the conductances g a0 and g b0 can be realized by the same element, and the circuit of FIG. 2 becomes the form of FIG. 3 b. However, the resistance 13 is (K 1 - 1) g 0 and the resistance 14 is K 1
It has a conductance of (K 1 2 −1)g 0 .
これら第３図ａ，ｂの回路は第２図の回路に比
べ、部品点数が少なく、５個必要とした抵抗素子
が３個で足りるという特徴がある。 The circuits shown in FIGS. 3a and 3b have a smaller number of components than the circuit shown in FIG. 2, and are characterized by requiring only three resistance elements instead of five.
なお、第２図、第３図の利得制御回路はともに
減衰側にのみ作用するが、例えば第３図ａ，ｂの
回路を第４図ａ，ｂに示すように演算増幅器１５
の帰還回路に挿入すると、演算増幅器１５の利得
が十分に大きければ、伝達関数はスイツチ４，５
の切換位置すなわちa0，a1の状態によつて１，
K1，K2，K3なる値をとり、利得側で動作する回
路となる。さらに、これは第２図の回についても
適用できる。 Note that both the gain control circuits in FIGS. 2 and 3 act only on the attenuation side, but for example, the circuits in FIGS.
If the gain of the operational amplifier 15 is sufficiently large, the transfer function will be the same as that of the switches 4 and 5.
1, depending on the switching position, that is, the state of a 0 and a 1 .
The circuit takes the values K 1 , K 2 , and K 3 and operates on the gain side. Furthermore, this can also be applied to the rounds in FIG.
同様に、第５図に示す利得制御回路も利得を４
ステツプに切換えられる誤差の生じない回路を提
供するものである。第５図において、抵抗１６〜
１９のコンダクタンスを図示の値とし、スイツチ
４，５の状態が抵抗１７，１９側に接続したとき
a0，a1を１とし、抵抗１６，１８側に接続したと
きa0，a1を０とし、増幅器１５の利得が非常に大
きければ、第５図の伝達関数は次の形で表わされ
る。 Similarly, the gain control circuit shown in FIG.
The present invention provides an error-free circuit that can be switched in steps. In FIG. 5, resistance 16~
When the conductance of 19 is set to the value shown in the diagram, and switches 4 and 5 are connected to resistors 17 and 19,
If a 0 and a 1 are set to 1, and when connected to the resistors 16 and 18, a 0 and a 1 are set to 0, and the gain of the amplifier 15 is very large, the transfer function in Fig. 5 is expressed in the following form. .
この場合、a0，a1の状態に応じて(7)式がデシベ
ルリニアな値をとることができることは明らかで
ある。また第５図を変形した第６図においても、
またスイツチ４，５をそれぞれ操作し抵抗２０，
２１を抵抗２２，２３に順次並列接続することに
より、デシベルリニアな利得制御回路を得ること
ができる。なお、これら第５図、第６図の回路は
減衰側のみでなく、利得側にも制御を行なうこと
ができる。 In this case, it is clear that equation (7) can take a decibel linear value depending on the states of a 0 and a 1 . Also, in Figure 6, which is a modification of Figure 5,
Also, operate switches 4 and 5 respectively to set resistance 20,
By sequentially connecting resistors 22 and 23 in parallel, a decibel linear gain control circuit can be obtained. Note that the circuits shown in FIGS. 5 and 6 can control not only the attenuation side but also the gain side.
次に、第７図は前記第１の利得制御回路に第４
図ｂの回路を付加した実施例を示す。第７図にお
いて、入出力端子１′，２′間の回路２４は前記の
先願(1)に示されたもので、これを第１の利得制御
回路として用い、図示の抵抗とスイツチ２４ａに
より比較的狭い範囲で利得を微細に変化する。ま
た、２５は第４図ｂに示した回路で、これを第２
の利得制御回路とし、デイジタル信号を加えてス
イツチ４，５を制御することにより、例えば０、
10dB、20dB、30dBの切換え増幅を行ない、回路
２４により０〜10dBの利得可変範囲の制御回路
を構成すれば、全体として40dBの範囲を微細に
変化できる利得制御回路を得ることができる。 Next, FIG. 7 shows that a fourth gain control circuit is added to the first gain control circuit.
An example in which the circuit of FIG. b is added is shown. In FIG. 7, a circuit 24 between input and output terminals 1' and 2' is shown in the above-mentioned prior application (1), and is used as a first gain control circuit. Finely changes the gain within a relatively narrow range. Further, 25 is the circuit shown in FIG. 4b, which is connected to the second
By controlling the switches 4 and 5 by adding a digital signal to the gain control circuit, for example, 0,
By performing switching amplification of 10 dB, 20 dB, and 30 dB and constructing a control circuit with a variable gain range of 0 to 10 dB using the circuit 24, it is possible to obtain a gain control circuit that can finely vary a range of 40 dB as a whole.
この場合の誤差は回路２４のみで発生し、その
誤差特性は前記第１図に曲線Ａで示した可変範囲
10dBの場合と等しく、誤差の最大値は±0.05dB
という極めて微小なものである。これに対し、回
路２５を用いずに回路２４のみで40dBの可変範
囲を得るようにすると、第１図の曲線Ｄから明ら
かなように誤差の最大値は±2.7dBに達する。こ
のように、回路２５を付加することにより、誤差
の大幅な低減を図ることができる。なお、第７図
における回路２４と２５は順序を逆転しても同様
の結果が得られることは明らかである。 In this case, the error occurs only in the circuit 24, and its error characteristics are within the variable range shown by curve A in FIG.
Equivalent to 10dB, maximum error is ±0.05dB
It is extremely small. On the other hand, if a variable range of 40 dB is obtained using only the circuit 24 without using the circuit 25, the maximum value of the error reaches ±2.7 dB, as is clear from the curve D in FIG. In this way, by adding the circuit 25, errors can be significantly reduced. It is clear that the same result can be obtained even if the order of circuits 24 and 25 in FIG. 7 is reversed.
また回路２４は、上記実施例に限定されること
なく、(1)式の如き伝達関数をもつ回路形式すべて
に適用することができることは明らかであり、例
えば第８図のように構成することもできる。ここ
で、回路２６は前記先願(2)に示されたものであ
り、抵抗およびスイツチ２６ａにより、ある範囲
内で微細な利得制御が可能な利得制御回路であ
る。これに第５図の場合と同様に回路２５を組合
わせることにより、広範囲にわたり微細な利得制
御を行なうことができる。 Furthermore, it is clear that the circuit 24 is not limited to the above embodiment, but can be applied to any circuit type having a transfer function as shown in equation (1). For example, the circuit 24 may be configured as shown in FIG. can. Here, the circuit 26 is shown in the aforementioned prior application (2), and is a gain control circuit that allows fine gain control within a certain range using a resistor and a switch 26a. By combining this with the circuit 25 as in the case of FIG. 5, fine gain control can be performed over a wide range.
以上述べたように、本発明によるときは大きな
可変範囲を必要とするデシベルリニアな利得制御
回路において誤差を非常に小さくすることがで
き、実用上の効果は極めて大きなものである。
As described above, according to the present invention, errors can be made extremely small in a decibel linear gain control circuit that requires a large variable range, and the practical effects are extremely large.
第１図はデシベルリニア回路において利得を変
化したときの誤差の大きさを示す特性図、第２図
は誤差を生じることなく広範囲に利得を切換え得
る回路（第２の利得制御回路）の実施例を示す回
路図、第３図ａ，ｂおよび第４図ａ，ｂは第２図
の回路の各変形例を示す回路図、第５図および第
６図は第２の利得制御回路の他の実施例およびそ
の変形例を示す回路図、第７図および第８図は広
範囲に利得を微細変化し得る利得制御回路の各実
施例を示す回路図である。
１，１′……入力端子、２，２′……出力端子、
３，６〜９，１１〜１４，１６〜２３……抵抗、
４，５……アナログスイツチ、１５……演算増幅
器、２４，２６……第１の利得制御回路、２５…
…第２の利得制御回路。
Figure 1 is a characteristic diagram showing the magnitude of error when the gain is changed in a decibel linear circuit, and Figure 2 is an example of a circuit (second gain control circuit) that can switch the gain over a wide range without causing errors. 3a, b and 4a, b are circuit diagrams showing variations of the circuit in FIG. 2, and FIGS. 5 and 6 are circuit diagrams showing other variations of the second gain control circuit. 7 and 8 are circuit diagrams showing each embodiment of a gain control circuit that can finely change the gain over a wide range. 1, 1'... Input terminal, 2, 2'... Output terminal,
3, 6-9, 11-14, 16-23...resistance,
4, 5... Analog switch, 15... Operational amplifier, 24, 26... First gain control circuit, 25...
...Second gain control circuit.
Claims (1)
幅器と可変抵抗回路を含む抵抗回路網とを設け、
上記可変抵抗回路網を複数の抵抗素子と上記抵抗
素子の選択切換えを行なう複数のスイツチとで構
成し上記スイツチをデイジタル符号信号によつて
切換えて上記入力出端子間の利得をデシベルリニ
ア制御し、上記入出端子間の伝達関数を Ｙ＋１／Ｙ−１＋（AG＋Ｂ）／Ｙ＋１／Ｙ−１−（AG
＋Ｂ） （Ｙは１でない定数、Ａ、Ｂは０でない定数、Ｇ
は０≦Ｇ＜１の変数、−１＜AG＋Ｂ＜１）と設
定し、上記可変抵抗回路がｎビツトの２進デイジ
タル信号の各ビツト信号ｉ（ｉ＝０、１、２……
ｎ−１）によつて開閉される複数のスイツチSWi
と、上記各スイツチと直列に接続され Ｒ／gi（gi＝2n-1-i／2n−１）の抵抗値を有する抵抗
を並 列に接続されR/Gの可変抵抗値を有する回路か、
または上記各スイツチに並列に接続されたgiＲの
抵抗値を有する抵抗を直列に接続されたGRの可
変抵抗値を有する回路のいずれか一方で構成され
ている第１の利得制御回路、ならびに第２の入出
力端子間に設けた第１の抵抗と、互いに一端を上
記第１の抵抗の入力側端子に共通接続した第２、
第３の抵抗と、互いに一端を接地した第４、第５
の抵抗とを具備し、上記第２と第４の抵抗の他端
を第１のスイツチにより切換えて上記第１の抵抗
の出力側端子に接続し、上記第３と第５の抵抗の
他端を第２のスイツチにより切換えて上記第１の
抵抗の上記出力側端子に接続する第２の利得制御
回路よりなり、上記第２の利得制御回路をデシベ
ルリニア制御するために、上記第１の抵抗のコン
ダクタンスをg0、上記第２、第３の抵抗のコンダ
クタンスをga0，ga1、上記第４、第５の抵抗のコ
ンダクタンスをgb0，gb1としたとき、 ga1＝１／Ｋ−１gb0−g0 ga0＝１／K2−１｛（K3−１）g0−gb0｝−g0 gb1＝（K3−１）g0−gb0 （ここで、Ｋは定数） となるように設定し、上記第１と第２の利得制御
回路を互いに縦続接続したことを特徴とする利得
制御回路。 ２ 前記第１の利得制御回路と、該第１の利得制
御回路に縦続接続された演算増幅器とを具備し、
上記演算増幅器の出力を前記第２の利得制御回路
を通じて上記演算増幅器の逆相側入力端子に加え
ることを特徴とする特許請求の範囲第１項記載の
利得制御回路。[Claims] 1. An amplifier having a constant gain and a resistance network including a variable resistance circuit are provided between the first input and output terminals,
The variable resistance network is configured with a plurality of resistance elements and a plurality of switches for selectively switching the resistance elements, and the switches are switched by a digital code signal to linearly control the gain between the input and output terminals in decibels, The transfer function between the above input and output terminals is Y+1/Y-1+(AG+B)/Y+1/Y-1-(AG
+B) (Y is a constant that is not 1, A and B are constants that are not 0, G
is set as a variable of 0≦G<1, -1<AG+B<1, and the variable resistance circuit receives each bit signal i (i=0, 1, 2...) of the n-bit binary digital signal.
multiple switches SW i opened and closed by n-1)
and a resistor connected in series with each of the above switches and having a resistance value of R/g i (g i =2 n-1-i /2 n -1) is connected in parallel and has a variable resistance value of R/G. A circuit?
or a first gain control circuit configured with one of a circuit having a variable resistance value of GR connected in series with a resistor having a resistance value of g i R connected in parallel to each of the above switches, and a first resistor provided between the second input and output terminals; a second resistor whose one end is commonly connected to the input terminal of the first resistor;
a third resistor, and fourth and fifth resistors whose ends are grounded.
the other ends of the second and fourth resistors are switched by a first switch and connected to the output side terminal of the first resistor, and the other ends of the third and fifth resistors are connected to the output terminal of the first resistor. a second gain control circuit which is switched by a second switch and connected to the output side terminal of the first resistor; When the conductance of the resistor is g 0 , the conductance of the second and third resistors is g a0 , g a1 , and the conductance of the fourth and fifth resistor is g b0 and g b1 , g a1 =1/K− 1g b0 −g 0 g a0 = 1/K 2 −1 {(K 3 −1) g 0 −g b0 }−g 0 g b1 = (K 3 −1) g 0 −g b0 (Here, K is A gain control circuit characterized in that the first and second gain control circuits are connected in cascade to each other. 2 comprising the first gain control circuit and an operational amplifier cascade-connected to the first gain control circuit,
2. The gain control circuit according to claim 1, wherein the output of the operational amplifier is applied to the negative phase side input terminal of the operational amplifier through the second gain control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24868684A JPS60137110A (en) | 1984-11-27 | 1984-11-27 | Gain control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24868684A JPS60137110A (en) | 1984-11-27 | 1984-11-27 | Gain control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60137110A JPS60137110A (en) | 1985-07-20 |
| JPH0127603B2 true JPH0127603B2 (en) | 1989-05-30 |
Family
ID=17181824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24868684A Granted JPS60137110A (en) | 1984-11-27 | 1984-11-27 | Gain control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60137110A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5623228A (en) * | 1993-05-17 | 1997-04-22 | Dan Inbar | Non-linear feedback network providing a linear transfer function |
| US7545209B2 (en) * | 2006-09-07 | 2009-06-09 | National Semiconductor Corporation | Gain adjustment for programmable gain amplifiers |
| JP4863085B2 (en) * | 2007-06-25 | 2012-01-25 | アイシン精機株式会社 | Engine exhaust gas purification device and engine-driven air conditioner |
-
1984
- 1984-11-27 JP JP24868684A patent/JPS60137110A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60137110A (en) | 1985-07-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4468607A (en) | Ladder-type signal attenuator | |
| JP3450336B2 (en) | Combination and method of D / A converter and FIR filter using active current division | |
| CA1124806A (en) | Gain control circuit | |
| JP2532212B2 (en) | Variable attenuator | |
| US5283580A (en) | Current/resistor digital-to-analog converter having enhanced integral linearity and method of operation | |
| WO2001013513A1 (en) | Programmable low noise cmos differential voltage controlled logarithmic attenuator and method | |
| JPH11261764A (en) | Variable gain amplifier | |
| JPH07249951A (en) | Resistor network circuit device and variable gain device using the same | |
| US5349353A (en) | Method and apparatus for mixed analog and digital processing of delta modulated pulse streams including digital-to-analog conversion of a digital input signal | |
| US5973566A (en) | Discrete step variable gain inverting amplifier with constant ratio between adjacent gains | |
| EP0026579B1 (en) | A digital-to-analog conversion system | |
| JPH0127603B2 (en) | ||
| JPS6313572B2 (en) | ||
| JPH07254830A (en) | Electronic volume control circuit | |
| JPS62173809A (en) | Amplifier | |
| JPH04160912A (en) | Electronic variable resistor | |
| JPH0595239A (en) | Level control circuit | |
| JPH03232310A (en) | Variable gain amplifier, cable line equalizer and dummy cable line | |
| JP2001292065A (en) | Digital/analog converter | |
| JP2993449B2 (en) | Step attenuator | |
| JP4402201B2 (en) | Step attenuator | |
| JPS5827415A (en) | Variable attenuator | |
| JPS61145918A (en) | Electronic volume circuit | |
| JPH0221780Y2 (en) | ||
| JPH0450646Y2 (en) |