JPS62200904A - Amplifier circuit - Google Patents
Amplifier circuitInfo
- Publication number
- JPS62200904A JPS62200904A JP4377586A JP4377586A JPS62200904A JP S62200904 A JPS62200904 A JP S62200904A JP 4377586 A JP4377586 A JP 4377586A JP 4377586 A JP4377586 A JP 4377586A JP S62200904 A JPS62200904 A JP S62200904A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- operational amplifier
- input
- terminal
- resistors
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000007704 transition Effects 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000008901 benefit Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 1
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、高周波領域における利得および位相特性に優
れた増幅回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an amplifier circuit with excellent gain and phase characteristics in a high frequency region.
（従来の技術）
第２図は、従来の演算増幅器を用いた反転増幅回路にお
いて、利得制御を可能となした例を示すもので、図中、
１は演算増幅器、２は可変利得制御回路、Ｓ１〜ｓｎ
＆；ｔｎ個のアナログスイッチ、ＲＡ１〜ＲＡｎはｎ個
の利得選択用の抵抗、ＲＢは固定抵抗である。ｖ４算増
幅器１は、その（＋）入力端子が接地され、（−）入力
端子が各アナログスイッチ８１〜３ｎの各一端に接続さ
れ、アナログスイッチ８１〜３ｎの各他端は直列に接続
された抵抗ＲＡＩ〜ＲＡｎ及びＲＢの相互の接続点に接
続されている。(Prior Art) Figure 2 shows an example in which gain control is possible in an inverting amplifier circuit using a conventional operational amplifier.
1 is an operational amplifier, 2 is a variable gain control circuit, S1 to sn
&; tn analog switches, RA1 to RAn are n gain selection resistors, and RB is a fixed resistor. The (+) input terminal of the V4 arithmetic amplifier 1 was grounded, the (-) input terminal was connected to one end of each of the analog switches 81 to 3n, and the other ends of each of the analog switches 81 to 3n were connected in series. It is connected to the mutual connection point of the resistors RAI to RAn and RB.
前記回路において、アナログスイッチ８１〜Ｓｎのいず
れか一つ、例えばｍ番目のスイッチＳｌが可変利得制御
回路２によって導通状態にされると、抵抗ＲＡＩ〜ＲＡ
Ｍが入力抵抗となり、抵抗ＲＡｌ÷１〜ＲＡｎおよびＲ
Ｂが帰還抵抗となる。この時の利得Ａは、
となる。即ち、導通させるアナログスイッチＳ１〜３ｎ
を選択することによって、利ｍＡを自由に制御すること
が可能となる。In the circuit, when any one of the analog switches 81 to Sn, for example the m-th switch Sl, is rendered conductive by the variable gain control circuit 2, the resistors RAI to RA
M is the input resistance, resistance RAl÷1~RAn and R
B becomes the feedback resistance. The gain A at this time is as follows. That is, the analog switches S1 to 3n are made conductive.
By selecting , it becomes possible to freely control the profit mA.
なお、ここでアナログスイッチ８１〜３ｎの導通抵抗は
、演算増幅器１の入力インピーダンスが高いために無視
し得る。Note that the conduction resistance of the analog switches 81 to 3n can be ignored here because the input impedance of the operational amplifier 1 is high.
（発明が解決しようとする問題点）
しかしながら前記回路は、低周波領域では良好に動作す
るが、高周波領域では、第３図に示すようにアナログス
イッチ８１〜Ｓｎに基づく浮遊容ＩｃＩ〜Ｃｎの影響に
より、ｎ段の低域通過ろ波器と等価な構成になり、第４
図に実線あるいは破線で示ず入力信号ＩＮに対して、同
様に示す出力信号０ｔＪＴに大きな位相遷移が生じ、且
つ利得の低下が生じて、その詳細な設計が困難になる等
の問題点があった。(Problems to be Solved by the Invention) However, although the above circuit operates well in the low frequency range, in the high frequency range, as shown in FIG. As a result, the configuration becomes equivalent to an n-stage low-pass filter, and the fourth
There are problems such as a large phase transition occurs in the output signal 0tJT, which is also shown in the same way, with respect to the input signal IN, which is not shown by a solid line or a broken line in the figure, and a decrease in gain occurs, making detailed design difficult. Ta.
本発明は前記問題点を除去し、高周波領域における利（
ワおよび位相特性に優れた増幅回路を提供することを目
的とする。The present invention eliminates the above problems and provides advantages in the high frequency region.
The purpose of the present invention is to provide an amplifier circuit with excellent power and phase characteristics.
（問題点を解決するための手段）
本発明では前記問題点を解決するため、演算増幅器の（
−）入力端子に所定の入力抵抗を介して入力信号を入力
するとともに、該演算増幅器の出力信号を所定の帰還抵
抗を介して前記〈−）入力端子に帰還し、入力抵抗と帰
還抵抗との比に基づく利得で入力信号を増幅する増幅回
路において、前記入力信号と、前記演算増幅器の出力信
号を前記利得の逆数倍し且つ橿性を反転した信号とを加
算する手段を設け、前記加算手段の出力を演算増幅器の
（＋）入力端子に接続した。(Means for Solving the Problems) In order to solve the above-mentioned problems, in the present invention, the operational amplifier (
-) An input signal is input to the input terminal via a predetermined input resistor, and the output signal of the operational amplifier is fed back to the input terminal (<-) via a predetermined feedback resistor. In an amplifier circuit that amplifies an input signal with a gain based on a ratio, means is provided for adding the input signal and a signal obtained by multiplying the output signal of the operational amplifier by a reciprocal of the gain and inverting the linearity, The output of the means was connected to the (+) input terminal of the operational amplifier.
（作用）
本発明によれば、入力信号と出力信号との間に位相差が
ない場合は、加算手段における２つの信号が正確に逆位
相の信号となり、その出力にはなにも生じないが、位相
差が発生すると、加算手段にて該位相差に基づく信号が
出力され、この信号が演算増幅器の（＋）入力端子に基
準レベルとして与えられ、入力信号とその出力信号とが
一致すべく作用°する。(Function) According to the present invention, when there is no phase difference between the input signal and the output signal, the two signals in the adding means become signals with exactly opposite phases, and nothing occurs in the output. When a phase difference occurs, the addition means outputs a signal based on the phase difference, and this signal is given to the (+) input terminal of the operational amplifier as a reference level, so that the input signal and its output signal match. to act.
（実施例）
第１図は本発明の一実施例を示すもので、ここでは前記
同様、利得を制御可能とした例を示す。(Embodiment) FIG. 1 shows an embodiment of the present invention, and here, like the above, an example in which the gain can be controlled is shown.
図中、従来例と同一構成部分は同一符号をもって表わす
。即ち、２は可変利得ｆｉ、ｌＪ御回路、８１〜３ｎは
ｎ個のアナログスイッチ、３，４．５は演算増幅器、Ｒ
Ｃは入力抵抗、Ｒ［１〜ＲＥｎはｎ個の利得選択用の帰
還抵抗、ＲＦ、ＲＧ、ＲｈＧ、を抵抗である。また、破
線で囲まれた部分６は本発明の増幅回路の主要部を示ず
。In the figure, the same components as those of the conventional example are represented by the same reference numerals. That is, 2 is a variable gain fi, lJ control circuit, 81 to 3n are n analog switches, 3 and 4.5 are operational amplifiers, and R
C is an input resistor, R[1 to REn are n feedback resistors for gain selection, and RF, RG, and RhG are resistors. Furthermore, a portion 6 surrounded by a broken line does not indicate the main part of the amplifier circuit of the present invention.
アナログスイッチ８１〜３ｎの一端は演算増幅器３の（
＋）Ｑ子に接続され、他端はそれぞれ直列に接続された
抵抗Ｒ［１〜Ｒ［ｎの相互の接続点に接続されている。One end of the analog switches 81 to 3n is connected to the operational amplifier 3 (
+)Q terminal, and the other end is connected to the mutual connection point of the resistors R[1 to R[n] connected in series.
なお、演算増幅器３はボルテージフォロワを構成してい
る。Note that the operational amplifier 3 constitutes a voltage follower.
入力信号ＩＮは抵抗ＲＣを介して演算増幅ｉ！Ｓ４のく
−）端子に入力され、その出力信号０ＬＪＴ４は、抵抗
ＲＥ１〜ＲＥｎを介して（−）端子に帰還されている。The input signal IN is operationally amplified i! via a resistor RC. The output signal 0LJT4 is input to the (-) terminal of S4, and is fed back to the (-) terminal via the resistors RE1 to REn.
演算増幅器４における利４！？Ａ１は、ＡＩ＝−ΣＲＥ
ｉ／ ＲＣ・・・・・・（２）１巳１
となる。なお、抵抗ＲＣ，抵抗ＲＥ１〜Ｒｏ１１．演算
増幅器４は反転増幅回路を構成する。Benefit 4 in operational amplifier 4! ? A1 is AI=-ΣRE
i/RC...(2) 1 巳1 becomes. Note that the resistors RC, resistors RE1 to Ro11. The operational amplifier 4 constitutes an inverting amplifier circuit.
ここで、アナ［］グスイッチ８１〜３ｎのうちのｍ番目
のスイッチ５ｒａが導通されているとすると、入力信号
ＩＮに対して演算増幅器３の出力信号（ｌｌＴ３の総合
利得Ａ２は、
Ａ２−−Ａ２・Ｅ ＲＥｉ／ΣＲＥ； ・・・・
・・（３）ｉ−ｆ ｉ＝Ｉ
となる。Here, if the m-th switch 5ra of the analog switches 81 to 3n is conductive, the output signal of the operational amplifier 3 (total gain A2 of llT3 with respect to the input signal IN is A2--A2・E REi/ΣRE; ・・・・
...(3) ifi=I.
演算増幅器５と抵抗ＲＦ 、ＲＧ 、Ｒ１＋は加算手段
を構成するものであり、
ＲＧ ／Ｒ）Ｉ −１／Ａ Ｉ ・・・
・・・（４）ＲＦ −ＲＧ
・・・・・・（５）に設定しである。The operational amplifier 5 and the resistors RF, RG, and R1+ constitute an adding means, and RG/R)I-1/AI...
...(4)RF-RG
......(5) is set.
第５図に示すように、抵抗ＲＧには実線で示す入力信号
ＩＮが入力され、抵抗Ｒ１＋には演算増幅器４によって
反転増幅された破線で示す出力信号０ＵＴ４が入力され
、抵抗ＲＧ、ＲＨの相互の接続点Ｋにおいて、入力信号
ＩＮについてはそのまま、出力信号００丁については（
１／Ａｌ）倍されて加算され、即ち相互の位相差に基づ
くレベル差が演算増幅器４の（＋）端子に入力される。As shown in FIG. 5, the input signal IN shown by the solid line is input to the resistor RG, the output signal 0UT4 shown by the broken line which has been inverted and amplified by the operational amplifier 4 is input to the resistor R1+, and the mutual At the connection point K, the input signal IN remains unchanged, and the output signal 00 (
1/Al) and are added, that is, the level difference based on the mutual phase difference is input to the (+) terminal of the operational amplifier 4.
以上の構成においで、その動作を説明する。The operation of the above configuration will be explained.
入力信号ＩＮが低周波領域であつＣ、アナログスイッチ
８１〜Ｓｎ等の浮遊容かが作用せず、接続点Ｋにおける
抵抗ＲＧを介した入力信号ＩＮと、抵抗Ｒ１＋を介した
演算増幅器４の出力信号０ＵＴ４との間に、第６図（八
）に示すように位相差がない場合、信号ＩＮと信号０Ｕ
Ｔ４との加算結果、即ち、演算増幅器５の出力０ＵＴ５
には第６図（Ｂ）に示すようになにも出力されない。従
って、演算増幅器４は（＋）端子が接地された場合と等
価の利得へ１の増幅回路として機能する。If the input signal IN is in the low frequency range, floating capacitors such as C and analog switches 81 to Sn do not act, and the input signal IN via the resistor RG at the connection point K and the output of the operational amplifier 4 via the resistor R1+. If there is no phase difference between the signal IN and the signal 0UT4 as shown in Figure 6 (8), the signal IN and the signal 0U
The result of addition with T4, that is, the output of operational amplifier 5 0UT5
In this case, nothing is output as shown in FIG. 6(B). Therefore, the operational amplifier 4 functions as an amplifier circuit with a gain of 1 equivalent to that when the (+) terminal is grounded.
入力信号ＩＮ／／ｉ周波領域であって、アナログスイッ
チ８１〜Ｓｎにおいて、第３図に示すＣ１〜Ｑｎに準じ
た浮遊容量が作用する場合、信号ＩＮと信号０ＵＴ４と
は単純な反転関係にはならず、例えば角度αで示す位相
差を生じる。なお、この角度αは周波数の変化に伴って
変化する。In the input signal IN//i frequency region, when stray capacitance similar to C1 to Qn shown in FIG. 3 acts on the analog switches 81 to Sn, the signal IN and signal 0UT4 do not have a simple inversion relationship. For example, a phase difference shown by angle α is generated. Note that this angle α changes as the frequency changes.
ここで、例えば第６図（Ｃ）に示す位相θ１においては
、信号ＩＮがｒｏｖ ＜ボルト）」であり、また信号０
ＵＴ４が負の値となっていて、その電圧レベルの差（＝
ＩＮ＋０ＵＴ４）は負となる。Here, for example, at phase θ1 shown in FIG. 6(C), the signal IN is rov<volts), and the signal 0
UT4 has a negative value, and the difference in voltage level (=
IN+0UT4) is negative.
このレベル差をΔとザると、演算増幅器５の出力０ｔＪ
Ｔ５は、第６図（［１）に示１ように正のレベル差４と
なる。演算増幅器４は、その（・ト）端子のレベルが正
となり、信＠０ＵＴ４を増大すべく作用し、該信号０Ｕ
Ｔ４は第６図（Ｃ）における上方に押し上げられ、即ち
レベル差Ａを減少させるべく負帰還として作用してレベ
ル差ΔがｒＯＪに収斂し、よって位相差αが「０」に収
斂する。従って、演算増幅器４の出力信号０ＬＪＴ４は
入力信号ＩＮを位相遷移「０」でＡ１倍した信号となる
。If this level difference is expressed as Δ, then the output of the operational amplifier 5 is 0tJ
T5 has a positive level difference of 4 as shown in FIG. 6 ([1)]. The operational amplifier 4 has a positive level at its (T) terminal, acts to increase the signal @0UT4, and the signal 0U
T4 is pushed upward in FIG. 6(C), that is, acts as a negative feedback to reduce the level difference A, so that the level difference Δ converges to rOJ, and therefore the phase difference α converges to "0". Therefore, the output signal 0LJT4 of the operational amplifier 4 is a signal obtained by multiplying the input signal IN by A1 with a phase transition of "0".
抵抗ＲＥＩ〜ＲＥｎを介してアナログスイッチ８１〜３
ｎからとり出される４９号も、同様に位相遷移はｒＯＪ
であり、演算増幅器３の出力信号０ＵＴ３も同様に位相
遷移は「０」、利得は前記Ａ２となる。Analog switches 81-3 via resistors REI-REn
Similarly, the phase transition of No. 49 extracted from n is rOJ
Similarly, the output signal 0UT3 of the operational amplifier 3 has a phase transition of "0" and a gain of A2.
（発明の効果）
以上説明したように本発明によれば、位相遷移に基づく
量を検出し、これを演算増幅器に帰還させるようになし
たため、低周波から高周波に至るまで一定の利得および
位相特性を有する増幅回路が得られ、従って、演算増幅
器の出力側に浮遊容量等を有する他の回路要素が介在す
る場合でも、これを補償でき、これらの応用のための設
計が容易となる等の利点がある。(Effects of the Invention) As explained above, according to the present invention, the amount based on the phase transition is detected and fed back to the operational amplifier, so that the gain and phase characteristics are constant from low frequency to high frequency. Therefore, even if other circuit elements having stray capacitance etc. are present on the output side of the operational amplifier, this can be compensated for, and the design for these applications is facilitated. There is.
第１図は本発明の増幅回路の一実施例を示す回路図、第
２図は従来の増幅回路の一例を示す回路図、第３図は第
２図の回路の浮遊容量の説明図、第４図は第２図の回路
の動作の波形図、第５図は第１図の要部を説明するため
の回路図、第６図は第５図に関わる動作の波形図である
。
４．５・・・演算増幅器、ＲＣ・・・入力抵抗、ＲＥ１
〜ＲＥｎ・・・利４ｇ選択用の帰還抵抗、ＲＦ 、 Ｒ
Ｇ 。
Ｒ１＋・・・抵抗。
特許出願人 沖電気工業株式会社
代理人弁理士 古 １） 精 孝
第１図
第２図
第３図
第 ４ 図
ＲＧ ＲＦ
第５図
Ｎ
（Ｂ） ０ＬＪＴ５□
第６図FIG. 1 is a circuit diagram showing an embodiment of the amplifier circuit of the present invention, FIG. 2 is a circuit diagram showing an example of a conventional amplifier circuit, FIG. 3 is an explanatory diagram of stray capacitance of the circuit in FIG. 4 is a waveform diagram of the operation of the circuit of FIG. 2, FIG. 5 is a circuit diagram for explaining the main part of FIG. 1, and FIG. 6 is a waveform diagram of the operation related to FIG. 4.5...Operation amplifier, RC...Input resistance, RE1
~REn... Feedback resistor for 4g selection, RF, R
G. R1+...resistance. Patent Applicant Oki Electric Industry Co., Ltd. Patent Attorney Furu 1) Takashi Sei Figure 1 Figure 2 Figure 3 Figure 4 Figure RG RF Figure 5 N (B) 0LJT5□ Figure 6
Claims (1)
入力信号を入力するとともに、該演算増幅器の出力信号
を所定の帰還抵抗を介して前記（−）入力端子に帰還し
、入力抵抗と帰還抵抗との比に基づく利得で入力信号を
増幅する増幅回路において、 前記入力信号と、前記演算増幅器の出力信号を前記利得
の逆数倍し且つ極性を反転した信号とを加算する手段を
設け、 前記加算手段の出力を演算増幅器の（＋）入力端子に接
続した ことを特徴とする増幅回路。[Claims] An input signal is input to the (-) input terminal of an operational amplifier via a predetermined input resistor, and an output signal of the operational amplifier is input to the (-) input terminal via a predetermined feedback resistor. In an amplifier circuit that feeds back and amplifies an input signal with a gain based on a ratio of an input resistance and a feedback resistance, the input signal and a signal obtained by multiplying the output signal of the operational amplifier by the reciprocal of the gain and inverting the polarity. An amplifier circuit comprising: means for adding , and an output of the adding means is connected to a (+) input terminal of an operational amplifier.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4377586A JPS62200904A (en) | 1986-02-28 | 1986-02-28 | Amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4377586A JPS62200904A (en) | 1986-02-28 | 1986-02-28 | Amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62200904A true JPS62200904A (en) | 1987-09-04 |
| JPH0543206B2 JPH0543206B2 (en) | 1993-07-01 |
Family
ID=12673127
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4377586A Granted JPS62200904A (en) | 1986-02-28 | 1986-02-28 | Amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62200904A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2369278A (en) * | 2000-12-27 | 2002-05-22 | Eugueni Sergeyevich Alechine | A method of signal transmission for low frequency sounds |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60127811A (en) * | 1983-12-15 | 1985-07-08 | Matsushita Graphic Commun Syst Inc | Variable gain control circuit |
-
1986
- 1986-02-28 JP JP4377586A patent/JPS62200904A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60127811A (en) * | 1983-12-15 | 1985-07-08 | Matsushita Graphic Commun Syst Inc | Variable gain control circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2369278A (en) * | 2000-12-27 | 2002-05-22 | Eugueni Sergeyevich Alechine | A method of signal transmission for low frequency sounds |
| GB2369278B (en) * | 2000-12-27 | 2003-02-19 | Eugenie Sergeyevich Aleshin | Method of sound channel upgrading |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0543206B2 (en) | 1993-07-01 |
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