JP2538708B2 - Variable gain amplifier - Google Patents

Variable gain amplifier

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Publication number
JP2538708B2
JP2538708B2 JP2227716A JP22771690A JP2538708B2 JP 2538708 B2 JP2538708 B2 JP 2538708B2 JP 2227716 A JP2227716 A JP 2227716A JP 22771690 A JP22771690 A JP 22771690A JP 2538708 B2 JP2538708 B2 JP 2538708B2
Authority
JP
Japan
Prior art keywords
circuit
output
differential circuit
voltage
differential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2227716A
Other languages
Japanese (ja)
Other versions
JPH04109705A (en
Inventor
敏雄 工藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NIPPON DENKI AISHII MAIKON SHISUTEMU KK
Original Assignee
NIPPON DENKI AISHII MAIKON SHISUTEMU KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NIPPON DENKI AISHII MAIKON SHISUTEMU KK filed Critical NIPPON DENKI AISHII MAIKON SHISUTEMU KK
Priority to JP2227716A priority Critical patent/JP2538708B2/en
Publication of JPH04109705A publication Critical patent/JPH04109705A/en
Application granted granted Critical
Publication of JP2538708B2 publication Critical patent/JP2538708B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は可変利得増幅器に関し、特に制御電圧に対し
て指数関数的に電圧利得が変化する可変利得増幅回路に
関する。
The present invention relates to a variable gain amplifier, and more particularly to a variable gain amplifier circuit whose voltage gain changes exponentially with respect to a control voltage.

〔従来の技術〕[Conventional technology]

従来の可変利得増幅回路の一例を第2図に、その具体
的回路例を第3図に示す。
An example of a conventional variable gain amplifier circuit is shown in FIG. 2, and a concrete circuit example thereof is shown in FIG.

第2図において、本回路は、電流出力型差動回路A1,A
2と、抵抗R1,R2と、入力端子dと、出力端子bと、定電
源電圧V1,V2と、制御電圧源Vcと、定電流源I0と、制御
回路10とを含み、構成される。第3図において、トラン
ジスタQ1〜Q15,抵抗R1,R2,定電流源I0,定電圧源V1,V2,
制御電圧源Vcが示されている。ここで、トランジスタQ1
〜Q5と定電流源I0,I3とは、第2図の電流出力型差動回
路A1構成し、トランジスタQ8〜Q25と定電流源I0とは、
第2図の電流出力型差動回路A2を構成する。また、トラ
ンジスタQ6,Q7,定電流源I0,定電圧源V2,制御電圧源Cc
て制御回路10を構成する。但し、トランジスタQ1は、ト
ランジスタQ4,Q8のペース電流による誤差を少なくする
為、バッファとして入れてある。
In FIG. 2, this circuit is a current output type differential circuit A 1 , A
2 , the resistors R 1 and R 2 , the input terminal d, the output terminal b, the constant power source voltages V 1 and V 2 , the control voltage source V c , the constant current source I 0, and the control circuit 10. Included and configured. In FIG. 3, transistors Q 1 to Q 15 , resistors R 1 and R 2 , constant current source I 0 , constant voltage sources V 1 and V 2 ,
The control voltage source V c is shown. Where transistor Q 1
~ Q 5 and the constant current sources I 0 , I 3 constitute the current output type differential circuit A 1 of Fig. 2, and the transistors Q 8 to Q 25 and the constant current source I 0 are
The current output type differential circuit A 2 shown in FIG. 2 is constructed. Further, the transistors Q 6 , Q 7 , the constant current source I 0 , the constant voltage source V 2 , and the control voltage source C c constitute the control circuit 10. However, the transistor Q 1 is included as a buffer in order to reduce an error due to the pace current of the transistors Q 4 and Q 8 .

次に、第2図により従来回路の動作を簡単に説明す
る。ここで、差動回路A1,A2の入力インピーダンスは充
分高いものとする。
Next, the operation of the conventional circuit will be briefly described with reference to FIG. Here, it is assumed that the input impedance of the differential circuits A 1 and A 2 is sufficiently high.

今、入力端子dに入力信号viが印加された時、出力端
子bでの出力端子voは次式で求められる。
Now, when the input signal v i is applied to the input terminal d, the output terminal v o at the output terminal b is obtained by the following equation.

まず、差動回路A1の入出力特性を求めると、次式とな
る。
First, when the input / output characteristics of the differential circuit A 1 are obtained, the following equation is obtained.

vC=vI+i・R1 …… i=−gm1・vc …… 前記,式より、次式が得られる。 v C = v I + i · R 1 ...... i = -g m1 · v c ...... it said, the equation, the following equation is obtained.

vc=vi/(1+gm1・R1) …… 次に、差動回路A2の出力電流ioは、次式となる。v c = v i / (1 + g m1 · R 1 ) ... Next, the output current i o of the differential circuit A 2 is given by the following equation.

io=gm2・vc ゆえに、vc=gm2・vc・Rd …… 以上前記,式より、従来回路の電圧利得は、次式
として得られる。
i o = g m2 · v c Therefore, v c = g m2 · v c · R d ...... From the above equation, the voltage gain of the conventional circuit is obtained as the following equation.

ここで、vi;d点での入力信号電圧,vC;c点での出力信
号電圧,vc;b点での出力信号電圧,i;差動回路A1の交流出
力電流,io;差動回路A2の交流出力電流,gm1;差動回路A1
の相互コンダクタンス,gm2;差動回路A2の相互コンダク
タンス。
Where v i ; input signal voltage at point d, v C ; output signal voltage at point c , v c ; output signal voltage at point b, i; AC output current of differential circuit A 1 , i o ; AC output current of differential circuit A 2 , g m1 ; Differential circuit A 1
Transconductance of, g m2 ; Transconductance of differential circuit A 2 .

ここで、電圧利得Avの制御を、差動回路A1,A2の相互
コンダクタンスgm1,gm2の制御で行う。
Here, the voltage gain A v is controlled by controlling the mutual conductances g m1 and g m2 of the differential circuits A 1 and A 2 .

次に、相互コンダクタンスgm1,gm2の制御について説
明する。
Next, control of the mutual conductances g m1 and g m2 will be described.

差動回路A1,A2の相互コンダクタンスgm1,gm2は、次式
により求まる。
The mutual conductances g m1 and g m2 of the differential circuits A 1 and A 2 are obtained by the following equation.

ここで、相互コンダクタンスgmの制御は、第1図の電
流I1,I2で行う。従って、次式が得られる。
Here, the mutual conductance g m is controlled by the currents I 1 and I 2 in FIG. Therefore, the following equation is obtained.

また、前記,式より、次式となる。 Further, from the above equation, the following equation is obtained.

前記,式より次式が得られる。 From the above equation, the following equation is obtained.

ここで、I1;トランジスタQ6のコレクタ電流,I2;トラ
ンジスタQ7のコレクタ電流,V2;定電圧源,Vc;制御電圧
源。
Here, I 1 ; collector current of transistor Q 6 , I 2 ; collector current of transistor Q 7 , V 2 ; constant voltage source, V c ; control voltage source.

ここで、gm1・R1≫1という条件を満たす時、前記
式及び前記式より、次式が得られる。
Here, when the condition of g m1 · R 1 >> 1 is satisfied, the following equation is obtained from the above equation and the above equation.

このように、従来の電圧制御型増幅器の場合、使用条
件が常にgm1・R1≫1の条件を満たす時のみ、制御電圧V
Cに対して電圧利得AVが指数関数的に制御出来る。
As described above, in the case of the conventional voltage-controlled amplifier, the control voltage V can be set only when the usage condition is always g m1 · R 1 >> 1.
The voltage gain A V exponentially control can be with respect to C.

〔発明が解決しようとする課題〕[Problems to be Solved by the Invention]

前述した従来の可変利得増幅器の場合、単純に増幅器
の電圧利得が相互コンダクタンスの比で決まらず、特に
電圧利得が大きくなった時、即ち〔gm1・R1〕の値が小
さくなり、〔gm1・R1+1≒gm1・R1〕という近似が出来
なくなった時、誤差成分が支配的となり、制御特性が、
設定した指数関数特性よりずれるという欠点がある。
For conventional variable gain amplifier as described above, simply the voltage gain of the amplifier is not determined by the ratio of the transconductance, especially when the voltage gain becomes larger, i.e., the value of [g m1 · R 1] becomes smaller, [g m1・ R 1 + 1 ≒ g m1・ R 1 ], the error component becomes dominant and the control characteristic becomes
There is a drawback that it deviates from the set exponential function characteristic.

本発明の目的は、前記欠点が解決され、制御特性が、
設定した指数関数特性に沿うようにした可変利得増幅器
を提供することにある。
The object of the present invention is to solve the above-mentioned drawbacks and to provide control characteristics
Another object of the present invention is to provide a variable gain amplifier adapted to meet a set exponential function characteristic.

〔課題を解決するための手段〕[Means for solving the problem]

本発明の構成は、第1,第2の抵抗と、電流出力型の第
1,第2の差動回路と、電圧出力型加算器と、利得制御手
段とを備え、前記第1の抵抗の一端を、前記第1の差動
回路の出力及び反転入力と、前記第2の差動回路の非反
転入力とに接続し、前記第1の差動回路の非反転入力と
前記第2の差動回路の反転入力とを定電位源に接続し、
前記第2の差動回路の出力に第2の抵抗を接続してなる
並列接続差動増幅器を設け、前記第1及び第2の差動回
路の相互コンダクタンスを相補的に制御するように前記
利得制御手段を設けた可変利得増幅回路において、第1
の入力を入力端子に接続し、かつ出力を前記第1の抵抗
の他端に接続し、かつ第2の入力を前記第1の差動回路
の出力に接続してなる2入力の電圧出力型加算器を設け
たことを特徴とする。
The configuration of the present invention includes the first and second resistors and the current output type first resistor.
1, a second differential circuit, a voltage output type adder, and gain control means, wherein one end of the first resistor is connected to the output and inverting input of the first differential circuit and the second differential circuit. Connected to the non-inverting input of the differential circuit, and connecting the non-inverting input of the first differential circuit and the inverting input of the second differential circuit to a constant potential source,
A parallel connection differential amplifier in which a second resistor is connected to the output of the second differential circuit is provided, and the gain is provided so as to complementarily control the transconductance of the first and second differential circuits. In the variable gain amplifier circuit provided with the control means, the first
Two-input voltage output type in which the input of is connected to the input terminal, the output is connected to the other end of the first resistor, and the second input is connected to the output of the first differential circuit. A feature is that an adder is provided.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be described with reference to the drawings.

第1図は本発明の一実施例の可変利得増幅器を示すブ
ロック図である。第1図において、本実施例の可変利得
増幅器は、電流出力型差動回路A1,A2と、電圧出力型加
算器A3と、抵抗R1,R2と、入力端子aと、出力端子b
と、制御回路10と、定電圧V1,V2と、可変の制御電圧源V
cとを備えている。
FIG. 1 is a block diagram showing a variable gain amplifier according to an embodiment of the present invention. In FIG. 1, the variable gain amplifier according to the present embodiment includes current output type differential circuits A 1 and A 2 , a voltage output type adder A 3 , resistors R 1 and R 2 , an input terminal a, and an output. Terminal b
, Control circuit 10, constant voltage V 1 , V 2 , and variable control voltage source V
It has c and.

第1図において、第2図と同一記号,同一番号の素子
は同一素子を示す。
In FIG. 1, elements having the same symbols and numbers as in FIG. 2 indicate the same elements.

本実施例において、第2図の従来回路と同様に差動回
路A1,A2,抵抗R1,R2等で構成されるが、入力回路に加算
器A3を付加している点が従来と異なる。この加算器A3
入力インピーダンスは充分高いものとする。また、相互
コンダクタンスの制御は、従来回路と同様に、制御回路
10、制御電圧源VC,定電圧源X2,定電流源I0にて行う。
In this embodiment, similar to the conventional circuit of FIG. 2 , it is composed of differential circuits A 1 and A 2 , resistors R 1 and R 2, etc., but the point that an adder A 3 is added to the input circuit Different from conventional. The input impedance of this adder A 3 is sufficiently high. In addition, the control of mutual conductance is similar to the conventional circuit.
10. Control voltage source V C , constant voltage source X 2 , constant current source I 0 .

次に第1図に示した本実施例の可変利得増幅器の動作
を説明する。但し、電圧利得の制御方法は、従来回路と
同様なので省略する。
Next, the operation of the variable gain amplifier of this embodiment shown in FIG. 1 will be described. However, the method of controlling the voltage gain is the same as that of the conventional circuit, and therefore will be omitted.

入力端子aに入力信号電圧viが印加された時、出力端
子bでの出力信号電圧voは次式により求められる。
When the input signal voltage v i is applied to the input terminal a, the output signal voltage v o at the output terminal b is obtained by the following equation.

まず、c点における電圧は次式により求まる。 First, the voltage at point c is obtained by the following equation.

vc=(vi+vc)+iR1 …… i=−gm1・vc …… 前記,式より、次式とたる。v c = (v i + v c ) + iR 1 ... i = -g m1 · v c ... From the above equation, the following equation is obtained.

vc=vi/gm1・Rz …… 次に差動回路A2の出力電流は、io=gm2vcであるの
で、次式となる。
v c = v i / g m1 · R z ...... Then, the output current of the differential circuit A 2 is i o = g m2v c , so the following equation is obtained.

v0=gm2vc・R2 …… 以上前記,式より、本実施例の電圧利得は、次式
となる。
v 0 = g m2 v c · R 2 ... From the above equation, the voltage gain of this embodiment is as follows.

ここで、従来回路と同様の制御方法より、前記式・
前記式より、次式が得られる。
Here, from the same control method as the conventional circuit,
From the above equation, the following equation is obtained.

このように、常に制御電圧に対して、電圧利得AVが指
数関数に変化する電圧制御型増幅器を得ることが出来
る。
In this way, it is possible to obtain a voltage-controlled amplifier in which the voltage gain A V changes exponentially with respect to the control voltage at all times.

本実施例では、第2の差動回路の出力を負荷抵抗に接
続して電圧をとりだし、第1および第2の差動回路A1,A
2の相互コンダクタンスを制御し,電圧利得を可変して
いる。
In the present embodiment, the output of the second differential circuit is connected to the load resistance to take out the voltage, and the first and second differential circuits A 1 , A
It controls the mutual conductance of 2 and changes the voltage gain.

〔発明の効果〕〔The invention's effect〕

以上説明したように、本発明は、入力回路に加算器を
有することにより、制御電圧に対する電圧利得変化が、
常に所要の指数関数で制御出来るという効果がある。
As described above, according to the present invention, by including the adder in the input circuit, the voltage gain change with respect to the control voltage is
It has the effect that it can always be controlled with the required exponential function.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の一実施例の可変利得増幅器のブロック
図、第2図は従来の可変利得増幅器のブロック図、第3
図は第2図の従来回路の具体的回路図である。 A1,A2……差動回路,A3……加算器,R1,R2……抵抗,a,d…
…入力端子,b……出力端子,Q1〜Q15……トランジスタ,I
0,I3……定電流回路,V1,V2……定電圧回路,VC……制御
電圧源。
FIG. 1 is a block diagram of a variable gain amplifier according to an embodiment of the present invention, FIG. 2 is a block diagram of a conventional variable gain amplifier, and FIG.
The figure is a specific circuit diagram of the conventional circuit of FIG. A 1 , A 2 ...... Differential circuit, A 3 ...... Adder, R 1 , R 2 ...... Resistance, a, d…
… Input terminal, b …… Output terminal, Q 1 to Q 15 … Transistor, I
0 , I 3 …… Constant current circuit, V 1 , V 2 …… Constant voltage circuit, V C …… Control voltage source.

Claims (1)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】第1,第2の抵抗と、電流出力型の第1,第2
の差動回路と、電圧出力型加算器と、利得制御手段とを
備え、前記第1の抵抗の一端を、前記第1の差動回路の
出力及び反転入力と、前記第2の差動回路の非反転入力
とに接続し、前記第1の差動回路の非反転入力と前記第
2の差動回路の反転入力とを定電位源に接続し、前記第
2の差動回路の出力に第2の抵抗を接続してなる並列接
続差動増幅器を設け、前記第1及び第2の差動回路の相
互コンダクタンスを相補的に制御するように前記利得制
御手段を設けた可変利得増幅回路において、第1の入力
を入力端子に接続し、かつ出力を前記第1の抵抗の他端
に接続し、かつ第2の入力を前記第1の差動回路の出力
に接続してなる2入力の電圧出力型加算器を設けたこと
を特徴とする可変利得増幅器。
1. A first and a second resistance, and a first and a second of a current output type.
Differential circuit, a voltage output type adder, and gain control means, and one end of the first resistor is connected to the output and inverting input of the first differential circuit and the second differential circuit. Of the first differential circuit and the inverting input of the second differential circuit are connected to a constant potential source, and are connected to the output of the second differential circuit. A variable gain amplifier circuit comprising a parallel-connected differential amplifier formed by connecting a second resistor, and the gain control means so as to complementarily control the mutual conductance of the first and second differential circuits. , A first input connected to the input terminal, an output connected to the other end of the first resistor, and a second input connected to the output of the first differential circuit. A variable gain amplifier comprising a voltage output type adder.
JP2227716A 1990-08-29 1990-08-29 Variable gain amplifier Expired - Fee Related JP2538708B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2227716A JP2538708B2 (en) 1990-08-29 1990-08-29 Variable gain amplifier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2227716A JP2538708B2 (en) 1990-08-29 1990-08-29 Variable gain amplifier

Publications (2)

Publication Number Publication Date
JPH04109705A JPH04109705A (en) 1992-04-10
JP2538708B2 true JP2538708B2 (en) 1996-10-02

Family

ID=16865235

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2227716A Expired - Fee Related JP2538708B2 (en) 1990-08-29 1990-08-29 Variable gain amplifier

Country Status (1)

Country Link
JP (1) JP2538708B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003179447A (en) 2001-12-10 2003-06-27 Nec Electronics Corp Variable-gain circuit

Also Published As

Publication number Publication date
JPH04109705A (en) 1992-04-10

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