JPH0233994B2 - - Google Patents
Info
- Publication number
- JPH0233994B2 JPH0233994B2 JP56154536A JP15453681A JPH0233994B2 JP H0233994 B2 JPH0233994 B2 JP H0233994B2 JP 56154536 A JP56154536 A JP 56154536A JP 15453681 A JP15453681 A JP 15453681A JP H0233994 B2 JPH0233994 B2 JP H0233994B2
- Authority
- JP
- Japan
- Prior art keywords
- board
- holes
- wiring board
- hole
- contact pin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000012360 testing method Methods 0.000 claims description 10
- 238000000034 method Methods 0.000 claims description 9
- 238000007689 inspection Methods 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000003822 epoxy resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 238000007772 electroless plating Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
- G01R31/2805—Bare printed circuit boards
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Measuring Leads Or Probes (AREA)
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Description
【発明の詳細な説明】 (産業上の利用分野) 本発明は、配線板の回路導通検査法に関する。[Detailed description of the invention] (Industrial application field) The present invention relates to a circuit continuity testing method for wiring boards.
(従来の技術)
配線板は、絶縁基板面に必要な回路を形成し、
スルーホールにより表裏面の回路を接続している
が、回路の断線、回路間のシヨートの有無を検査
する必要がある。(Prior art) Wiring boards form necessary circuits on an insulating substrate surface,
Although the circuits on the front and back sides are connected using through holes, it is necessary to inspect the circuits for breaks and shorts between the circuits.
従来このような配線板の導通検査法としては、
回路パターン毎に、回路パターンに対応した位置
に接点ピンを有するカセツト盤を作成して検査し
ていたが、多品種少量生産には不向きであつた。
最近では、パターン毎にカセツト盤を作成せずに
すむように、格子点に多数の接点ピンを有する万
能型導通検査機が使用されるようになつてきてい
る。第1図は、このような万能型導通検査機を示
すもので、1は格子点に多数の貫通孔を有する絶
縁板、2はその貫通孔に挿入された接点ピンであ
る。接点ピン2は、第2図に示すように、絶縁板
1に固定されたソケツト3内で、スプリング4に
より上下方向に可動できるように支持されてい
る。 The conventional continuity testing method for such wiring boards is as follows:
For each circuit pattern, a cassette board having contact pins at positions corresponding to the circuit pattern was created and inspected, but this was not suitable for high-mix, low-volume production.
Recently, universal continuity testing machines having a large number of contact pins at grid points have come into use so that it is not necessary to create a cassette board for each pattern. FIG. 1 shows such a universal continuity tester, in which 1 is an insulating plate having a large number of through holes at grid points, and 2 is a contact pin inserted into the through holes. As shown in FIG. 2, the contact pin 2 is supported within a socket 3 fixed to the insulating plate 1 by a spring 4 so as to be movable in the vertical direction.
このような万能型導通検査機を使用する場合で
も、配線板上の格子点からはずれているスルーホ
ールは検査できないことがあり、これを解決する
ために、第3図に示すように、万能型導通検査機
5と被検査配線板6の間に、万能型型導通検査機
5の接点ピン2とはずれたスルーホール7を接続
する修正ピン8を有する補助盤9を置き、接点ピ
ン2と接続できないパターンとの接続を修正して
いた。また、第4図に示すように、万能型導通検
査機5の接点ピン2とはずれたスルーホール7と
接続できる修正ピン11を有する補助盤12を被
検査配線板6の裏面に置き、接点ピン2とパター
ンとの接続を修正して検査を行つていた。 Even when using such a universal continuity tester, it may not be possible to inspect through-holes that are off the grid points on the wiring board. An auxiliary board 9 is placed between the continuity tester 5 and the wiring board 6 to be tested, and has a correction pin 8 that connects the contact pin 2 of the universal continuity tester 5 to the through hole 7 that has come off, and is connected to the contact pin 2. A connection with a pattern that was not possible was fixed. In addition, as shown in FIG. 4, an auxiliary board 12 having a correction pin 11 that can be connected to the contact pin 2 of the universal continuity tester 5 and the detached through hole 7 is placed on the back surface of the wiring board 6 to be tested, and the contact pin The connection between 2 and the pattern was corrected and then inspected.
(発明が解決しようとする課題)
このような、多数の格子点に接点を有する万能
型導通検査機のずれを補助板で修正する方法で
は、構造が複雑になり、作業性が悪いという問題
があつた。(Problems to be Solved by the Invention) This method of correcting the misalignment of a universal continuity tester having contacts at a large number of grid points using an auxiliary plate has the problem of a complicated structure and poor workability. It was hot.
(課題を解決するための手段)
本発明は、このような万能型導通検査機を用い
る検査法において、格子点でない箇所にスルーホ
ールを有する配線板とカセツト盤との間に、接点
ピンと接触しないスルーホールと接点ピンとを電
気的に接続する手段と格子点にあるスルーホール
の箇所に接点ピンを通すことのできる穴を有する
補助回路板を配することを特徴とする配線板の回
路導通検査法である。(Means for Solving the Problems) The present invention provides an inspection method using such a universal continuity tester, in which the contact pins do not come into contact between the wiring board and the cassette board, which have through holes at locations other than grid points. A method for testing circuit continuity of a wiring board, comprising: a means for electrically connecting a through hole and a contact pin; and an auxiliary circuit board having a hole through which a contact pin can pass through the through hole located at a grid point. It is.
すなわち、本発明は、従来の補助盤を使用する
ことに代えて、被検査配線板の格子点からはずれ
た回路(スルーホール)が、万能型導通検査機の
接点ピンと電気的に接続できるようにするため
に、格子点に引き出しパツドを設けた薄い配線板
からなる補助回路板を、接点ピンと被検査配線板
との間に挿入する方法である。この薄い配線板か
らなる補助回路板は、被検査配線板6を作成する
ときに使用するフオトマスクを利用し、格子点か
らはずれているスルーホールのみを選び、そのス
ルーホールと格子点上に設けたパツドとをパター
ンで接続した配線板とする。また、被検査配線板
でスルーホールが格子点にあるものは、接点ピン
と直接接触できるように、補助回路板の相当する
位置に接点ピンの直径より大きい穴をあけてお
く。 That is, instead of using the conventional auxiliary board, the present invention enables circuits (through holes) that are off the grid points of the wiring board to be electrically connected to the contact pins of the universal continuity tester. In order to do this, an auxiliary circuit board made of a thin wiring board with pull-out pads provided at grid points is inserted between the contact pins and the wiring board to be inspected. The auxiliary circuit board made of this thin wiring board was made by using the photomask used when creating the wiring board 6 to be inspected, selecting only the through holes that were off the grid points, and placing them on the through holes and the grid points. This is a wiring board in which the pads are connected in a pattern. In addition, if the wiring board to be inspected has through holes at grid points, holes larger than the diameter of the contact pins should be drilled at the corresponding positions on the auxiliary circuit board so that the through holes can come into direct contact with the contact pins.
第5図および第6図に基づいて、本発明の検査
法を更に説明する。 The inspection method of the present invention will be further explained based on FIGS. 5 and 6.
第5図において、13は格子点に多数の接点ピ
ン2を有するカセツト盤で、14は接点ピン2と
接触しない被検査回路と接点ピン2とを電気的に
接続する回路パターン15を有する補助回路板、
16は接点ピン2の直径よりも大きい穴、6は被
検査配線板である。 In FIG. 5, 13 is a cassette board having a large number of contact pins 2 at lattice points, and 14 is an auxiliary circuit having a circuit pattern 15 for electrically connecting the contact pins 2 to the circuit under test that does not come into contact with the contact pins 2. board,
16 is a hole larger than the diameter of the contact pin 2, and 6 is a wiring board to be inspected.
第6図は、カセツト盤13、補助回路板14、
被検査配線板6を重ね合わせた状態を示す断面図
であり、被検査配線板6の格子点にあるスルーホ
ールは補助回路板14にあけられた穴16によつ
て直接接点ピン2と電気的に接続され、また、格
子点からはずれたスルーホール18と接点ピン2
は補助回路板14の前記スルーホール18に相当
する位置にスルーホールを設け、格子点には引き
出しパツド19を設け、両者を回路パターン15
で接続することにより電気的に接続される。この
ようにして、格子点にあるスルーホールも格子点
からはずれたスルーホールも万能型導通検査機5
の接点ピン2と電気的に接続されるので、被検査
配線板6の回路は全て導通検査を行うことができ
る。 FIG. 6 shows the cassette board 13, the auxiliary circuit board 14,
It is a sectional view showing a state in which the wiring boards 6 to be inspected are stacked, and the through holes at the lattice points of the wiring board 6 to be inspected are directly electrically connected to the contact pins 2 by holes 16 made in the auxiliary circuit board 14. The through hole 18 and the contact pin 2 which are connected to the lattice point
A through hole is provided at a position corresponding to the through hole 18 of the auxiliary circuit board 14, a pullout pad 19 is provided at the grid point, and both are connected to the circuit pattern 15.
It is electrically connected by connecting with . In this way, through-holes located at lattice points and through-holes deviated from lattice points can be inspected with the all-purpose continuity tester 5.
Since it is electrically connected to the contact pin 2 of the wiring board 6, all the circuits of the wiring board 6 to be tested can be tested for continuity.
なお、補助回路板14の薄い配線板の材料とし
ては、ポリイミドフイルムと銅箔を粘りあわせた
フレキシブル配線板用基板や薄いエポキシ樹脂銅
張積層板が利用できる。 Note that as the material for the thin wiring board of the auxiliary circuit board 14, a flexible wiring board substrate made of adhesively bonded polyimide film and copper foil or a thin epoxy resin copper-clad laminate can be used.
実施例
接着剤を塗布した基板上に、絶縁電線を固定し
た100ミル(約2.54mm)格子点と75ミル(約1.8
mm)格子点にスルーホールを有するマルチワイヤ
配線板を、以下の手順で作成した補助回路板を用
いて、100ミル格子点に接点ピンを有する万能型
導通検査機を用いて回路導通検査を行つた。Example 100 mil (approx. 2.54 mm) lattice points and 75 mil (approx. 1.8
mm) Perform a circuit continuity test on a multi-wire wiring board with through holes at grid points using an auxiliary circuit board created using the following procedure using a universal continuity tester with contact pins at 100 mil grid points. Ivy.
〔補助回路板の作成〕
被検査配線板の内層に用いられスルーホール
の貫通する箇所の銅箔のみを除去した電源層又
はグランド層用のフオトマスクに、100ミル格
子点に全てマークのあるフイルムを重ね、その
格子点からはずれた75ミル格子点にあるスルー
ホールを選出する。[Creation of auxiliary circuit board] Place a film with marks at all 100 mil grid points on a photomask for the power supply layer or ground layer, which is used as the inner layer of the wiring board to be inspected and only removes the copper foil in the areas where the through holes penetrate. Then select a through hole located at a 75 mil lattice point that is off from that lattice point.
75ミル格子点にあるスルーホールと、100ミ
ル格子点とを結ぶパターンを設けた新たなフオ
トマスクを作成する。 Create a new photomask with a pattern connecting the through holes at the 75 mil grid points and the 100 mil grid points.
75ミル格子点にあるスルーホールを設けるた
めの穴あけ機用データテープと、スルーホール
として使用する100ミル格子点に接点ピンの通
る穴を設けるための穴あけ機用データテープを
作製する。 Create a data tape for a hole puncher to create through holes at 75 mil grid points, and a data tape for a hole punch to create holes for contact pins to pass through at 100 mil grid points to be used as through holes.
基材として厚さ0.23mmのガラス布−エポキシ
樹脂銅張積層板MCL−E−608(日立化成工業
株式会社製商品名)を準備する。 A glass cloth-epoxy resin copper-clad laminate MCL-E-608 (trade name, manufactured by Hitachi Chemical Co., Ltd.) with a thickness of 0.23 mm is prepared as a base material.
75ミル格子点にあるスルーホールの穴あけを
行う。 Drill through holes at 75 mil grid points.
スルーホール内を無電解めつきによつて金属
化する。 The inside of the through hole is metallized by electroless plating.
75ミル格子点にあるスルーホールと、100ミ
ル格子点とを結ぶパターンを設けた新たなフオ
トマスクを、エツチングレジストを形成するた
めの光硬化型レジストフイルムをラミネートし
た基材の表面に重ね、紫外線を露光する。 A new photomask with a pattern connecting through holes at 75 mil lattice points and 100 mil lattice points was placed on the surface of a base material laminated with a photocurable resist film to form an etching resist, and ultraviolet rays were applied. Expose.
紫外線が露光されなかつた部分を溶解除去す
るために、現像する。 It is developed to dissolve and remove the portions that were not exposed to ultraviolet light.
形成されたエツチングレジストから露出した
銅箔をエツチング除去する。 The copper foil exposed from the formed etching resist is removed by etching.
75ミル格子点にあるスルーホールに接続され
る100ミル格子点にあるスルーホール以外の100
ミル格子点に直径2.3mmの穴をあける。 100 non-through holes at 100 mil grid points connected to through holes at 75 mil grid points
Drill a hole with a diameter of 2.3 mm at the mill grid point.
必要な部分以外を切断し、外形加工する。 Cut out the parts other than the necessary parts and process the external shape.
このようにして、導通検査を行つた結果、1回
の操作で正確な検査結果が得られた。 As a result of conducting the continuity test in this manner, accurate test results were obtained with a single operation.
(発明の効果)
以上に説明したように、本発明のによつて、次
の効果を有する検査法を提供することができた。(Effects of the Invention) As explained above, according to the present invention, it was possible to provide an inspection method having the following effects.
(1) 配線板の格子からはずれたスルーホールであ
つても、従来の複雑な構造を有する高価な補助
盤を使用せずに、安価な配線板を補助回路板と
して使用することができ、経済的となつた。(1) Even if the through-hole is outside the grid of the wiring board, an inexpensive wiring board can be used as an auxiliary circuit board without using an expensive auxiliary board with a conventional complicated structure, making it economical. It hit the mark.
(2) 従来の補助盤を利用する検査機より構造が簡
単になつた。(2) The structure is simpler than the conventional inspection machine that uses an auxiliary panel.
(3) 薄い配線板からなる補助回路板の交換が簡単
であり、従来の補助盤より作業性に優れてい
る。(3) The auxiliary circuit board, which is made of a thin wiring board, is easy to replace and is easier to work with than conventional auxiliary boards.
第1図は格子点に多数の接点ピンを有する万能
型導通検査機の斜視図、第2図は接点ピンの構造
を示す断面図、第3図および第4図は従来の検査
法を説明するための斜視図、第5図は本発明の検
査法を示す斜視図、第6図は本発明の検査状態を
示す要部拡大断面図である。
符号の説明、1……絶縁板、2……接点ピン、
5……万能型導通検査機、6……被検査配線板、
13……カセツト盤、14……補助回路板。
Fig. 1 is a perspective view of a universal continuity tester having a large number of contact pins at grid points, Fig. 2 is a sectional view showing the structure of the contact pins, and Figs. 3 and 4 explain the conventional testing method. FIG. 5 is a perspective view showing the inspection method of the present invention, and FIG. 6 is an enlarged sectional view of the main part showing the inspection state of the present invention. Explanation of symbols, 1...Insulating plate, 2...Contact pin,
5... Universal continuity tester, 6... Wiring board to be inspected,
13...Cassette board, 14...Auxiliary circuit board.
Claims (1)
セツト盤を重ね各接点ピン間の導通の有無を検査
する方法において、格子点でない箇所にスルーホ
ールを有する配線板とカセツト盤との間に、接点
ピンと接触しないスルーホールと接点ピンとを電
気的に接続する手段と格子点にあるスルーホール
の箇所に接点ピンを通すことのできる穴を設けた
補助回路板を配することを特徴とする配線板の回
路導通検査法。1. In a method of stacking a cassette board having a large number of contact pins at lattice points on a wiring board and inspecting the presence or absence of continuity between each contact pin, between the cassette board and the wiring board having through holes at locations other than lattice points, A wiring board characterized by disposing an auxiliary circuit board having a means for electrically connecting a through hole that does not come into contact with the contact pin and the contact pin, and a hole through which the contact pin can pass through the through hole located at the grid point. circuit continuity testing method.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56154536A JPS5855766A (en) | 1981-09-28 | 1981-09-28 | Testing method for circuit continuity of printed circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56154536A JPS5855766A (en) | 1981-09-28 | 1981-09-28 | Testing method for circuit continuity of printed circuit board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5855766A JPS5855766A (en) | 1983-04-02 |
JPH0233994B2 true JPH0233994B2 (en) | 1990-07-31 |
Family
ID=15586396
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56154536A Granted JPS5855766A (en) | 1981-09-28 | 1981-09-28 | Testing method for circuit continuity of printed circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5855766A (en) |
-
1981
- 1981-09-28 JP JP56154536A patent/JPS5855766A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS5855766A (en) | 1983-04-02 |
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