JPH0233283A - High efficiency coding device - Google Patents

Abstract

PURPOSE:To attain buffering processing of a transmission data white suppressing the deterioration in decoded picture quality by not only varying a threshold value in the level direction but also varying a threshold value for the frame omission processing in the timewise direction. CONSTITUTION:A detection circuit 3 obtains a maximum value, a minimum value of plural picture element data included in a block comprising areas belonging to plural frames of a digital picture signal and its dynamic range. Moreover, the detection circuit 3 detects the movement quantity for each block. A three- dimension frequency distribution generating circuit 5 sums the frequency occurrence for each block for a prescribed period and an integration type frequency distribution generating circuit 6 obtains an integration type frequency distribution. A movement discrimination circuit 10 and an averaging circuit 12 apply frame omission processing as to blocks whose movement is less than a prescribed quantity, and a three-dimension ADRC encoder 11 and a two-dimension ADRC encoder 13 apply compression coding to plural picture element data in a block in response to the dynamic range of the block.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a high-efficiency encoding device applied to an image signal,
In particular, the present invention relates to a high-efficiency encoding device that is applied to control the transmission rate of recorded data to a predetermined value corresponding to a transmission path when recording a digital video signal on a magnetic tape.

[Summary of the invention]

In this invention, when performing variable-length encoding in which the number of encoded bits is variable according to the dynamic range, a high-efficiency encoding device that controls the amount of generated information so that it does not exceed the transmission capacity of the transmission path, reduces the amount of motion. The introduced frequency distribution is formed,
Not only the threshold value in the level direction that determines the number of encoded bits, but also the motion threshold value for frame dropping processing is changed to control the amount of generated information, without increasing quantization error. The amount of generated information is well controlled.

[Conventional technology]

The applicant of this application calculates the dynamic range, which is the difference between the maximum and minimum values of multiple pixels included in a two-dimensional block, as described in Japanese Patent Application No. 59-266407, and calculates the dynamic range based on this dynamic range. A high-efficiency encoding device that performs adaptive encoding is proposed. Also, a special request in 1986
As described in Japanese Patent No. 232,789, a high-efficiency encoding device has been proposed that performs encoding adapted to the dynamic range of a three-dimensional block formed from pixels in areas included in each of a plurality of frames. Furthermore, as described in Japanese Patent Application No. 60-268817, there is a variable length encoding method in which the number of bits changes depending on the dynamic range so that the maximum distortion caused when quantization is constant. is proposed.

High-efficiency encoding (A
DRC) is suitable for application to digital VTRs because it can significantly compress the amount of data to be transmitted.

In particular, variable length ADRC can increase the compression rate. However, with variable length ADRC, the amount of data to be transmitted varies depending on the image content, so when using a fixed rate transmission path such as a digital VTR that records a predetermined amount of data as one track, buffering processing is required. is necessary.

As a buffering method for variable length ADRC, the applicant of the present application forms an integrated type dynamic range frequency distribution as described in Japanese Patent Application No. 61-257586, and for this frequency distribution, It has been proposed that a set of threshold values prepared in advance is applied, the amount of generated data is determined for a predetermined period, for example, one frame period, and the amount of generated data is controlled so as not to exceed a target value.

FIG. 11 shows an integrated type frequency distribution graph shown in the above-mentioned application, and the horizontal axis of FIG. 11 is the dynamic range DR.
, and the vertical axis is the frequency of occurrence in blocks. T1 to T4 written on the horizontal axis are threshold values. This threshold I
The number of quantization bits is determined by TI to T4. That is, in the case of a dynamic range DR in the range of (maximum value to Tl), the number of quantization bits is set to 4 bits, and (Tl-
1 to T2), the number of quantization bits is set to 3 bits, and in the range of (T2-1 to T3), the number of quantization bits is set to 2 bits, and (T3-1 to T3), the number of quantization bits is set to 3 bits. T4), the number of quantization bits is set to 1 bit, and (7
4-1 to the minimum value), the number of quantization bits is set to 0 bits (no code signal is transmitted).

In the cumulative type frequency distribution, when calculating the frequency distribution of the dynamic range DR within one frame period, the threshold value (Tl ~ 1 ) to the threshold value Tl.
The frequencies of occurrence up to 3 are also accumulated in the same way. Hereafter, the same process is repeated. Therefore, the frequency of occurrence of the minimum value of dynamic range DR is the total number of blocks included in one frame (
MXN).

In this way, when a cumulative frequency distribution is formed, the cumulative frequency up to the threshold Tl becomes Xl, the cumulative frequency up to the threshold Tl becomes (x++x2), and the cumulative frequency up to the threshold T3 becomes (XI 10Xt +Xs), and the threshold value T4
The cumulative frequency up to (X, +Xt + x 3 + x
a ), therefore, the amount of information generated in l frame period (
The total number of bits) is expressed by the following formula.

4 (x+ O)+3 ((XI +X!)
XI )+2 ((x+ +xt +X3) (
x+ +Xz ))+1 ((x+ +x, +X, +X
4)-(x+ +xz +Xs) ) -41+
+3 X+2xs+4 Threshold values T1 to T4 are set so that the amount of generated information described above does not exceed the target value. When changing the threshold value to find an optimal threshold value, the values of x1 to x4 described above are changed according to the threshold value, and the amount of generated information is calculated for each set of threshold values.

Therefore, if you create a cumulative frequency distribution table,
The amount of generated information can be calculated quickly.

[Problem to be solved by the invention]

As mentioned above, the method of converging the transmission data rate to a target value by changing, for example, four thresholds in the level direction, is insufficient in terms of performance in terms of reducing distortions such as quantization noise. there were.

Therefore, an object of the present invention is to not only change the threshold value in the level direction, but also change the threshold value for frame drop processing in the time direction, and to buffer transmission data while suppressing deterioration of restored image quality. The object of the present invention is to provide a highly efficient encoding device that can achieve the following.

[Means to solve the problem]

This invention includes a circuit 3 that calculates the maximum value MAX3, minimum value MIN3, and dynamic range DR3 of a plurality of pixel data contained in a block consisting of areas belonging to a plurality of frames of a digital image signal, and a circuit 3 that detects the amount of motion for each block. a circuit 5 which inputs the frequency of each block into the memory using the dynamic range DR3 and motion amount of each block as an address, and calculates the frequency distribution by summing the frequencies over a predetermined period; and the address of the dynamic range DR3 from the frequency distribution. A circuit 6 that calculates an integrated frequency distribution by sequentially accumulating frequencies in the address direction of direction and motion amount, and a circuit that performs frame drop processing by averaging corresponding pixel data between multiple fields for blocks whose motion amount is less than a predetermined amount. 10, 12, and a circuit 11 for compressing and encoding a plurality of pixel data in a block according to the dynamic range DR3 of the block.
13, and a circuit 6.7 for setting a predetermined amount of motion and the number of encoding bits according to the cumulative frequency distribution and the transmission capacity of the transmission path.

Effect C] In this invention, when high-efficiency encoding is performed, one image is divided into many three-dimensional blocks in a high-efficiency encoding device that controls the amount of generated information so that it does not exceed the transmission capacity of the transmission path. The maximum pixel data contained in each block (
IEMAX3, minimum value MIN3, and dynamic range DR3 are determined, and the amount of motion (for example, maximum frame difference ΔF) is detected from pixel data that are temporally different and included in the same block. In a stationary block with a small amount of movement, the amount of generated information is reduced by frame drop processing.

When determining the amount of generated information, a frequency distribution table with the dynamic range DR3 and the amount of movement as axes is formed. This frequency distribution table is formed by writing the frequency for each block into a memory using the dynamic range DR3 and the amount of motion as addresses, respectively, and summing up the frequencies over a predetermined period, for example, two frame periods. This frequency distribution table is converted into an integrated frequency distribution table by being aggregated in the direction of the dynamic range DR3 and the direction of the amount of motion.

Using the cumulative frequency distribution table, threshold values T1 to T4 in the level direction and motion threshold MTH are determined so that the amount of generated information does not exceed the target value. This motion threshold MTH
Frame drop processing is performed depending on the magnitude of the amount of movement of the block relative to the block. In addition, threshold values T1 to T in the level direction
4 controls the number of encoding bits in variable length high efficiency encoding, for example ADRC. And variable length AD
Encoded data obtained by RC is recorded on a magnetic tape.

In this invention, since the motion threshold value MTH, which is the standard for determining whether or not to perform frame drop processing, is also changed, it is possible to perform good buffering, which could not be achieved by changing the threshold value in the level direction alone. I can do it.

〔Example〕

Hereinafter, one embodiment of the present invention will be described in the following order with reference to the drawings.

a, Configuration of recording side, ADRC encoder c, Formation of three-dimensional frequency distribution table d, Example of three-dimensional frequency distribution generation circuit, integration type frequency distribution generation circuit and threshold value determination circuit a, Configuration of recording side 1st The figure shows the configuration of the recording side of an embodiment of the present invention,
In FIG. 1, a digital video signal in which one sample is quantized to 8 bits, for example, is supplied to an input terminal indicated by 1. This digital video signal is supplied to the blocking circuit 2. The blocking circuit 2 converts television scanning order data into block order data.

In the blocking circuit 2, for example, (520 lines x 720 lines
As shown in Figure 2, one frame screen of (M pixels)
XN) is subdivided into blocks. One block consists of two areas each having a size of (4 lines x 4 pixels), as shown in FIG. 3, for example. Each region belongs to two temporally consecutive frames. Further, as shown in FIG. 4, the sampling pattern has an offset between blocks due to subsampling. In FIG. 4, O indicates a pixel that is transmitted, Δ indicates a pixel that is not transmitted, and in a spatially corresponding block two frames later, the transmitted and thinned out pixels have an inverse relationship. Such a sampling pattern enables good interpolation in a still area when interpolating thinned out pixels on the receiving side. From blocking circuit 2, BII+ BIz+
BI31...A digital video signal converted into the BMN block order is generated.

The output signal of the blocking circuit 2 is supplied to a detection circuit 3 and a delay circuit 4. The detection circuit 3 detects the maximum value M of each block.
AX3 and the minimum value MIN3 are detected, and the maximum frame difference ΔF of the block is detected. As described above, in this example, since the block consists of two regions each belonging to two frames, the maximum frame difference ΔF between these two regions is detected. Between the two areas that make up one block,
The difference between the data of pixels at the same position is determined, the difference between each pixel is converted into an absolute value, and the maximum value of the differences converted into absolute values is set as the maximum frame difference ΔF.

Maximum value MAX3 from detection circuit 3. Minimum value MIN3. The maximum frame difference ΔF is supplied to the three-dimensional frequency distribution generation circuit 5. This three-dimensional frequency distribution generating circuit 5 has a dynamic range DR3 (-MAX3-MIN3) as described later.
+1) is taken as the vertical axis, and the maximum frame difference ΔF is taken as the horizontal axis, and the frequency of block occurrence is totaled in a two-frame period. The frequency distribution table formed in this way is used in the cumulative frequency distribution generation circuit 6.
is supplied to form an integrated frequency distribution table.

Direction of maximum frame difference ΔF and dynamic range DR3
By the process of integrating the degrees with respect to both the direction of
A cumulative frequency distribution table is obtained.

Using the cumulative frequency distribution table, the threshold determining circuit 7 determines optimal thresholds (level thresholds T1 to T4 and motion threshold MTH).

The optimal threshold value means a threshold value that allows encoding to be performed so that the total number of bits per two frames does not exceed the transmission capacity of the transmission path. This optimal threshold value is determined using the motion threshold value MTH as a parameter. A ROM 8 is provided in association with the threshold value determining circuit 7. This ROMB stores a program for finding an optimal threshold value.

The pixel data PD passed through the delay circuit 4 is supplied to a frame difference detection circuit 9. This frame difference detection circuit 9 is
The maximum frame difference ΔF is detected in the same manner as the detection circuit 3 described above. The maximum frame difference ΔF and pixel data PD from the frame difference detection circuit 9 are supplied to the motion determination circuit 10. The motion determination circuit 10 compares the motion threshold MTH from the threshold determination circuit 7 with the maximum frame difference ΔF, and determines whether the block to be processed is a motion block or a still block.

A block having the relationship (maximum frame difference ΔF>motion threshold MTH) is determined to be a moving block, and a block having the relationship (maximum frame difference ΔF≦motion threshold MTH) is determined to be a stationary block.

The pixel data of the motion block is supplied to a three-dimensional ADRC encoder 11. Furthermore, the pixel data of the still block is supplied to the averaging circuit 12.

This averaging circuit 12 adds the data of pixels at the same position in two areas included in one block, and then converts the data to % to form a block with a number of pixels equal to 2 of the original number of pixels in one block. Such processing is referred to as evacuation processing. The output signal of the averaging circuit 12 is supplied to a two-dimensional ADRC encoder 13. These encoders 11 and 13
, the threshold (!: T1 to T4
is supplied.

The three-dimensional ADRC encoder 11 selects the maximum value MAX3. out of a total of 32 pixel data (4 lines x 4 pixels x 2 frames). The minimum value MIN3 is detected and (MAX3-M
Dynamic range DR3 due to IN3+1-DR3)
is required. Dynamic range DR of this block
3 and the threshold values T1 to T4, the code signal DT
The number of bits of 3 is determined. That is, in the block where (DR3≧Tl), a 4-bit code signal is formed, and (TI>
In the block where DR3≧T2), a 3-bit code signal is formed, and in the block where (T2>DR3≧T3), a 3-bit code signal is formed.
A 2-bit code signal is formed, and (T3>DR3≧7
In the block 4), a 1-bit code signal is formed, and in the block (T4>DR3), O bits, that is,
No code signal is transmitted.

For example, in the case of 4-pit quantization encoding, the detected dynamic range DR3 is divided into 16 (=24),
A 4-bit code signal DT3 is generated corresponding to the range to which the level of the data after removing the minimum value MIN3 of each pixel data belongs.

In the two-dimensional ADRC encoder 13, the above-mentioned three-dimensional AD
By the same operation as the RC encoder 11, the maximum value MAX
2. Minimum value MIN2. Dynamic range DR2 is detected and code signal DT2 is formed. However, what is to be encoded is data whose number of pixels has been set to η by the averaging circuit 12 at the previous stage.

The output signal of the three-dimensional ADRC encoder 11 (DR3, M
IN3. DT3) and the output signal (DR2, MIN2.DT2) of the two-dimensional ADRC encoder 13 are supplied to the selector 14. The selector 14 is controlled by a determination signal SJ from the motion determination circuit 10. That is, in the case of a motion block, the selector 14 selects the output signal of the three-dimensional ADRC encoder 11, and in the case of a still block, the selector 14 selects the output signal of the two-dimensional ADRC encoder 13. The output signal of this selector 14 is supplied to a framing circuit 15.

In addition to the output signal of the selector 14, the framing circuit 15 is supplied with a threshold code Pi specifying a threshold set and a determination code SJ. The threshold code Pi is 2
It changes on a frame-by-frame basis, and the judgment code SJ is 1.
Changes in block units. The framing circuit 15 converts the human input signal into recorded data having a frame structure. The framing circuit 15 performs error correction code encoding processing as necessary. Output terminal 1 of framing circuit 15
The recorded data obtained in step 6 is supplied to a rotary head via a recording amplifier, a rotary transformer, etc. (not shown), and is recorded on a magnetic tape.

b. ADRC Encoder FIG. 5 shows the configuration of an example of the three-dimensional ADRC encoder 11. In FIG. A minimum value detection circuit 23 and a delay circuit 24 are connected. The maximum value MAX3 detected by the maximum value detection circuit 22 is detected by the subtraction circuit 2.
5. The minimum value MIN3 detected by the minimum value detection circuit 23 is supplied to a subtraction circuit 25, and the output signal of this subtraction circuit 25 is supplied to a +1 addition circuit 27. +
A dynamic range DR3 expressed as (MAX3-MINa+1) is obtained from the 1 addition circuit 27.

Pixel data passed through the delay circuit 24 is supplied to a subtraction circuit 26. The subtraction circuit 26 is supplied with the minimum value MIN3, and the pixel data P after the minimum value is removed from the subtraction circuit 26.
DI occurs. This pixel data PDI is transferred to the quantization circuit 3.
0. The dynamic range DR3 is taken out to the output terminal 31 and also supplied to the ROM 28. The ROM 28 is supplied with a threshold code Pi generated by the threshold determining circuit 7 from a terminal 29.

This ROM 28 generates a bit number code Nb indicating the quantization step Δ and the number of bits.

The quantization step Δ is supplied to the quantization circuit 30, and a code signal DT3 is formed from the minimum value removed data PDI and the quantization step Δ. This code signal DT3 is taken out to the output terminal 34.

Output signals generated at these output terminals 31, 32, 33, and 34 are supplied to a framing circuit 15.

The bit number code Nb is determined by the framing circuit 15.
Used to select valid bits.

The formation of the code signal DT3 in the above-mentioned quantization circuit 30 will be explained. Generally, in the case of encoding in which n bits are allocated, the level of the original data PD is expressed as Li, and the quantization code is expressed as Qi. The symbol [ ] means truncation.

Also, on the decoding side, if the restoration level is expressed as Li, i,
i = (DR3/2”) X (Qi +0.5
)+MIN3=ΔX (Qi +0.5) +M
I N 3 processing is performed.

c. Creation of a three-dimensional frequency distribution table The creation of a three-dimensional frequency distribution table performed by the three-dimensional frequency distribution generation circuit 5 will be explained with reference to FIG. In FIG. 6, the vertical axis shows the dynamic range DR3, and the horizontal axis shows the maximum frame difference ΔF. These dynamic range DR3 and the maximum frame difference ΔF are those detected by the detection circuit 3. Maximum frame difference ΔF
can take values in the range (0-255). To simplify the process, all maximum frame differences greater than or equal to a predetermined value may be replaced with a predetermined value.

At the position defined by the dynamic range DR3 of each block detected by the detection circuit 3 and the maximum frame difference ΔF,
The frequency of occurrence is written, and the frequency is totaled for two frame periods. As discussed below, the frequency table is formed in memory. In FIG. 6, the frequencies of occurrence in areas that are not shown are all set to 0 for simplicity.

In the cumulative type frequency distribution generation circuit 6, the frequency distribution table compiled over two frame periods is converted into a cumulative type. Integration is performed in both directions of maximum frame difference ΔF and dynamic range DR3. The table shown in FIG. 7A is obtained by integrating the maximum frame difference ΔF in the direction from 255 to O with respect to the table shown in FIG. Next, the table shown in FIG. 7A is integrated in the direction from 255 to O in the dynamic range DR3, thereby obtaining the table shown in FIG. 7B. The table shown in FIG. 7B is a cumulative type frequency distribution table. The frequency (47 in FIG. 7B) when (ΔF-0.DR3=0) is the total number of blocks in a two-frame period. The purpose of converting the frequency distribution table to the cumulative type is to facilitate the immediate determination of the amount of generated information.

The threshold determination circuit 7 determines an optimal threshold set and motion threshold MTH using a cumulative frequency distribution table. The method for determining this is to set an initial value for the motion threshold MTH that does not cause jerkiness in the restored image, and then move the threshold in the level direction to bring the generated information amount (total number of bits) to the target value. Determine a threshold set that does not exceed . If the target value cannot be reached, the motion threshold MTH is moved and a threshold set that does not exceed the target value is searched again. Processing for determining this threshold set is performed according to a program stored in the ROM 8.

With reference to FIG. 8A, a process for calculating the amount of generated information using the frequency distribution table shown in FIG. 6 will be described.

When the motion threshold MTH is given, (ΔF≦MT)
The range of I) is treated as a stationary block, and (ΔF>MT
The range of H) is treated as a motion block.

For a still block, an encoded code signal DT2 of 16 pixels is generated, and for a motion block, an encoded code signal DT3 of 32 pixels is generated.

When threshold values T1 to T4 in the level direction are given, the number of encoding bits is allocated as follows.

When (T4>DR3), 0 bit (T3>DR3≧T4), 1 bit (T2>DR3)
≧73), 2 bits (Tl>DR3≧T2),
When 3 bits (DR3≧Tl), 4 bit motion threshold MTH and level direction thresholds T1 to T4
Accordingly, the frequency distribution table is divided into 10 regions as shown in FIG. 8A. The total number of frequencies included in each area is M
When expressed as OO to M41, the data amount DA■ (number of bits) for two frame periods regarding the code signal is calculated by the following equation.

DAv=IX16XM10+IX32XM112X16
XM20+2X32XM21 3X16XM30+3X32XM31 4X16XM40+4X32XM41 =16 (M10+ 2 M11+ 2 M20+ 4
M21+ 3 M30+ 6 M31+ 4 M40
+ 8 M41)=16 ((M10+M11+M20
+M21+M30+M31+M40+M41) + (M11+M21+M31+M41)+ (M20
+M21+M30+M31+M40+M41)+ (M
21+M31+M41) + (M30+M31+M40+M41)+ (M31
+M41) + (M40+M41) + (M41)) The amount of information generated in a two-frame period is calculated by adding the fixed data amount DAf (number of bits) to the variable data amount DAv according to the dynamic range in the above formula. This is what I did. The fixed data amount DAf is the number of bits obtained by multiplying 17 bits, which is the sum of DR3 and MIN3 and the determination code SJ, by the total number of blocks.

As can be seen from the above formula, the frequencies of multiple regions M00~M
The data amount DAV is calculated by selectively integrating 4L. The integrated value of the frequencies enclosed in parentheses in the above equation can be immediately obtained from the integrated frequency distribution table shown in FIG. 7B obtained by the integrated frequency distribution generating circuit 6.

Figure 8B shows the above equation () in the cumulative frequency distribution table.
These integrated values, which indicate the positions of integrated values NIO to N41 bracketed by , correspond to each other as shown below.

Nl0- (M10+M11+M20+M21+M30
+M31+M40+M41) Nll- (MIL+M21+M31+M41) N20-
(M20+M21+M30+M31+M40+M41
)N21- (M21+M31+M41)N30= (
M30+M31+M40+M41)N31- (M31
+M41) N40= (M40+M41) N41= (M41) Therefore, to calculate the data amount DAv using the cumulative frequency distribution table, DAv=16 (N10+N11+N20+N21+N
30+N31+N40+N4N processing is performed. As described later, since the cumulative frequency distribution table is created in memory, the threshold values MTH and T1
By using ~T4 as an address, reading out the frequencies at eight locations and adding them, the amount of information DAv can be obtained.

d. Examples of three-dimensional frequency distribution generation circuit, cumulative frequency distribution generation circuit, and threshold value determination circuit Three-dimensional frequency distribution generation circuit 5, cumulative frequency distribution generation circuit 6
The threshold value determination circuit 7 has a configuration shown in FIG. 9, for example. In FIG. 9, the maximum value MAX3 is supplied from the input terminal 41 to the address controller 44, the minimum value MIN3 is supplied from the input terminal 42 to the address controller 44, and the maximum value frame difference ΔF is supplied from the input terminal 43. is the address controller 44
supplied to

The address controller 44 is RAM45! , Jj in the horizontal direction (upper) and vertical direction (lower). This RAM 45 is arranged vertically (0 to 255).
It has addresses (0 to 255) in the horizontal direction, and all stored contents are cleared in the initial state. Multiple bits of data can be stored in one address of the RAM 45. This number of bits is sufficient to represent the number of blocks in two frame periods. The vertical address of the RAM 45 corresponds to the dynamic range DR3, and the horizontal address of the RAM 45 corresponds to the maximum frame difference ΔF.

When the maximum frame difference ΔF is limited to a number less than 255, for example 31, the horizontal addresses of RAM 45 are also reduced.

The data read from the RAM 45 is supplied to the adder circuit 46 via the register 52 having an output control function, and the output data of the adder circuit 46 is sent to R via the registers 47 and 48.
Supplied to AM45. A frequency distribution table is stored in the RAM 45 by being supplied with an address corresponding to the dynamic range DR3 and the maximum frame difference ΔF. That is, the output data of the RAM 45 is supplied to the adder circuit 46 via the register 52, and the output data of the adder circuit 46 is written to the same address in the RAM 45 via the registers 47 and 48.

The output of the +1 generating circuit 50 is supplied to the adding circuit 46 via a register 49. The above register 52, addition circuit 46, registers 47, 48, 49, and +1 generation circuit 50
As a result, a frequency distribution table (see FIG. 6) for two frame periods is created and stored in the RAM 45.

Next, the registers 51 and 52 are set to an output enabled state, and the register 49 is set to an output disabled state, and a cumulative frequency distribution table is created. The maximum frame difference Δ is stored in the RAM 45.
A horizontal address (upper address) that starts from 255 of F and decrements to 0 and a vertical address (lower address) that decrements by (-1) from 255 of dynamic range DR3 are supplied.

Based on this address, the data read from the RAM 45 is added to the previous data stored in the register 51 in the adder circuit 46.

The output data of the adder circuit 46 is written to the same address as the read address in the RAM 45.
5 stores an integrated frequency distribution table.

Then, in order to calculate the amount of generated information, the threshold values T1 to T4 in the level direction are sequentially supplied from the address controller 44 to the RAM 45 as lower address signals.

The upper address signal is the motion threshold MTH or (ΔF
-0). When the threshold values T4 to T1 are sequentially supplied to the RAM 45 as addresses in a state where they are initially set to (ΔF-0), the frequencies NIO, N20, . N30. N40
is read out.

Next, in a state where (ΔF=MTH), the threshold value T4~
When T1 is sequentially supplied to the RAM 45 as an address,
Frequency Nil, N21. N31. N41 is read. In this way, when the frequencies are read out sequentially, the output of the adder circuit 54 becomes (N10+N11+N20+N21 +N30+N31+N40+N41).
4 and MTH and corresponding data fi D A v to 16
It is nothing but the multiplied value.

The comparison circuit 56 generates a comparison output signal that becomes "O" when the amount of data exceeds the reference value (target value) from the terminal 57, and becomes "1" when the amount of data does not exceed the reference value. This comparison output signal is supplied to the address controller 44 through terminal 5. Address controller 44
When the comparison output becomes "L", it stops updating the threshold value and generates a threshold code pt indicating the current threshold value (Tl to T4 and MTH) at the output terminal 53.

The process of converting the frequency distribution table into an integrated type and the process of determining the optimal threshold value can be performed during the vertical blanking period.

FIG. 10 shows an example configuration of the address controller 44. As shown in FIG. In FIG. 10, the maximum value MAX3 and the minimum value MIN3 are supplied to the input terminals indicated by 41 and 42, respectively, and the output signal of the subtraction circuit 61 is supplied to the +1 generation circuit 75, whereby the dynamic range DR3 is calculated. .

This dynamic range DR3 is taken out to an output terminal 63 via a register 62 having an output control function. The address generated at this output terminal 63 is a vertical (lower) address of the RAM 45.

Further, an integration counter 64 is provided which sequentially generates output signals of 0 to 255, and the output signal of the integration counter 64 is taken out as an address signal to an output terminal 63 via a register 65 having an output control function.

Further, 66.67.6B and 69 respectively indicate ROM,
The ROM 66 stores, for example, 11 threshold values T1, and the other ROMs 67, 68, and 69 store similarly 11 threshold values T2, T2, T3, . T4 is stored. The ROMs 66-69 are supplied with the threshold code Pi generated by the address generation circuit 74 as an address.

The address generation circuit 74 is supplied with the output signal of the comparator circuit 56 from a terminal 58, and when the comparison output is "0", addresses that change at a predetermined period are supplied to the ROMs 66-69. The threshold values are sequentially read from the ROMs 66 to 69 until the amount of generated information becomes less than the reference value, that is, until the comparison output signal becomes "1". The threshold values read from each of the ROMs 66 to 69 are sent to the output terminal 6 via registers 70.71 and 72.73, each having an output control function.
It is taken out on 3rd. The registers 70 to 73 sequentially output threshold values.

In the address generation circuit 74, the threshold code Pi for specifying the optimal threshold value generated is output from the output terminal 5.
It is taken out on 3rd. This threshold code Pi is ADRC
It is used for encoding and is also transmitted.

The horizontal (upper) address of the RAM 45 is generated at the output terminal 83. The address generated at the output terminal 63 described above is an address related to the dynamic range DR3, whereas the address generated at the output terminal 83 is an address related to the maximum frame difference ΔF.

The maximum frame difference ΔF is supplied from the input terminal 43 and taken out to the output terminal 83 via a register 85 having an output control function. Reference numeral 81 indicates an integration counter, and an address that changes from 0 to 255 formed by this integration counter 81 is taken out to an output terminal 83 via a register 82 having an output control function. The integration counter 81 generates an address when forming a frequency distribution table.

Further, a ROM 84 is provided, and the output of the ROM 84 is taken out to an output terminal 83 via a register 85 having an output control function. This ROM 84 includes an address generation circuit 7.
The motion threshold value MTH read from the ROM 84 is used when calculating the data amount.

Further, a 0 generation circuit 87 is provided which generates an address when (ΔF; 0), and the output of the 0 generation circuit 87 is taken out to an output terminal 83 via a register 88 having an output control function.

In the address controller 44 described above, registers 86 and 62 are turned on when creating a frequency distribution table.

When creating a cumulative frequency distribution table, registers 82 and 65 are turned ON. During integration in the direction of the maximum frame difference ΔF, the output of the integration counter 81 changes from 255 to O within a period in which the output of the integration counter 64 is 255;
Next, within a period in which the output of the integration counter 64 is 254, the output of the integration counter 81 changes from 255 to 0. Thereafter, similar operations are repeated, and the output of the integration counter 81 changes from 255 toward O within the period in which the output of the integration counter 64 is O, thereby completing the integration in the direction of the maximum frame difference ΔF.

When integrating in the direction of the dynamic range DR3, the output of the integration counter 81 reaches the output of the integration counter 6 within a period of 255.
The output of the integration counter 81 changes from 255 to 0, and then the output of the integration counter 81 changes from 255 to 0 within the period of 254.
The output of 4 changes from 255 to 0. Thereafter, the same operation is repeated, and the output of the integration counter 64 changes from 255 to 0 within the period in which the output of the integration counter 81 is O, so that the integration in the direction of the dynamic range DR3 is completed, and the integration type A frequency distribution table is created.

Also, when calculating the amount of generated information, registers 85 and 88
．． 70 to 73 are turned on. Register 88 is ONL, (
During the period ΔF-0), registers 70 to 73 are sequentially turned ONL.
,, By the occurrence of threshold values T1 to T4, the frequency NIO
~N40 is obtained, and the register 85 is ONL, , (ΔF-
MTH), registers 70 to 73 are sequentially ONL,
, the frequency Ni1-N41 is obtained.

With the configuration shown in FIGS. 9 and 10 above, a three-dimensional frequency distribution table is formed, this frequency distribution table is converted into an integral type table, and an optimal threshold value is determined. Further, although not shown, the address controller 44 generates a motion threshold MTH for determining the optimal threshold, and this motion threshold MTII is supplied to the motion determination circuit 10 to perform frame dropping processing. It will be done.

In FIG. 1, a frame difference detection circuit 9 is provided separately from the detection circuit 3, but the maximum frame difference ΔF obtained by the detection circuit 3 is stored, and this maximum frame difference is used to detect the movement. The determination may be made, and the three-dimensional ADRC encoder 11 and the two-dimensional ADRC encoder 13 may have a common circuit configuration.

〔Effect of the invention〕

In a high-efficiency encoding device such as a three-dimensional block variable length ADRC, the amount of generated information is reduced from a target value in consideration of the fact that the amount of transmitted information is compressed by frame drop processing in the still area. In order to keep it small, not only the dynamic range DR but also a motion threshold is introduced. Therefore, by changing the motion threshold, the area treated as a stationary block increases, and the threshold in the level direction does not need to be made stricter accordingly. Therefore, according to the present invention, quantization noise in a restored image can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the recording side of an embodiment of the present invention, FIGS. 2, 3, and 4 are route diagrams for explaining the block configuration, and FIG. 5 is a diagram of the ADRC encoder. An example block diagram, Figures 6 and 7 are route maps for explaining the frequency distribution table, Figure 8 is a route map used for explaining the calculation of the amount of generated information, and Figure 9 is a three-dimensional frequency distribution generation circuit. and a block diagram of an example of a threshold value determination circuit; FIG. 10 is a block diagram of an example of an address controller which is a part of FIG. 9;
FIG. 11 is a route diagram for explaining the previously proposed buffering circuit. 11: 3-dimensional ADRC encoder, 12: averaging circuit, 13: 2-dimensional ADRC encoder. Agent: Patent Attorney Masatoshi Sugiura Explanation of the main symbols in the drawing 1: Digital video signal input terminal, 2-block conversion circuit, 3: Detection circuit, 5: 3-dimensional frequency distribution generation circuit, 6: Integrating frequency distribution Generation circuit, 7: Threshold determination circuit,

Claims (1)

[Claims] Means for determining the maximum value, minimum value, and dynamic range of a plurality of pixel data included in a block consisting of regions belonging to a plurality of frames of a digital image signal, and detecting the amount of motion for each block. means for inputting the frequency of each block into a memory using the dynamic range and the amount of movement for each block as addresses, and calculating the frequency distribution by summing up the frequencies over a predetermined period; and calculating the dynamic range from the frequency distribution. A means for obtaining an integrated frequency distribution by sequentially accumulating frequencies in the address direction and the address direction of the above-mentioned amount of movement, and a frame dropping process that averages corresponding pixel data between multiple fields for blocks whose movement amount is less than a predetermined amount. means for compressing and encoding a plurality of pixel data in the block according to the dynamic range of the block; and means for compressing and encoding the plurality of pixel data in the block according to the dynamic range of the block; 1. A high-efficiency encoding device, comprising: means for setting the number of encoding bits.