JP2508483B2 - Digital image signal buffering device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to the transmission rate of recorded data when a variable-length encoded digital video signal is recorded on, for example, a magnetic tape. The present invention relates to a digital image signal buffering device applied to control to a corresponding predetermined value.

SUMMARY OF THE INVENTION According to the present invention, when a plurality of thresholds are set for the dynamic range and the pixel data are coded with different numbers of bits corresponding to the plurality of thresholds, it is optimal. Multiple thresholds are generated. That is, when the integrated value of each occurrence frequency of the dynamic range of one frame period of the digital video signal is obtained, and a threshold set consisting of a plurality of threshold values prepared in advance is applied to this integrated value. The total number of bits is detected, it is determined whether the total number of bits exceeds the target value, the degree of distortion when the threshold set is applied is examined, and the range that does not exceed the data rate of the transmission line is checked. And variable length coding is performed using a threshold value that minimizes distortion.

[Conventional technology]

The applicant of the present application obtains a dynamic range defined by the maximum value and the minimum value of a plurality of pixels included in a two-dimensional block as described in Japanese Patent Application No. 59-266407, and determines the dynamic range as the dynamic range. We have proposed a high-efficiency coding device that performs the applied coding. In addition, Japanese Patent Application No. 60-
As described in Japanese Patent No. 232789, there has been proposed a high-efficiency coding apparatus which performs coding adapted to a dynamic range for a three-dimensional block formed from pixels in regions included in each of a plurality of frames. Furthermore, Japanese Patent Application Sho 60-
As described in Japanese Patent No. 268817, there is proposed a variable length coding method in which the number of pits changes according to the dynamic range so that the maximum distortion generated when quantization is made constant.

High efficiency code (AD
It is called RC. ) Is applicable to a digital VTR because it can significantly reduce the amount of data to be transmitted. In particular, the variable length ADRC can increase the compression rate. However, the variable length ADRC uses a fixed rate transmission line such as a digital VTR that records a predetermined amount of data such as one frame and one field as one track because the amount of transmission data varies depending on the content of the image. When doing, buffering processing is required. If the length of one frame or one field of the recorded data is not uniform without performing the buffering process, inconvenience may occur in terms of variable speed reproduction, editing and the like.

The applicant of the present application, as shown in Japanese Patent Application No. 61-257586, finds the occurrence frequency of each value of the dynamic range of one frame in the case of variable length ADRC, integrates the occurrence frequencies, and integrates them. We have proposed a method of forming a frequency distribution table and easily calculating the total number of bits when the threshold value is changed.

FIG. 17 shows the configuration of the above application, in which the digital video signal to be encoded is supplied from the input terminal indicated by 110. This input digital video signal is supplied to the minimum value detection circuit 111, the maximum value detection circuit 112 and the subtraction circuit 113. In the subtraction circuit 113, the minimum value is subtracted from the pixel data, and the data ΔV after removal of the minimum value is obtained from the subtraction circuit. The data ΔV after the removal of the minimum value is stored in the buffer memory 114.

Minimum value (MIN) detected by the minimum value detection circuit 111
Are stored in the buffer memory 115. Maximum value detection circuit 112
The maximum value (MAX) detected in the buffer memory 116
Stored in. The maximum value and the minimum value are supplied to the subtraction circuit 123, the dynamic range DR that is the difference between the maximum value and the minimum value is obtained from the subtraction circuit 123, and this dynamic range DR is supplied to the frequency distribution detection circuit 118. The frequency distribution detection circuit 118 forms an integrated type frequency distribution table as shown in FIG.

In FIG. 19, the vertical axis represents the frequency of occurrence and the horizontal axis represents the dynamic range DR. This is a case where a set of four thresholds TH0 to TH3 is applied to the dynamic range DR. The blocks included in the range of each dynamic range DR divided by these threshold values are encoded into code signals of word lengths of 0 bit, 1 bit, 2 bits, 3 bits, and 4 bits. Therefore, with the set of thresholds,
For example, the total number of bits in one frame period changes. The frequency corresponding to the threshold value TH3 is the total frequency of forming the 4-bit code signal, and the frequency corresponding to the good value TH2 is the total frequency of forming the 3-bit and 4-bit code signals. And the frequency corresponding to the threshold TH1 is 2
It is the sum of the frequencies at which the bit, 3-bit and 4-bit code signals are formed, and the frequency corresponding to the threshold TH0 is 1.
It is the sum of the frequencies at which bit, 2 bit, 3 bit and 4 bit code signals are formed.

The threshold value arithmetic circuit 119 is provided with a plurality of threshold value sets, and the plurality of threshold value sets are sequentially applied to the integrated type frequency distribution table to calculate the total of each threshold value set. The number of bits is calculated. This total number of bits is compared with the data transmission capacity of the transmission line to determine a threshold set that does not exceed the data transmission capacity. This threshold set is supplied to the ADRC encoder 120.

The data after the minimum value removal and the dynamic range DR from the subtraction circuit 117 are supplied to the ADRC encoder 120. Dynamic range D in ADRC encoder 120
Quantization is done using R and a threshold set. This ADR
The buffer memory 121 stores the code signal from the C encoder 120, the minimum value, the maximum value, and the code signal indicating the threshold value set.
Is output to the output terminal 122 from the buffer memory 121 at a constant data rate.

The buffering device described above operates according to the timing shown in FIG. FIG. 18 shows a pulse signal that is inverted for each field of input data. In the valid data period T1 of one frame period of the input data, the minimum value and the maximum value are detected, the minimum value and the maximum value are written to the buffer memories 115 and 116, the dynamic range DR is integrated, and the minimum value is calculated. The data after the removal is written to the buffer memory 114.

In the next period T1 ', the optimum threshold value is calculated. In the next frame period, ADRC encoding of each pixel is performed using the optimum threshold value, and the code signal resulting from the ADRC encoding is written in the buffer memory 121. Along with this, it is written in the minimum and maximum value buffer memory 121. Then, in the next frame period T3, the contents of the buffer memory 121 are read out at a constant rate.

[Problems to be solved by the invention]

The invention described in the above application has a problem that the required memory capacity becomes large in order to perform the processing for three frames. Further, although the generated information amount can be prevented from overflowing, consideration has not been given to the point of quantization distortion.

Therefore, an object of the present invention is to configure a device with a small memory capacity, and to set a threshold value that minimizes quantization distortion within a range in which the data length of encoded data within a predetermined period such as one frame does not overflow. It is an object to provide a buffering device for a digital image signal that can be set.

[Means for solving problems]

According to the present invention, a digital image signal is divided into blocks, a circuit that detects the maximum value, the minimum value, and the dynamic range for each block, and the frequency of occurrence of each of the dynamic range within a predetermined period or the data obtained by compressing the dynamic range are aggregated. A circuit that sequentially accumulates the occurrence frequencies of the dynamic range or the data in which the dynamic range is compressed to generate an integrated value of the occurrence frequency, and encoding when multiple threshold values are set for the integrated value of the occurrence frequencies. A circuit that determines whether the total number of bits of the code exceeds a target value corresponding to the transmission path, and generates data indicating the degree of distortion when a plurality of threshold values are set for the integrated value of the occurrence frequency. A circuit that generates a plurality of thresholds whose total number of bits does not exceed a target value and reduces the degree of distortion, and a plurality of determined thresholds Used, Sadamari dynamic range of each block, and with the original in a short number of bits than the number of quantization bits, and the encoding circuit for compressing the pixel data of the block are provided.

[Action]

For example, the occurrence frequencies of the dynamic range DR or the compressed dynamic range DR ′ within one frame period are integrated, and a preset threshold value set is applied to the distribution of the occurrence frequencies. The total number of bits is calculated for each set of thresholds. Also, for each set of thresholds, the degree of distortion is examined. A threshold set that minimizes distortion is selected as long as the total number of bits does not exceed the target value determined by the data rate of the transmission path. The ADRC encoding is done using this set of thresholds.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. This description will be given in the following order.

a. Configuration on recording side b. Configuration on playback side c. Overall operation timing d. Variable length ADRC e. Threshold value generating part a. Configuration on recording side FIG. 1 shows the recording side of one embodiment of the present invention. Shows the configuration of. In FIG. 1, an input terminal designated by 1 is supplied with a digital video signal converted into a block order. As an example, as shown in FIG. 2, one block has a size of (6 lines × 6 pixels). The screen of one frame is divided in units of this block. Second
In the figure, digital video signals are supplied from an input terminal 1 in the order of numbers. Further, one sample of the digital video signal is 8 bits, and the sampling frequency is 13.5 MHz.

The digital video signal is supplied to the ADRC encoder 2. The ADRC encoder 2 is composed of a minimum value detection circuit 3, a maximum value detection circuit 4, a quantization circuit 5, and subtraction circuits 6 and 7. The minimum value detection circuit 3 detects the minimum value in the pixel data of one block, and the maximum detection circuit 4 detects the maximum value in the pixel data of one block. In the subtraction circuit 6, the minimum value is subtracted from the input data, and the data after the removal of the minimum value is supplied to the quantization circuit 5. In the subtraction circuit 7, the minimum value is subtracted from the maximum value, and the dynamic range DR of each block is detected.

The data after the minimum value removal and the dynamic range DR are supplied to the quantization circuit 5, and the quantization circuit 5 forms a code signal in which the number of quantization bits of one pixel is compressed from 8 bits to 4 bits. . This code signal is supplied to the rearrangement circuit 9 of the buffering unit 8. The output signal of the rearrangement circuit 9 is supplied to the pixel data buffer 10. Further, the minimum value from the minimum value detection circuit 3 of the ADRC encoder 2 is supplied to the minimum value buffer 11. Further, the maximum value from the minimum value detection circuit 4 is supplied to the maximum value buffer 12.

The pixel data buffer 10, the minimum value buffer 11, and the maximum value buffer 12 temporarily store data, and the read timing is controlled by a control signal from the buffer controller 17. The data read from the buffers 10, 11 and 12 are supplied to the multiplexer 13,
Output data is generated at the output terminal 15 of the multiplexer 13.

The threshold value for the variable length ADRC is generated by the threshold value generation unit 18. The threshold value generator 18 is provided with an integrating circuit 19, which allows the dynamic range to be increased.
The cumulative frequency distribution of DR is obtained. The output signal of the integrating circuit 19 is supplied to the total bit number calculating circuit 20 and the distortion calculating circuit 21. Output signals of the total bit number calculation circuit 20 and the distortion calculation circuit 21 are supplied to the determination circuit 22. From the output signals of these total bit number calculation circuit 20 and distortion calculation circuit 21, the determination circuit 2
2, the total number of bits does not exceed the data rate of the transmission line,
In addition, a threshold value that minimizes quantization distortion is determined.

The threshold code corresponding to the optimum threshold value determined by the judgment circuit 22 is the threshold value generation circuit 23.
Is supplied to. The threshold value generation circuit 23 is composed of, for example, a ROM, and a threshold value set from four threshold values TH0 to TH3 is generated by a threshold code from the determination circuit 22. The threshold generator 18 includes a set counter.
A 30S and a level counter 30L are provided.

The thresholds TH0 to TH3 generated by the threshold generator 18 are AD
It is supplied to the level comparators 25, 26, 27 and 28 of the RC encoder 24, respectively. These level comparators 25-27 include a subtraction circuit 14
The dynamic range DR from is supplied. The output signals of the level comparators 25 to 27 are priority encoders 29.
Is supplied to.

The level comparators 25 to 27 generate output signals which become "1" when the dynamic range DR is larger than the threshold values TH0 to TH3, respectively. The priority encoder 29 determines the level relationship with respect to the threshold value of the dynamic range DR from the output signals of the level comparators 25 to 27, and determines the quantization bit number, that is, the word length. This word length is stored in the word length memory 16 of the buffering unit 8. A buffer controller 17 generates a necessary control signal based on the word length data stored in the word length memory 16.

The recording data generated at the output terminal 15 of the multiplexer 13 is subjected to processing such as error correction code encoding and digital modulation, if necessary, and is recorded on the magnetic tape by the rotary head.

The reproduction data reproduced by the rotary head from the magnetic tape is decomposed by a demultiplexer (not shown) into additional data for each block of maximum value, minimum value and threshold code and a code signal corresponding to each pixel. It The threshold code is supplied to the ROM, and a set of threshold values (TH0 to TH3) corresponding to the threshold code is generated.

b. Structure on the reproducing side FIG. 3 shows the structure on the reproducing side. In FIG. 3, a code signal for each pixel is supplied to an input terminal indicated by 31 and a minimum value MIN is supplied to an input terminal indicated by 32. The maximum value MAX is supplied to the input terminal indicated by 33. The sets of thresholds TH0, TH1, TH2, TH3 generated based on the received threshold code are supplied to the input terminals 34, 35, 36, 37 respectively. These threshold values are supplied to the level comparators 38, 39, 40, 41 and compared with the dynamic range DR from the subtraction circuit 42. The output signals of the level comparators 38 to 41 are priority encoders.
43, the word length code is supplied to the priority encoder
It originates from 43.

The word length code and the code signal from the input terminal 31 are supplied to the multiplication coefficient generation circuit 44, and the generated multiplication coefficient is supplied to the multiplication circuit 45. The multiplication circuit 45 multiplies the multiplication coefficient by the dynamic range DR from the subtraction circuit 42, and the multiplication output is supplied to the addition circuit 46. The output signal of the multiplication circuit 45 is the restoration level after removal of the minimum value, and the minimum value MIN is added to the output signal of the multiplication circuit 45 by the addition circuit 46. The output signal of the adder circuit 46 is taken out to the output terminal 47 as the restored data.

c. Overall Operation Timing In one embodiment of the present invention, the digital video signal is AD
The RC is coded, the code signal obtained by the coding is written in the pixel data buffer 10, the integrated frequency distribution of the dynamic range DR in one frame period is calculated, and then from this frequency distribution The optimal threshold is determined, and this threshold determines the word length of each block,
The code signal converted into the determined word length is read from the pixel data buffer 10.

FIG. 4 shows the timing of the operation of this embodiment, which is one frame period T1 of the input digital video signal.
At (t0 to t1), ADRC encoder 2
And the dynamic range DR is detected. This dynamic range DR is the threshold value generator 18
And the integrated frequency distribution of the dynamic range DR is obtained. Further, the code signal from the ADRC encoder 2 is written in the pixel data buffer 10 via the rearrangement circuit 9 of the buffering unit 8. The maximum value and the minimum value from the ADRC encoder 2 are written in the minimum value buffer 11 and the maximum value buffer 12, respectively.

In the period T2 (t1 to t2) of the next frame, the threshold generation unit 18 does not exceed the bit rate of the transmission line,
In addition, an optimum threshold value is obtained in the sense that distortion is small. Level comparator during the next period T3 (t2 to t3)
25-28 and the priority encoder 29, the previous 1
The word length of each block of data in the frame period is calculated,
This word length is stored in the word length memory 16.

In the one frame period T4 of (t3 to t4), the pixel data buffer 10 controls the buffer controller 17 to
The code signal is read. In this case, the variable length code signal is read by referring to the word length of each block stored in the word length memory 16.

d. Variable-length ADRC The variable-length ADRC in this embodiment performs ADRC encoding of fixed 4 bits in the ADRC encoder 2, and when reading from the pixel data buffer 10, 1 bit, 2 bits, 3 in order from the least significant bit. This is a method of forming a code signal having a word length of 3 bits, 2 bits, 1 bit, and 0 bits other than 4 bits by removing bits and 4 bits.

FIG. 5 illustrates a case where a predetermined dynamic range DR is encoded by the above method. Since the ADRC encoder 2 quantizes 4 bits, the dynamic range DR is divided into (2 ⁴ = 16), and the central level of each level range is set as the representative level. In the quantization circuit 5,
4-bit code signals (0000) to (1111) are assigned according to which level range the level of the pixel data after the minimum value removal belongs. For example, when the level of pixel data after removal of the minimum value is included in the third level range from the bottom, this pixel data is encoded into a code signal of (0010). The quantization circuit 5 is composed of a ROM. Further, at the time of decoding, the code signal is restored to the representative level.

If the least significant bit of 4 bits is removed, (000) to (1
A result equivalent to the state encoded by the 3-bit code signal of 11) is obtained. When the least significant bit and the next bit are removed, a result equivalent to the state encoded by the 2-bit code signal (00) to (11) is obtained. By removing 3 bits from the least significant bit, a result equivalent to the state encoded by the 1-bit code signal is obtained. If all 4 bits are removed, a result equivalent to the case where the code signal is 0 bit, that is, the code signal is not transmitted, is obtained. The representative level for 0 bit is an intermediate level between the maximum value and the minimum value.

The above variable length coding is performed by the rearrangement circuit 9 and the pixel data buffer 10. The operations of the rearrangement circuit 9 and the pixel data buffer 10 will be described with reference to FIG.

FIG. 6A shows a 4-bit code signal output from the quantization circuit 5. In FIG. 6, the code (i-j) attached to each bit is (i: pixel number in the block, i
= 1-36) (j: 4-bit bit number, least significant bit: j
= 0, most significant bit: j = 3). The output data of the quantization circuit 5 is 4-bit parallel data for each pixel.

The rearrangement circuit 9 collects the bits of the same bit number in the output data of the quantization circuit 5 every 4 bits to form 4-bit parallel data shown in FIG. 6B.
The output data of the rearrangement circuit 9 is written in the pixel data buffer 10 in order from the address n, as shown in FIG. 6C. In this way, if the data whose arrangement has been changed by the rearrangement circuit 9 is written in the pixel data buffer 10, it becomes easy to control the word length. That is, one block
Corresponding to 36 pixels, as shown in FIG. 6C at the addresses (n to n + 35), if the data is written, the address becomes (+
1) step by step, n, (n + 4) ... Addresses are skipped in the case of a word length 3 bit block, and n, (n + 1), in the case of a word length 2 bit block.
If the addresses (n + 4), (n + 5) ... Are skipped and the word length is a block of 1 bit, n, (n +
1), (n + 2), (n + 4), (n + 5), (n +
6) The addresses of ... Are skipped. If the block has a word length of 0 bits, no data is read out.

The data read from the pixel data buffer 10, the minimum value buffer 11, and the maximum value buffer 12 and combined by the multiplexer 13 are output as 8-bit parallel data, as shown in FIG. Maximum value MAX and minimum value M
IN is supposed to be located in the data at a constant cycle Tx. FIG. 7 shows an example of 1-bit data in which the n-th block is 3-bit data in which only the least significant bit is removed, and the (n + 1) -th block is in which 3 bits including the minimum value bit are removed. Shows.

e. Threshold Generation Unit The threshold generation unit 18 is configured as shown in FIG. 8 as an example. The integrating circuit 19 calculates the frequency of occurrence of the dynamic range DR in various one frame periods. In this embodiment, in order to reduce the circuit scale, the compression of the dynamic range DR is integrated. The original dynamic range DR is in the range of (0 to 25) because it is 8 bits, but this dynamic range is compressed into 36 types of (0 to 35). Expressed as an analog value, nonlinear compression is performed as shown in FIG.

In FIG. 8, the dynamic range DR is supplied to the input terminal indicated by 51, and this dynamic range DR is
The level is digitally compressed by being supplied to 2 as an address input. The ROM 52 has, for example, a 14-bit address input, and is supplied with the dynamic range DR as the upper 8 bits of the address signal. The lower 6-bit address signal of the ROM 52 supplied from the terminal 53 is
When the 8-bit address has a predetermined value, it is incremented by 1 bit.

1-bit output data is generated from the ROM 52. ROM
As shown in FIG. 10, when the address corresponding to the dynamic range DR of (0 to 255) is input, 52 becomes (0 to
The 36-bit output of 35) is output one bit at a time.
In the case of (DR = 3), for example, as shown in FIG. 11, the compressed dynamic range DR ′ in which the first 3 bits are “0” and the latter 33 bits are “1” is read from the ROM 52 to 1 It is output bit by bit. In FIG. 11, CLK indicates a sample clock, the dynamic range of the block of the n-th block is obtained at the end of the timing, and the ROM 52 is read at the timing of the next (n + 1) -th block.
Output occurs.

The dynamic range DR ′ is supplied to the adder circuit 54. The output side of the adder circuit 54 has 37 registers L1 ...
L37 is connected. The registers L1 to L37 have 13-bit parallel inputs / outputs. These 13 bits are 1
The number of bits required and sufficient to represent the total number of blocks in the frame. The outputs of the registers L1 to L36 are supplied to the multiplexer 55, and the output of the register L37 is fed back to the adder circuit 54. Registers L1 to L37 have terminals 5
It is reset at the same time by the reset pulse of the frame cycle supplied from 6.

As mentioned above, the 36-bit serial output of ROM52 is
Dynamic range DR and corresponding dynamic range D
After the bit with a value larger than R'becomes "1",
By repeatedly adding in the adding circuit 54,
After the elapse of one frame period, the cumulative frequency distribution data of the dynamic range DR 'is stored in each of the registers L1 to L36, as shown in FIG.

The multiplexer 55 sequentially selects each of the 36 integrated frequencies stored in each of the registers L1 to L36 after the elapse of one frame period, and outputs them to the total bit number detection circuit 20 and the distortion detection circuit 21. . Total bit number detection circuit 20
Indicates whether the total number of bits per frame is overflowing the target number of bits when the set of candidate threshold values is applied to the cumulative distribution of the dynamic range DR ′. Generate a flag.

A method of calculating the total number of bits will be described with reference to FIG. The additional data such as the maximum value MAX has a predetermined number of bits, unlike the word length, and is therefore ignored in the calculation of the total number of bits.

FIG. 13 shows the dynamic range DR ′ with the horizontal axis compressed.
And the vertical axis is the occurrence frequency P (DR ') within one frame period of the block having the value of the dynamic range DR'. (MI
In the range of N ≦ DR ′ ≦ TH1), the code signal is not transmitted. In the range of (TH0 + 1 ≦ DR ′ ≦ TH1), 1-bit quantization is performed. In FIG. 13, a curve 60 shows a range in which 1-bit quantization is performed. (TH1 + 1≤DR'≤TH
In the range of 2), 2-bit quantization is performed. Curve 61
Indicates the range in which 2-bit quantization is performed. (TH2
In the range of + 1 ≦ DR ′ ≦ TH3), 3-bit quantization is performed. The curve 62 shows the range in which 3-bit quantization is performed. In the range of (TH3 + 1 ≦ DR ′ ≦ MAX), 4-bit quantization is performed. Curve 63 shows the range in which 4-bit quantization is performed.

In FIG. 13, the shaded area (A + B + C +
D) is the total number of bits St. This total number of bits St is
In FIG. 13, the number of bits included in the area not shaded for each of the quantization bit numbers is S (TH0),
If S (TH1), S (TH2), S (TH3), then the following formula is obtained.

St = {S (MAX) -S (TH0)} + {S (MAX) -S (TH
0)} + {S (MAX) -S (TH0)} + {S (MAX) -S (T
H0)} = S (MAX)-{S (TH0) + S (TH1) + S (TH2)
+ S (TH3)} ..... Let Sr be the target number of bits allowed per frame of recorded data, then the relationship of Sr ≧ St ..

From formulas and formulas {S (TH0) + S (TH1) + S (TH2) + S (TH3)} ≧ 4S
(MAX) -Sr Here, if the total number of blocks in one frame is K, then 4S (MAX) -Sr = 4K-St ..., By making the value obtained by the equation constant,
The overflow of recorded data can be prevented.

The total bit number detection circuit 20 calculates the total bit number St as described above. The total bit number detection circuit 20 includes a data selector 71, a ROM 72, an addition circuit 73, a latch 74 and a latch 7.
It is composed of 7 and. The ROM 72 generates a control signal for controlling the data selector 71 corresponding to the set of prepared threshold values. The output signal of the multiplexer 55 is supplied as one input signal of the data control 71, and the data of "0" (data of all 13 bits being "0") is supplied as the other input signal of the data control. The output signal of the data selector 71 and the output signal (for example, 17 bits) of the addition circuit 73 via the latch 74 are supplied to the addition circuit 73. The output signal of the adder circuit 73 is the level comparator 75.
And is compared with the reference bit number St from the terminal 76 in the level comparator 75. Level comparator
The 75 generates a 1-bit flag which becomes "1" when the relation of the expressions is established. The 1-bit flag from the level comparator 75 is stored in the latch 77.

FIG. 14 shows one cycle of the operation for obtaining the total number of bits St for one set of prepared threshold values. FIG. 14A shows the dynamic range from the integrating circuit 19.
The cumulative distribution of DR 'is shown. Further, FIG. 14B shows a control signal generated by the ROM 72. When this control signal is low level, especially when the data selector 71 selects the data of “0” and the control signal is high level,
The data selector 71 selects the output data from the multiplexer 55. The output signal SC of the set counter 30C and the output signal LC of the level counter 30L are supplied to the ROM 72, and the control signal shown in FIG. 14B is generated corresponding to the setting of the threshold value. That is, the data selector 71 selects the integrated frequency corresponding to each of the thresholds TH0 to TH3.

By the above operation, the output signal of the adder circuit 73 changes as shown in FIG. 14C, and when the input of the integrated frequency of the maximum value of the dynamic range DR 'is completed, the level comparator 75 performs the comparison operation. . The bit number flag from the latch 77 is supplied to the AND gate 102 of the determination circuit 22.

The distortion calculation performed by the distortion calculation circuit 21 will be described below.

The maximum distortion in a block is D = DR '/ 2 ^{B + 1} ..., Where B is the number of bits assigned to each pixel of the block. As is clear from FIG. 5, the maximum distortion D varies depending on the word length. When the word length is (0 bit, 1 bit, 2 bit, 3 bit, 4 bit), the maximum distortion D is (1 / 2DR ', 1 / 4DR', 1 / 8DR ', 1 / 16DR', 1 / 32D
R ′). If this maximum distortion is converted into a relative value, (16D
R ', 8DR', 4DR ', 2DR', DR '). Therefore, the total sum Dt of the maximum distortions within one frame is expressed by the following equation.

In the above equation, P (DR ') is the dynamic range D
Indicates the frequency of occurrence of R '. Therefore, the formula can be converted into the following formula.

FIG. 15 is a graph for explaining the sum Dt of one frame of maximum distortion, in which the vertical axis represents maximum distortion and the horizontal axis represents dynamic range DR ′. In FIG. 15, 80 is the maximum distortion when the code signal is 0 bits, 81 is the maximum distortion when the code signal is 1 bit, and 82 is the maximum distortion when the code signal is 2 bits. 83 indicates the maximum distortion when the code signal is 3 bits, and 84 indicates the maximum distortion when the code signal is 4 bits.

As is clear from the above formula, the total sum Dt of the maximum strains when the threshold values TH0 to TH3 are set is as shown in FIG.
It is the area of the shaded area. The distortion detection circuit 21
The calculation of the formula is performed for each of the threshold sets, and the total sum Dt of the maximum strains is calculated.

The distortion detection circuit 21, as shown in FIG.
It comprises a data selector 86, a simple gate circuit 87, a latch 88, a multiplication circuit 89, a ROM 90, an adder circuit 91, a latch 92 and a latch 93. The multiplexer 55 supplies the integrated value of the dynamic range DR ′ to the adder circuit 85 and one input terminal of the data selector 86.

“0” data is supplied to the other input terminal of the data selector 86. The output signal of the data selector 86 is supplied to the subtraction circuit 85 via the latch 88. Since the latch 88 causes a delay of one clock, the subtraction circuit 85
The two input terminals are supplied with two data having a time difference of one clock. That is, the occurrence frequency (integrated value) shown in FIG. 16A is supplied to one input terminal of the subtraction circuit 85, and the occurrence frequency shown in FIG. 16B is supplied to the other input terminal of the subtraction circuit 85. The data selector 86 is controlled by the simple gate 87 so as to select “0” data when the dynamic range DR ′ is the integrated frequency S (0) of 0.

Therefore, the output signal of the subtraction circuit 85 is (0, P (0), P (1), ... P (35) in FIG. 16C.
The frequency of occurrence of each of the dynamic range DR ′ of (35) to (35) is itself. The output signal of the subtraction circuit 85 is supplied to the multiplication circuit 89 and is multiplied by the coefficient from the ROM 90. In ROM90,
The output signal SL of the level counter 30L and the output signal SC of the set counter 30C are supplied. From ROM90, the threshold value is T
Up to H0, 16 coefficients are generated, and from (TH0 + 1) to TH1,
A coefficient of 8 is generated, a coefficient of 4 is generated from (TH1 + 1) to TH2, a coefficient of 2 is generated from (TH2 + 1) to TH3, and a coefficient of 1 is generated from (TH3 + 1) to (35). Occurs.

When the output signals of the multiplication circuit 89 corresponding to the respective dynamic ranges DR 'are represented as E0 to E35, the output signals of the multiplication circuit 89 are as shown in FIG. 16D. The output signal of the multiplication circuit 89 is supplied to the addition circuit 91. The output signal of the adder circuit 91 is fed back as another input signal of the adder circuit 91 via the latch 92. Therefore, the output signal of the adder circuit 91 is
16 The result is shown in FIG. The output signal of the adder circuit 91 is supplied to the latch 100 and the level comparator 101 of the determination circuit 22 via the latch 93.

The output signal of the latch 100 is fed back to the level comparator 101. The level comparator 101 compares the sum of maximum distortion from the distortion detection circuit 21 and the value from the latch 100,
When the value fed back to the input is larger, an output signal that becomes low level is generated. This level comparator 10
The output signal of 2 is inverted and supplied to the AND gate 102. The output signal of the AND gate 102 is the latch 100 and the latch 103.
Is supplied to. These latches 100 and 103 are enabled at high level.

The total bit number flag is, as described above, a high level flag when the total bit number does not exceed the target value. The sum of maximum distortion is calculated sequentially for multiple sets of thresholds for which the level comparator 10
For the output signal of 1, the total bit number flag is high level,
Further, the level becomes low when the total sum of maximum distortions is smaller than the total maximum distortions input before the user.

The output signal SC of the set counter 30C is supplied to the latch 103. At the stage when the total bit count flag and the maximum distortion summation for all the sets of thresholds prepared are input, the content of the latch 103 is such that the maximum distortion summation is within the range in which the total bit count does not overflow. It gives the smallest set of thresholds.

The signal indicating the threshold set from the above-mentioned determination circuit 22 is
It is supplied to the ROM 104. The ROM 104 stores all threshold sets, and the threshold set specified by the output signal of the determination circuit 22 is taken out as an output.

〔The invention's effect〕

According to the present invention, the data amount of a field, frame, etc. in a predetermined period can be set to a fixed amount, and
In the case of VTR, one field or one frame can be recorded as one track, and variable speed reproduction, editing, etc. can be performed without trouble as in the conventional VTR using a fixed length code. . According to the invention, 1
The buffering process of the data for the frame can be performed in a short time, and the required memory amount can be reduced. Further, according to the present invention, the threshold value is determined so that the quantization distortion becomes small, so that it is possible to prevent deterioration of the image quality of the restored image.

[Brief description of drawings]

FIG. 1 is a block diagram showing the structure of the recording side in one embodiment of the present invention, FIG. 2 is a schematic diagram showing the size of blocks in this one embodiment, and FIG. 3 is a reproducing side in this one embodiment. FIG. 4 is a timing chart for explaining the operation of this embodiment, FIG. 5 is a schematic diagram for explaining the variable length ADRC of this embodiment, and FIG. FIG. 7 is a timing chart for explaining the operation of the data rearrangement circuit in one embodiment, FIG. 7 is a schematic diagram showing the structure of the output data of the multiplexer, and FIG. 8 is a concrete example of the threshold value generator in this embodiment. Block diagrams showing the structure, FIGS. 9, 10, 12, and 13 are schematic diagrams for explaining the dynamic range integrating operation in this embodiment, and FIG. 11 is the dynamic range integrating operation. Timing Cha to explain FIG. 14 is a timing chart for explaining the total bit number detecting operation, FIGS. 15 and 16 are schematic diagrams and timing charts for explaining the total distortion maximum detecting operation, and FIG. FIG. 18 is a block diagram of an example of the previously proposed buffering device, and FIGS. 18 and 19 are a timing chart and a schematic diagram for explaining the previously proposed buffering device. Description of main symbols in the drawing 1: Input terminal, 2, 24: ADRC encoder, 8: Buffering section, 15: Output terminal, 18: Threshold generation section, 19: Accumulation circuit, 2
0: Total bit number detection circuit, 21: Distortion calculation circuit, 22: Judgment circuit.

Claims (1)

(57) [Claims] 1. Dividing a digital image signal into blocks,
A means for detecting the maximum value, the minimum value, and the dynamic range for each block, and aggregating the occurrence frequency of each of the dynamic range or the data obtained by compressing the dynamic range within a predetermined period, and calculating the dynamic range or the dynamic range. Means for sequentially accumulating the occurrence frequencies of the compressed data to generate an integrated value of the occurrence frequencies, and the total number of bits of the encoded code when a plurality of thresholds are set for the integrated value of the occurrence frequencies. Means for determining whether or not exceeds a target value corresponding to the transmission path, and means for generating data indicating the degree of distortion when the plurality of threshold values are set for the integrated value of the occurrence frequency, A means for generating the plurality of thresholds, wherein the total number of bits does not exceed a target value, and the degree of the distortion is reduced; And a coding means for compressing the pixel data of the block with a bit number which is determined by the dynamic range of each block using a threshold value and which is shorter than the original quantization bit number. Image signal buffering device.