JPH02105786A - Data compression circuit for electronic still camera - Google Patents

Abstract

PURPOSE:To record digital image pickup signals in real time while the picture quality is well maintained by compressing data by an inter-frame process which is a three-dimensional process at the time of consecutive photographing operations. CONSTITUTION:In a state where digital image pickup signals from an A/D converter 2 are supplied to the terminal (a) of a switch circuit 3 and a camera makes consecutive photographing operations, the terminals (a) of switch circuits 3 and 4 are successively connected to terminals (c) and (d). Namely, during the consecutive photographing operations where image pickup signals of five frames F1-F5, etc., are obtained in (t) seconds the image pickup signal of the first frame F1 is supplied to a two-dimensional ADRC encoder 7 through the terminal (c) of the switch circuit 3 and the image pickup signals of the remaining four frames F2-F5 are supplied to an adaptive frame omission circuit 8 where the signals are subjected to a three-dimensional process and reduced in data quantity through the terminal (d) of the circuit 3. Therefore, the data produced at the time of consecutive photographing operations can be recorded in real time without deteriorating the picture quality.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an electronic still camera in which an image signal from an image sensor is digitized and recorded on a recording medium such as a magnetic disk. This invention relates to a data compression circuit for reducing data loss.

[Summary of the invention]

In the present invention, in an electronic still camera that converts an image signal from an image sensor into a digital image signal and records it on a recording medium, during continuous shooting operation, the digital image signal is subjected to flex processing. By reducing the amount of data, it is possible to record data generated during continuous shooting in real time without deteriorating image quality.

[Conventional technology]

An image sensor such as a CCD converts the image of the subject into an image signal, digitizes this image signal, records it on a small diameter magnetic disk such as 2 inches, and reproduces the image signal on a monitor receiver. An electronic still camera has been proposed that allows viewing. The digital imaging signal is
It can be recorded on a magnetic disk in real time, or it can be taken into a frame memory and recorded at a lower data rate. Furthermore, when compressing the amount of data to enable recording in real time, two-dimensional processing within a frame or within a field is used. Since electronic still cameras record still images, two-dimensional processing has generally been adopted.

[Problem to be solved by the invention] When an electronic still camera performs rapid shooting, in which the shutter is operated multiple times in a short period of time to capture multiple images, a large amount of data is generated, so it is difficult to record it on a disk. Data compression is required. Two-dimensional data compression used for normal imaging operations (single shooting) takes into account prevention of deterioration in image quality of reproduced images, so the compression ratio is insufficient and it cannot be applied to continuous shooting operations. However, the above problem cannot be solved.

If the digital image signal is temporarily stored in a semiconductor memory, recording can be performed at a low speed, but the memory capacity becomes large enough to accommodate several frames, resulting in an increase in circuit scale.

Therefore, an object of the present invention is to record digital image signals in real time while maintaining good image quality by compressing data using interframe processing, which is three-dimensional processing, during continuous shooting. An object of the present invention is to provide a data compression circuit in an electronic still camera.

[Means to solve the problem]

The present invention provides an electronic still camera that converts an image signal from an image sensor into a digital image signal and records it on a recording medium. , which reduces the amount of data.

[Effect]

In a continuous shooting operation, the shutter operation is performed multiple times in a short period of time, so the background etc. are common between multiple screens, and even if there are multiple images, the static area occupies a large portion.

Therefore, inter-frame processing, which cannot be applied to normal photographing operations in which completely different images are obtained individually, is effective for a plurality of images obtained during continuous photographing operations. Through this interframe processing, it is possible to significantly compress the amount of data while suppressing deterioration in image quality, and it is possible to record multiple images in real time.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of this embodiment, where 1 is C
This is an image sensor consisting of an area sensor using a CD. An analog image signal from the image sensor 1 is supplied to an A/D converter 2 and converted into a digital image signal. A
A digital imaging signal from the /D converter 2 is supplied to a terminal a of the switch circuit 3.

The switch circuit 3 has terminals C, d-t", and the terminal C is connected to the terminal C of the switch circuit 4. The terminal C of the switch circuit 3 is supplied to the two-dimensional ADRC encoder 7, and the two-dimensional Data compressed by the ADRC encoder 7 is supplied to the terminal C of the switch circuit 4. Not limited to two-dimensional ADRC, compression circuits such as transform encoding, DPCM, etc. that perform two-dimensional processing within a frame or within a field can be used. The terminal d of the switch circuit 3 is supplied to the adaptive drop protection circuit 8, and the data compressed by the adaptive drop protection circuit 8 is supplied to the terminal d of the switch circuit 4.

The data taken out to the terminal a of the switch circuit 4 is supplied to the recording circuit 5, and a recording signal is obtained at the output terminal 6 of the recording circuit 5. This recording signal is supplied to the magnetic head via a recording amplifier (not shown) and recorded on the magnetic disk. The recording circuit 5 performs processing on the output signal of the switch circuit 4, such as adding an identification signal to identify it as an imaging signal for a continuous shooting operation, adding a synchronization signal, and channel modulation.

Switch circuits 3 and 4 are controlled by a control signal from terminal 9. The control signal is a signal corresponding to the photographing operation of the camera. When the camera is in normal shadow operation, that is, in single-shot operation, terminals a of switch circuits 3 and 4 are connected to terminals A, respectively. Therefore, A/
The digital image signal from the D converter 2 is supplied to the recording circuit 5 without being subjected to compression processing.

When the camera performs a continuous shooting operation, terminals a of switch circuits 3 and 4 are sequentially connected to terminals C and d. - For example, as shown in Figure 2, 5 times per second (e.g. 1 second)
In the snapshot operation in which imaging signals of frames (Fl, F2, F3, F4, F5) are obtained, the imaging signals of the first frame Fl are transferred to the two-dimensional AD via the terminal C of the switch circuit 3.
The signal is supplied to the RC encoder 7. Remaining 4 rams F2~
F5 is supplied to the adaptive dropout circuit 8 via the terminal d of the switch circuit 3 and subjected to three-dimensional processing.

The adaptive ablation circuit 8 configures a three-dimensional block consisting of two areas belonging to two frames, respectively, as will be described later.
The presence or absence of movement is determined for each 3D block, and if there is movement, coding (ADRC) that adapts to the dynamic range is performed for each 3D block, and if there is no movement,
2 by the average value of pixels at corresponding positions in the two areas.
It constitutes a dimensional block and performs two-dimensional ADRC. Therefore, adaptive deletion processing is performed on two frames F2 and F3 and two frames F4 and F5 during the continuous shooting operation.

In addition to adaptive deletion processing, interframe processing such as interframe prediction and motion compensation processing may also be used.Normally, when performing interframe processing, the quality of the first reproduced image is poor, so one Regarding the data of the eye frame F1, two-dimensional ADRC processing is performed as described above. This one
Regarding the first image, it is also possible to record it on the disk without data compression, as in the normal imaging operation.

During continuous shooting, images are taken in an extremely short period of time, so
Between the still images and the corresponding 5 frames Fl to F5,
Stationary parts such as the background occupy a large area of the image, and the amount of data can be significantly reduced by adaptive deletion processing.

Therefore, even if a large amount of data is generated in a short period of time due to continuous shooting, it can be recorded on the magnetic disk. In addition, since three-dimensional processing is performed on moving parts, high-quality reproduced images with little image deterioration can be obtained.

Although not shown, on the playback side, it is determined whether the signal is a quick-shot operation signal or a normal photographing signal based on an identification signal inserted in the recorded signal, and the signal is decoded based on this determination. Even if deletion processing has been performed, the original number of images will be restored by decoding.

An example of the adaptive ablation circuit 8 will be described below with reference to FIGS. 3 to 7. In this example, buffering processing is performed to prevent the amount of data in a two-frame period from exceeding a predetermined threshold and therefore recording not being possible in time.

In FIG. 3, a digital video signal in which one sample is quantized to 8 bits, for example, is supplied to an input terminal indicated by LL. This digital video signal is supplied to a blocking circuit 12. The blocking circuit 12 converts the digital image signal into data in a block order.

In the blocking circuit 12, for example, (520 lines x 72
As shown in Figure 4, one frame screen of (0 pixel) is (
MXN) blocks. One block consists of two areas each having a size of (4 lines x 4 pixels), as shown in FIG. 5, for example.

Each region belongs to two temporally consecutive frames.

As described above, frames F2 and F3 and frames F4 and F5 during the continuous shooting operation are two frames forming a three-dimensional block, respectively. Furthermore, when subsampling is performed in order to further increase the compression ratio, the sampling pattern has an offset between blocks as shown in FIG. In FIG. 6, O indicates a pixel that is transmitted, Δ indicates a pixel that is not transmitted, and in a spatially corresponding block two frames later, the transmitted and thinned out pixels have an inverse relationship.

Such a sampling pattern enables good interpolation in a still area when interpolating thinned out pixels on the receiving side. From the blocking circuit 12, B, , B, ,
B, . . . A digital video signal converted to the block order of BMH is generated.

The output signal of the blocking circuit 12 is supplied to a detection circuit 13 and a delay circuit 14. The detection circuit 13 detects the maximum value MAX3 and minimum value MIN3 of each block, and detects the dynamic range DR3 that is the difference between these values, and
Amount of movement in sample units of blocks, e.g. frame difference FD
Detect i.

The difference between the data of pixels at the same position between two areas constituting one block is determined, and this difference between each pixel is converted into an absolute value and set as a frame difference FDi. That is, if the data of the current frame is x, i and the data of the previous frame is X-1i, then the frame difference in sample units F D
＋! , t, FDi= x, i −XM−+ i
It is required as.

The frame difference FDi and dynamic range DR3 from the detection circuit 13 are supplied to the frequency distribution generation circuit 15.

This frequency distribution generating circuit 1-5 has a dynamic range D
With R3 (=MAX3-MIN3+1) as the vertical axis and the block movement amount N as the horizontal axis, the frequency of occurrence of each block is tallied over a period of two frames. The frequency distribution table formed in this manner is supplied to the cumulative frequency distribution generation circuit 16, and a cumulative frequency distribution table is formed.

Threshold determination circuit 17 uses an integrated frequency distribution table.
is the optimal threshold (threshold related to level Tl-74
and the motion threshold MT)I). The optimal threshold value means a threshold value that allows encoding to be performed so that the total number of bits per two frames does not exceed the transmission capacity of the transmission path.

This optimal threshold value is determined using the motion threshold value MTH as a parameter. In conjunction with the threshold determination circuit 17, R
OM1B is provided. This ROM 18 stores a program for determining an optimal threshold value.

The pixel data PD passed through the delay circuit 14 is supplied to a frame difference detection circuit 19. This frame difference detection circuit 1
9 detects the frame difference F in the same way as the detection circuit 13 described above.
Detect Di. The frame difference FDi and pixel data PD from the frame difference detection circuit 19 are supplied to the motion determination circuit 21. The motion determination circuit 21 compares the motion threshold MTH from the threshold determination circuit 17 with the frame difference FDi, and determines whether the block to be processed is a motion block.
Or determine whether it is a stationary block.

A block with the relationship (frame difference FDi>motion threshold MTH) is determined to be a motion block, and (frame difference FDi>motion threshold MTH) is determined to be a motion block.
A block satisfying the relationship Di≦motion threshold value MTH) is determined to be a stationary block. The pixel data of the moving block is supplied to the three-dimensional ADRCi encoder 22, and the pixel data of the still block is supplied to the averaging circuit 23. This averaging circuit 23 adds the data of pixels at the same position in two areas included in one block, converts t to %, and forms a block whose number of pixels is % of the original number of pixels in one block. This kind of processing is called drop-proof processing, and the output signal from the equalization circuit 23 is supplied to the two-dimensional ADRC encoder 24.

These encoders 22 and 24 are supplied with a threshold value Tl-T4 from a threshold value determination circuit 17.

The three-dimensional ADRC encoder 22 selects the maximum value MAX3. out of a total of 32 pixel data (4 lines x 4 pixels x 2 frames). The minimum value MIN3 is detected and (MAX3-M
Dynamic range DR3 due to IN3+1=DR3)
is required. From the relationship between the dynamic range D of this block and the threshold values T1 to T4, the code signal DT
The number of bits of 3 is determined. That is, in the block where (DR3≧TI), a 4-bit code signal is formed, and (TI>
In the block where DR3≧72), a 3-bit code signal is formed, and in the block where (T2>DR3≧T3), a 3-bit code signal is formed.
A 2-bit code signal is formed, and (T3>DR3≧T
In the block 4), a 1-bit code signal is formed, and in the block (T4>DR3), a 0-bit code signal is formed, that is,
Code signal is not transmitted.

For example, in the case of 4-bit quantization encoding, the detected dynamic range DR3 is divided into 16 (=24),
A 4-bit code signal DT3 is generated corresponding to the range to which the level of the data after removing the minimum value MIN3 of each pixel data belongs.

In the two-dimensional ADRC encoder 24, the three-dimensional AD
By the same operation as the RC encoder 22, the maximum value MA
X2. Minimum value MIN2. Dynamic range DR2 is detected and code signal DT2 is formed. However, what is to be encoded is data whose number of pixels has been set to % by the averaging circuit 23 at the previous stage.

The output signal of the three-dimensional ADRC encoder 22 (DR3, M
[N3. DT3) and the output signal (DR2, MIN2.D'r2) of the two-dimensional ADRC encoder 24 are output to the selector 25.
supplied to The selector 25 is controlled by a determination signal SJ from the motion determination circuit 21. That is, in the case of a motion block, the selector 25 selects the output signal of the three-dimensional ADRC encoder 22, and in the case of a still block, the selector 25 selects the output signal of the three-dimensional ADRC encoder 22.
The output signal of the dimensional ADRC encoder 24 is sent to the selector 25.
chooses. The output signal of this selector 25 is supplied to a framing circuit 26.

In addition to the output signal of the selector 25, the framing circuit 26 is supplied with a threshold code Pi specifying a threshold set and a determination code SJ. The threshold code Pi is 2
It changes on a frame-by-frame basis, and the judgment code SJ is
Changes in block units. The framing circuit 26 converts the input signal into frame-structured recording data. The framing circuit 26 performs error correction code encoding processing as necessary. Output terminal 2 of framing circuit 26
Output data is obtained at step 7. This output data is supplied to the terminal d of the switch circuit 4 (see FIG. 1).

FIG. 7 shows the configuration of an example of the three-dimensional ADRC encoder 22. In FIG. 7, 31 indicates an input terminal, and this input terminal 31 is connected to a maximum value detection circuit 32. A minimum value detection circuit 33 and a delay circuit 34 are connected. The maximum value MAX3 detected by the maximum value detection circuit 32 is the subtraction circuit 3.
5. The minimum value MIN3 detected by the minimum value detection circuit 33 is supplied to a subtraction circuit 35, and the output signal of this subtraction circuit 35 is supplied to a +1 addition circuit 37. +
A dynamic range DR3 expressed as (MAX3-MIN3+1) is obtained from the 1 addition circuit 37.

Pixel data passed through the delay circuit 34 is supplied to a subtraction circuit 36. The subtraction circuit 36 is supplied with the minimum value MIN3, and the pixel data P after the minimum value is removed from the subtraction circuit 36.
DI occurs. This pixel data PDI is transferred to the quantization circuit 4.
0. The dynamic range DR3 is taken out to the output terminal 41 and is also supplied to the ROM3B. The ROM 38 has a threshold value determination circuit 17 from a terminal 39.
The threshold code Pl generated in is supplied. This R.O.
From M3B, a bit number code Nb indicating the quantization step Δ and the number of bits is generated.

The quantization step Δ is supplied to the quantization circuit 40, and a code signal DT3 is formed from the minimum value removed data PDI and the quantization step Δ. This code signal DT3 is taken out to the output terminal 44.

The output signals generated at these output terminals 41, 42, 43, 44 are supplied to a framing circuit 26.

The bit number code Nb is determined by the framing circuit 26,
Used to select valid bits.

The formation of the code signal DT3 in the above-mentioned quantization circuit 40 will be explained. - In the case of encoding that allocates n bits to boat fishing, the level of the original data PD is expressed as Li, and the quantization code is expressed as Qi. The symbol [ ] means truncation.

Also, on the decoding side, if the restoration level is expressed as Li, then 1,...
i-(DR3/2″)X (Qi +0.5)+MI
N3=ΔX (Qi +0.5) +M I N 3
processing is performed.

The frame difference FDi is applied as the axis of the amount of movement in the frequency distribution table, and the frame difference FDi and dynamic range DR
A frequency distribution table with 3 as two axes is formed. This frequency distribution table is formed by assigning (+1) to portions of the table that are treated as stationary blocks and (+2) to portions of the table that are treated as moving blocks, as described in Japanese Patent Application No. 133924/1982. method of allocating or patent application 1986
A method of allocating the number of blocks occurring in one screen (two frame periods) can be used, as described in Japanese Patent No. 183,781. In reality, the frequency distribution table uses a memory, and the horizontal and vertical addresses of the memory are specified by N and DR3.

This frequency distribution table is generated by the cumulative frequency distribution generation circuit 16.
Converted to an integrated frequency distribution table. Threshold determination circuit 1
7, for the cumulative frequency distribution table, the motion threshold M
T) The amount of generated information is calculated by applying the threshold values T1 to T4 regarding I and the level. The determined amount of generated information is compared with a target value, and within a range where the amount of generated information does not exceed the target value, the motion threshold MTH and the threshold T1 are set.
~T4 is determined. The motion threshold value MT)I performs the deletion process, and the threshold values T1 to T4 are used by the ADRC encoders 22 and 24.

Note that the present invention is not limited to the above-described adaptive dropout prevention circuit, and interframe processing such as interframe prediction or a hybrid configuration in which different encoding is performed for a motion region and a still region may be used.

〔Effect of the invention〕

This invention has the advantage that it is possible to significantly compress the multiple images generated during the continuous shooting operation of an electronic still camera, making it possible to record these image data in real time and not requiring a large capacity memory. There is. In addition, in this invention,
Since the amount of data is reduced by interframe processing for a plurality of images that are characterized by many static areas, it is possible to maintain good image quality of the reproduced images.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a route diagram used to explain the quick-shooting operation, FIG. 3 is a block diagram showing an adaptive fall prevention circuit to which the present invention can be applied, and FIGS. 5 and 6 are route diagrams for explaining the block configuration, and FIG. 7 is a block diagram of an example of an ADRC encoder. Explanation of main symbols in the drawings 1: Image sensor, 3, 4: Switch circuit, 7: Two-dimensional AD
RC encoder. 8: Adaptive drop protection circuit. Figure 1 Agent Patent Attorney Tadashi Sugiura Figure 2 One-A-Song Pattern Figure 6

Claims (1)

[Claims] In an electronic still camera that converts an image signal from an image sensor into a digital image signal and records it on a recording medium, during continuous shooting operation, interframe processing is performed on the digital image signal. A data compression circuit for an electronic still camera, which is characterized by reducing the amount of data.