JPH023281A - Solid-state imaging device and its manufacture - Google Patents

Abstract

PURPOSE:To enable contact etching to be performed easily by reducing the film thicknesses of a gate electrode contact formation part and an insulating film part below the gate electrode than the film thickness of other parts of a light receiving part. CONSTITUTION:An n-diffusion layer 102, an insulating film 103, a gate insulating film 105, and a polysilicon film 106 are formed in order on an n<->-silicon layer 101 using a photolithography method, an ion implantation method, an etching method, and an oxidation method. Next, the polysilicon film 106 at an unnecessary part is removed, and source and drain n<+> diffusion layers 108, and an interlayer insulating film 109 are removed. The thickness of this insulation film 109 is 1000 to 3000Angstrom . After that, flow glass 110 is accumulated in the thickness of 6000Angstrom by the APCVD method, and after carrying out flowing 8, a contact hole 111 is formed using a photolithography method and a RIE method. At this time, since a gate electrode film 106 and an insulating film 103 below that are made thick, generation of the short-circuit between the gate and the substrate can be prevented effectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a solid-state imaging device using a light-receiving element having an MIS type light-receiving/accumulating section, and a method for manufacturing the same.

[Conventional technology]

Conventionally, various types of solid-state imaging devices are known that consist of a light-receiving element having a Mis-type light-receiving/accumulating section.
There is a solid-state imaging device that uses a light receiving element that has an MXS type light receiving and storage section and has an internal amplification function. As an example, the CMD (Charge
Modulation Device) There is an imaging device using a light receiving element, which is disclosed in Japanese Patent Application Laid-open No. 61-84059 and 1.
InternationalE held in 1986
lectron Device Meeting
“A NEW MOS IMAGE 5ENSOR” on pages 353-356 of the proceedings of (r EDM)
OPERAT1 layer G 1 layer A N0N-DESTRU
CTIVE R1! The content is disclosed in a paper titled ``ADOUT MODE''.

The planar structure of a pixel in a solid-state imaging device using such a CMD light-receiving element is shown in FIG. Figure tC
) shows a partially enlarged view of the sectional view shown in FIG. 9 (■).

In the figure, 1 is a p-substrate, 2 is an n-channel layer, 3 is an n0 source (drain) layer, 4 is an n' drain (source) layer, 5 is a gate insulating film, 6 is a gate polysilicon electrode, and 7 is a Protective film (passivation film) made of insulating material,
Reference numeral 8 designates a source electrode contact hole, 9 a gate electrode contact hole, 10 a connecting portion of each gate electrode of two adjacent pixels, and 11 an n diffusion layer for isolation between pixels.

Next, the light receiving operation of the CMD light receiving element having such a configuration will be explained. First, when light 12 enters the gate electrode 6 from above, the incident light 12 enters the protective film 7. Gate electrode6. It enters the channel layer 2 through the gate insulating film 5 and generates hole-electron pairs there. Of these, the photogenerated holes are transferred to the gate insulating film 5- directly below the gate electrode 6 to which a reverse bias is applied.
It accumulates at the interface of n-channel layer 2, resulting in an increase in surface potential. Thereby, the source layer 3 and the drain layer 4
The electron barrier to the intervening electrons is lowered, and an electron current flows through the n-channel layer 2. By reading this current, an amplified optical signal can be obtained.

[Problem to be solved by the invention]

By the way, in the solid-state imaging device configured in this way, the gate insulating film 5 has a thickness of 200 to 800 mm,
Further, the gate polysilicon electrode 6 has a thickness of 100 to 700 μm, and the protective film 7, which serves as an insulating film between the eyebrows, has a thickness of approximately 1 μm. In this structure, it is necessary to make a gate electrode contact hole 9, but as pixels have become increasingly finer in recent years, it has become essential to use selective ion etching (RIE) as the etching method. .

When making a hole with a depth of nearly 1 μm using this RIE method, over-etching is usually performed by about 20%.
Since both film thicknesses are thin, on the order of several hundred layers, if the etching end point is not carefully detected, both the polysilicon electrode 6 and the gate insulating film 5 will be etched, resulting in a gate-substrate short circuit and a defect. This was a drawback of the conventional method.

The present invention has been made to solve the above-mentioned problems of the prior art, and it is an object of the present invention to provide a structure and a manufacturing method for a solid-state imaging device that facilitates contact etching.

[Means and effects for solving the problem] In order to solve the above-mentioned problems, the present invention provides a solid-state imaging device using a light receiving element having an MIS type light receiving/accumulating part, in which the gate electrode part of the gate electrode contact forming part is or the thickness of the insulating film section below the gate electrode section is configured to be thicker than the gate electrode section of the light receiving section or the film thickness of the insulating film section of the light receiving section.

With this structure, even if the contact hole is over-etched when forming the gate electrode contact, the gate electrode film or insulating film underneath is formed thickly, so short circuits between the gate and the substrate can be effectively prevented. Therefore, the gate electrode contact forming process becomes extremely easy, and the yield can be improved.

〔Example〕

Examples will be described below. 1 to 1) are schematic sectional views showing a first embodiment of a solid-state imaging device according to the present invention and its manufacturing process.

In this first embodiment, the oxide film under the contact hole of the gate polysilicon electrode is formed thickly. In particular, the method for forming the thick oxide film is to oxidize the entire imaging surface thickly, and then form the gate contact. This method uses a wet or dry etching method to remove unnecessary oxide films, leaving only the oxide film below the surface.

Next, the specific manufacturing process and configuration will be explained. First, as shown in FIG.
form. The surface concentration of this n-diffused layer 102 is ~lX
An insulating film 103 is then formed on the surface of the n- silicon layer 101 using an oxidation method or the like.

The thickness is preferably 1,000 to 5,000 people. Thereafter, a resist 104 is formed using a photolithography method so as to surround the contact forming portion (the portion indicated by reference numeral 111 in FIG. 1). The process up to this point will result in the state shown to first nationals.

Next, the oxide film 103 is removed by wet or dry etching using the resist 104 as a mask.

Thereafter, a gate insulating film 105 is formed using an oxidation method. The thickness of this gate insulating film is in the range of 100 to 1000. A polysilicon film 106 that will later become a gate electrode
is formed to a thickness of ~2000 using the LPCVD method.
Next, the gate electrode portion is covered with a resist 107 using a photolithography method.

When this step is completed, the state shown in Figure 1 is reached.

Next, the unnecessary portions of the polysilicon film 1 are removed using the RIE method.
06 is removed, and then using ion implantation, the source,
A drain n3 diffusion layer 108 is formed.

For ion implantation, for example, ^S9 at 150 keV, 5
Then, the polysilicon film 106 is oxidized to form a glabella insulating film 109.
The thickness of 9 is 1000-3000 people. When this process is completed, the state shown in FIG. 1 (C1) is reached.

After that, flow glass 110 is applied to ~6 by APCVD method.
After depositing with a thickness of 000 and performing flow glass,
Contact hole 111 is formed by photolithography method, RIE
Then, the aluminum electrode 112 is formed. This completes the process, and a solid-state imaging device having the configuration shown in ) in FIG. 1 is obtained.

In this embodiment, since the imaged area is uniformly oxidized to form an oxide film, even if the insulating film 103 is finally disposed so as to be partially thick, there are fewer defects, and therefore, the imaged area is formed with less defects. It has the advantage of reducing noise. Furthermore, the gate capacitance is smaller than that of the conventional example, which is more advantageous than the conventional example in terms of high-speed single-image operation.

Next, a second embodiment of the present invention will be described based on FIGS. This second embodiment also has a thick oxide film under the contact hole of the gate polysilicon electrode.
In particular, as a method for forming the thick oxide film, a selective oxidation method is used in which only the oxide film under the gate contact formation portion is oxidized thickly.

Next, the specific manufacturing process and configuration will be explained. First, as shown in the second example, the n-silicon layer 201 is oxidized to form a protect oxide film 202.

The thickness of this oxide film 202 is 500 mm. After that, S
The iS N4 film 203 is formed using the LPCVD method.
A resist 204 is applied, a window 206 is formed in a portion where an n-type diffusion layer 205 for isolation between pixels is to be formed using a photolithography method, and a window 206 is formed using an RIE method. 206 S i s
The Na film 203 is etched and an n-type diffusion layer 205 is formed using ion implantation. Once this process is complete, it will be in a state that can be shown to second nationals.

Next, the resist film 204 is removed and oxidized to form a thick insulating film 207. The thickness is preferably about 4000 to 8000. Gate oxidation is performed to form the gate insulating film 208, and the polysilicon film 208, which is the gate electrode material, is
Deposit 9 ~2000 people. Thereafter, the gate electrode portion is covered with a resist 210 using a photolithography method. When this process is completed, the state shown in FIG. 2 is obtained.

After that, using the RIE method, unnecessary parts of the polysilicon film 2 are removed.
09 is removed, and then the source and drain n9 are diffused r! using ion implantation. 211 is formed. Then, the polysilicon film 209 is oxidized to form a glabellar insulating film 212. When this process is completed, the state shown in FIG. 2 C1 is reached.

After that, flow glass 213 is deposited by APCVD method, and after a flowing process, contact holes 213 are deposited.
is formed using a photolithography method and an RIE method,
After that, an aluminum electrode 215 is formed. This completes the process, and a solid-state imaging device having the structure shown in ) in FIG. 2 is obtained.

In this embodiment, MOSFETs constituting the peripheral circuit
When integrally formed on the same semiconductor substrate, MOSFE
The selective oxidation process of the T part and the selective oxidation process of the light receiving element part can be combined, and as a result, the number of mask processes is reduced by one, and the alignment accuracy is improved. Furthermore, the gate capacitance is smaller than that of the conventional example, and high-speed single-image operation is possible. Furthermore, the S i 3 Na film 203 can be used as a gate insulating film in some cases, and has various advantages such as being able to easily form a gate insulating film having high light transmittance, which is advantageous for increasing sensitivity.

Next, a third embodiment of the present invention will be described based on FIGS. 3(8) to 3). In this third embodiment, the thickness of the polysilicon film in the contact forming part of the gate polysilicon electrode is made thicker than in other parts, and in particular, the thick polysilicon film and the thin polysilicon film are formed into one layer. It is characterized by the fact that it is formed from a polysilicon film, and that both polysilicon films are made thinner in subsequent steps such as oxidation.

The specific manufacturing process and configuration will be described below. First, as shown in the third country, an n-type diffusion layer 302 for isolation between pixels is formed in the n-silicon layer 301 by sequentially using photolithography and ion implantation.
Thereafter, a gray-colored frame film 303 is formed using an oxidation method or the like. Next, a polysilicon electrode 304 that will become a gate electrode is formed using the LPCVD method, about 5,000 Ac, and a photolithography method to form a resist film 305 on the gate electrode portion, using the acid resist film 305 as a mask. , Unnecessary portions are removed by etching using the RIE method.

Once this process is complete, it will be ready to be shown to third country nationals.

Thereafter, the polysilicon electrode 304 other than the light receiving portion is covered with a resist 306 using a photolithography method. Then, using RIE or wet etching method, a polysilicon electrode 304 which will become a light receiving part is etched by 30mm.
Etching 00-4000 people. When this process is completed, the state shown in FIG. 3 [B] is reached.

Next, using the polysilicon electrode 304 as a mask, an ion implantation method is used to form a source/drain n'' diffusion layer 307, and then the polysilicon electrode 304 is oxidized to form a glabella insulating film 308. This step is completed. and Figure 3 (C
The state shown in 1 is reached.

Thereafter, a flow glass 309 is deposited by APCVD, and after a flowing process is performed, a contact hole 310 is formed by sequentially performing photolithography and RIE, and then a gate lead-out electrode 311 is formed. This completes the process, and a solid-state imaging device having the structure shown in FIG. 3 (DJ) is obtained.

In this example, there is no limit to the thickness of the contact forming portion of the light receiving element and the polysilicon forming the MOSFET, and therefore the resistance of the gate electrode can be significantly lowered and the time constant CR can be increased. This reduces the decrease in response speed due to this, and enables high-speed driving.

Furthermore, the thickness of the polysilicon gate electrode in the light receiving section can be made very thin, which is advantageous for increasing the intensity. Further, the process is almost the same as the conventional process, and has the advantage of being highly applicable to the process.

Next, a fourth embodiment of the present invention will be described based on FIGS. This fourth embodiment also has gate polysilicon tIl.
! The thickness of the polysilicon film in the contact forming part of j is made thicker than other parts, and in particular, the thick polysilicon film and thin polysilicon film are formed from one layer of polysilicon film, and then, This method is characterized in that the polysilicon film is covered with a Si3N film so that the polysilicon film is not oxidized, so that the thickness of the polysilicon film does not change.

Next, the specific manufacturing process and configuration will be explained. First, as shown in the fourth countryman, in the n-silicon layer 401,
By sequentially using a photolithography method and an ion implantation method, an n-type diffusion layer 40 for isolation between pixels is formed.
After that, a gate insulating film 403 is formed by an oxidation method or the like. Next, a polysilicon film 404 that will become the gate electrode is formed to a thickness of 2000 nm using the LPCVD method, and a resist film 404 is formed on the polysilicon film 404 other than the gate electrode light-receiving area using the photolithography method.
5 is formed, and using the resist film 405 as a mask, RI is performed.
The light-receiving portion polysilicon film 404 is etched to a thickness of 300 to 600 mm using the E method or the weight etching method. Once this process is complete, it will be in a state that can be shown to people from a fourth country.

Next, the polysilicon film 404 is oxidized to
A film 406 is formed by oxidizing about 300 layers, and then LPCVD is performed.
According to the law, 700 people or 1
650 people will be deposited. Then, by photolithography, a resist film 40 is formed on the position that will become the gate electrode.
Form B. When this step is completed, the state shown in the 4th part) will be reached.

After that, using the RIE method, unnecessary parts of the 5ilN4 film 4 are removed.
07. The oxide film 111406 and the polysilicon film 404 are sequentially etched and removed. Next, an oxide film 410 for polysilicon interlayer insulation is formed, and a Si3N film 407 is formed.
An n3 source drain diffusion layer 409 is formed by ion implantation using as a mask. Once this process is finished, the fourth
The state shown in Figure (C) is reached.

Next, a flow glass 411 is deposited by the APCVD method, and after a flowing process is performed, a contact hole 412 is formed by sequentially performing a photolithography method and an RIE method, and then a gate lead-out tFj 413 is formed. This completes the process, and a solid-state imaging device having the structure shown in FIG. 4fDl is obtained.

In this embodiment, as in the third embodiment, there is no restriction on the thickness of the gate polysilicon film in the contact forming portion and the MOSFET portion, which is advantageous for high-speed driving of the device. Furthermore, the polysilicon film thickness of the light receiving section can be made very thin, which is advantageous for high sensitivity. In addition, the film thickness of the gate polysilicon electrode remains unchanged after the deposition of the 5isNa film, which allows better control of the film thickness. , has various advantages such as being advantageous for increasing sensitivity.

Next, a fifth embodiment of the present invention will be described based on items 58 to (2). In this fifth embodiment as well, the thickness of the polysilicon film in the contact forming part of the gate polysilicon electrode is made thicker than in other parts, and in particular, the thick polysilicon film and the thin polysilicon film are formed into one layer. A MOS F is formed from a polysilicon film, and then a polysilicon film for a gate contact forming part and a peripheral circuit are formed.
The upper part of the polysilicon of the ET is covered with a Si 3 Na film so that the thickness of these polysilicon films does not change in the subsequent process, and on the other hand, the polysilicon film thickness of the light receiving part is made thinner in the later oxidation process. It is characterized by the following points.

Next, the specific manufacturing process and configuration will be explained. First, as shown in the fifth prisoner, in the n-silicon layer 501,
By sequentially using a photolithography method and an ion implantation method, an n-type diffusion layer 50 for isolation between pixels is formed.
2 and then gate insulation II! 503 is formed by an oxidation method or the like. Next, a polysilicon film 504 of 2000 layers, a thin oxide film 505 of 100 to 300 layers,
~1000 people (7) A Si S N 4 film 506 is formed using an LPCVD method, a thermal oxidation method, and an LPCVD method, and a resist 507 is formed using a photolithography method at a location that is to become a gate electrode. Then, by using the resist 507 as a mask and using the RrE method, unnecessary 5riNa film 506 oxide film 505. Polysilicon film 504 is removed. Once this process is complete, the state shown for the fifth prisoner will be reached.

Next, the gate electrode portions other than the gate electrode portion of the light receiving portion are covered with a resist 508 by photolithography, and the 5i3Na film 506 of the light receiving portion is etched using the RIE method. When this step is completed, the state shown in FIG. 5 [Bl] is reached.

After that, insulation oxidation IJ between the eyebrows! 5 (19) is formed by thermal oxidation, and then, using the gate electrode as a mask, an n4 source and drain diffusion layer 510 is formed by ion implantation.

When this process is completed, the state shown in Figure 5 (mouth) will be achieved.

After that, a flow glass 511 is deposited by the APCVD method, and after a flowing process is performed, the contact hole 511 is
is formed by sequentially using a photolithography method and an RIE method, and then a gate lead electrode 513 is formed. This completes the process, and a solid-state imaging device having the structure shown in ) in FIG. 5 is obtained.

In this embodiment, the contact forming portion and the MOS
The thickness of the gate polysilicon film in the FET section can be increased, which is advantageous for high-speed operation of the device. Furthermore, the polysilicon film thickness of the light receiving portion can be made thinner, which is advantageous for increasing sensitivity. Further, since the light-receiving portion polysilicon film is thinned by an oxidation method, there are various advantages such as good film thickness uniformity and less variation in in-plane sensitivity.

Next, a sixth embodiment of the present invention will be described based on FIGS. In this sixth embodiment, the polysilicon film in the contact forming portion of the gate polysilicon electrode is made thicker than other parts, and in particular, the thick polysilicon film and the thin polysilicon film are made of one layer of polysilicon. By lowering the n-type impurity concentration in the part where the gate contact is formed, the polysilicon film loss due to thermal oxidation after the polysilicon film formation process is reduced only in the contact forming part. This is a characteristic feature.

Next, the specific manufacturing process and configuration will be explained. First, as shown in the 6th countryman, an n-type diffusion layer 602 for pixel isolation is formed in an n-silicon layer 601 by sequentially using photolithography and ion implantation, and then a gate insulating film 603 is formed. 0 formed using oxidation method etc.
Next, a polysilicon film 604 is deposited for 20 minutes using the LPCVD method.
Approximately 00 people will be formed.

Next, a resist film 605 is formed on the portion where the gate contact is to be formed by photolithography, and using this resist film 605 as a mask, the polysilicon film 604 is doped with phosphorus 31pl by ion implantation. 1XIQ with acceleration energy of 70 kaV
em-” impurity is implanted. After this step, the sixth
It will be in a state shown to the doujinshi.

After removing the resist film 605, the entire surface of the polysilicon film 604 is thinly doped with phosphorus using an ion implantation method, for example, with an acceleration energy of 70 keV.
C111-" impurity is implanted. Then, by heat treatment, the polysilicon film 604 is implanted in the vertical direction (perpendicular to the substrate).
phosphorus, an impurity, is uniformly diffused into the water.

Next, a resist pattern 606 is formed in a portion that will become a gate electrode using a photolithography method.

Then, unnecessary polysilicon film 604 is etched and removed by RIE method. After this process is completed, the 6th release)
The state shown in is reached.

Next, an ion implantation method is used to form the n source/drain diffusion layer 6.
By forming 07 and then performing polysilicon oxidation, the oxide film 608 in the polysilicon film of the light receiving part doped with phosphorus becomes thick (as a result, the n
The 9-polysilicon film 604a is thinner than the n-polysilicon film 604b in the contact forming portion. If 900° C. wet oxidation is used, the thickness of the light-receiving portion will be approximately 500 mm, and the thickness of the contact forming portion will be approximately 1,200 mm. When this step is completed, the state shown in FIG. 6(C) is reached.

After that, a flow glass 611 is deposited by the APCVD method, and after a flowing process, a contact glass 611 is deposited.
is formed by sequentially performing photolithography and RIE, and then the pole 613 of A1 is formed. This completes the process, and a solid-state imaging device having the structure shown in ) in FIG. 6 is obtained.

This embodiment has the feature that a structure in which the polysilicon film in the contact forming portion is thick can be easily formed by using normal steps by only increasing the number of mask steps by I.

Next, a seventh embodiment of the present invention will be described based on FIGS. In this seventh embodiment as well, the polysilicon film thickness in the contact forming portion of the gate polysilicon electrode is made thicker than in other parts. The method is characterized in that a thin polysilicon film is first formed, and then a thick polysilicon film is formed.

Next, the specific manufacturing process and configuration will be explained. First, as shown in FIG. 7, an n-type diffusion layer 702 for pixel isolation is formed in an n-silicon layer 701 by sequentially using photolithography and ion implantation, and then a gate insulating film 703 is formed. is formed using an oxidation method or the like.

After that, the polysilicon film 704 is formed by the LPCV[) method.
After the n-type impurity is diffused to the solid solution limit, an oxide film 705 having a thickness of about 100 mm or more is formed using an oxidation method.

Next, using a photolithography method, resist 7 is applied to the part that will become the gate electrode except for the part where the gate contact is to be formed.
06 to form a pattern. After that, wet etching is performed to form a thin oxide film 70 using the resist 706 as a mask.
Remove 5. Thereafter, an n° source and drain diffusion layer 707 is formed using an ion implantation method. When this step is completed, the state shown in the seventh diagram is reached.

Next, LP 5000 thick polysilicon 1JW708
A resist pattern 709 is formed on the entire surface of the wafer using the CVD method, and a resist pattern 709 is formed on the polysilicon film 708 in the contact forming portion using the photolithography method. Then, the thick polysilicon film 708 is etched using the RIE method. At this time, the resist pattern 709 and the thin oxide film 705 serve as an etching mask, so when the RIE process is completed, the state shown in FIG. 7 (upper) is obtained.

Thereafter, a polysilicon interlayer insulating film 710 is formed by a thermal oxidation process to obtain the state shown in FIG. After that, the AI electrode 713 is formed by sequentially using the method and the RYE method.The process is thus completed, and a solid-state imaging device having the structure shown in FIG. 7 (2) is obtained.

In this example, since the thin polysilicon film and the thick polysilicon film are formed separately, the thickness of each polysilicon film can be easily controlled, and as a result, the process is advantageous for high sensitivity and high speed drive. It has the following characteristics.

Next, an eighth embodiment of the present invention will be described based on FIGS. In this eighth embodiment, the polysilicon film in the contact formation part of the gate polysilicon electrode is made thicker than in other parts, and in particular, the thick polysilicon film and the thin polysilicon film are made of two layers of polysilicon. It is characterized in that it is formed of a film, and its formation order is that a thick polysilicon film is first formed, and then a thin polysilicon film is formed.

Next, the specific manufacturing process and configuration will be explained. First, as shown in the 8th figure, an n-type diffusion layer 802 for pixel isolation is formed in the 0 to 9937 layer 801 by sequentially using photolithography and ion implantation, and then a gate insulating film 803 is formed. Formed using an oxidation method or the like.

After that, a thick polysilicon film 804 is formed by the LPCVD method, and the polysilicon film 804 is formed in the gate contact formation area.
04 and a resist pattern 805 is formed on the gate electrode part of the peripheral MOSFET part, and an unnecessary polysilicon film 804.04 is formed by RIE method. Oxide film 803 is removed. When this process is completed, the state shown in Figure 8 is reached.

Thereafter, gate oxidation is performed again to simultaneously form a gate oxide film 806 and a polysilicon interlayer insulating film 807. Next, a thin polysilicon ll! is produced using the LPCVD method. 8
Deposit 08. Then, a resist pattern 809 is formed using a photolithography method in a portion that is to become a light receiving portion and a contact portion.

When the process progresses to this point, the state shown in FIG. 8 (Bl) is reached.

Next, the thin polysilicon film 808 is removed using the RIE method using the resist pattern 809 as a mask, and the n9 source/drain diffusion layer 810 is formed using the ion implantation method using the resist pattern 809 as a mask. Thereafter, the resist pattern 809 is removed, and a glabellar oxide film 811 is formed by an oxidation method, resulting in the state shown in FIG. 8C+.

Thereafter, a flow glass 812 is deposited by the APCVD method, and after a flowing process is performed, a contact hole 813 is formed by sequentially performing a photolithography method and an RIE method, and then a gate extraction electrode 814 is formed. This completes the process, and a solid-state imaging device having the structure shown in ) in FIG. 8 is obtained.

In addition to the same effects as the seventh embodiment, this embodiment has a feature that the oxide film thickness of the MOSFET section and the oxide film thickness of the light receiving section can be individually optimized.

〔Effect of the invention〕

As explained above based on the embodiments, according to the present invention, the thickness of the gate electrode or the oxide film thereunder in the contact forming part is made thicker than in other parts, so even if the contact hole is formed, there is Even if etching is performed, the occurrence of gate-substrate short circuits can be effectively prevented.

This greatly simplifies the contact formation process in the manufacturing process of light receiving elements in solid-state imaging systems that use light receiving elements with MIS-type light receiving and accumulating sections such as CMDs, and reduces the yield rate of imaging systems due to poor contact. Advantages such as being able to prevent deterioration and greatly contributing to process standardization can be obtained.

[Brief explanation of the drawing]

Figures 1 to 1) are schematic sectional views showing the manufacturing process and final configuration of the first embodiment of the solid-state imaging device and its manufacturing method according to the present invention, and Figures 2 to 2) show the second embodiment. 3 (D) is a schematic sectional view showing the third embodiment, FIG. 4 (D) is a schematic sectional view showing the fourth embodiment,
IDI to FIG. 5 is a schematic sectional view showing the fifth embodiment, FIG. 6 to IDI) is a schematic sectional view showing the sixth embodiment, and FIG. A schematic cross-sectional view showing the embodiment, Figure 8~■) is a schematic cross-sectional view showing the eighth embodiment, and Figure 9 shows the planar structure of a pixel of a solid-state imaging device using a conventional CMD light-receiving element. 9 (Bl is a cross-sectional view taken along the line A-A', and FIG. 9(C) is a partially enlarged view of FIG. 9 (Bl). In the figure, 101 is n- A silicon layer, 102 is an n-diffused layer for isolation between pixels, 103 is an insulating film, 105
106 is a gate insulating film, 106 is a polysilicon film, 10B is a source and drain n° diffusion layer, 109 is an insulating film between eyebrows, 110
111 indicates a flow glass, 111 a contact hole, and 112 an aluminum electrode. Patent applicant: Olympus Optical Industry Co., Ltd. Figure 2 Figure 1 (A) Figure 3 (C) 308 ZetsuR Exhibition Figure 4 Figure 5 Figure 7 Figure 8

Claims (1)

[Scope of Claims] 1. In a solid-state imaging device using a light-receiving element having an MIS type light-receiving/storage section, the film thickness of the gate electrode portion of the gate electrode contact forming portion or the insulating film portion under the gate electrode portion A solid-state imaging device characterized in that the thickness of the film is thicker than the thickness of a gate electrode portion of a light receiving portion or the thickness of an insulating film portion of a light receiving portion. 2. The solid-state imaging device according to claim 1, wherein the gate electrode portion of the gate electrode contact forming portion and the gate electrode portion of the light receiving portion are formed of a single layer of electrode film. 3. The gate electrode portion of the light receiving portion is formed of a first electrode film, and the gate electrode portion of the gate electrode contact forming portion is formed of the first electrode film and a second electrode film stacked on the electrode film. 2. The solid-state imaging device according to claim 1, further comprising: a solid-state imaging device; 4. In a method for manufacturing a solid-state imaging device using a light-receiving element having an MIS type light-receiving/storage section, a thick oxide film is formed over the entire surface of the semiconductor, and the oxide film is removed from the area where the gate electrode contact is formed. A method for manufacturing a solid-state imaging device, comprising forming an insulating film thicker in an electrode contact forming part than in other parts. 5. A method for manufacturing a solid-state imaging device using a light-receiving element having an MIS-type light-receiving/storage section, characterized in that an insulating film thicker than other parts is formed in a gate electrode contact forming part by a selective oxidation method. A method for manufacturing an imaging device. 6. In a method for manufacturing a solid-state imaging device using a light-receiving element having an MIS-type light-receiving/storage section, the gate electrode is formed with a single layer of electrode film, and the film thickness of the electrode film of the light-receiving section other than the gate electrode contact forming part is A method for manufacturing a solid-state imaging device, characterized in that the electrode film in a gate electrode contact forming portion is formed thickly by reducing it by etching. 7. Manufacturing the solid-state imaging device according to claim 6, characterized in that a post-process is used to reduce the thickness of each of the electrode films of the gate electrode contact forming part and the electrode films of the other light-receiving parts. Method. 8. Manufacturing the solid-state imaging device according to claim 6, characterized in that a post-process is used for the electrode film of the gate electrode contact forming portion and the electrode film of the other light-receiving portions in which the respective film thicknesses thereof are not changed. Method. 9. In a method for manufacturing a solid-state imaging device using a light-receiving element having an MIS-type light-receiving/accumulating section, the gate electrode is formed with a single layer of polysilicon electrode film, and an oxide film is formed on the electrode film of the light-receiving section by oxidation treatment. 1. A method of manufacturing a solid-state imaging device, characterized in that the thickness of only an electrode film of a light receiving part is reduced by forming a light receiving part. 10. In a method for manufacturing a solid-state imaging device using a light-receiving element having an MIS-type light-receiving/storage section, the gate electrode is formed of a single layer of polysilicon electrode film, and in each electrode film of the gate electrode contact forming part and the light-receiving part. By changing the impurity concentration of
Manufacture of a solid-state imaging device characterized by forming an oxide film thicker than the contact forming part on the electrode film of the light receiving part by oxidation treatment, and forming the electrode film of the light receiving part thinner than the electrode film of the contact forming part. Method. 11. In a method for manufacturing a solid-state imaging device using a light receiving element having an MIS type light receiving/accumulating section, a first thin electrode film is formed on the gate insulating film, then a second thick electrode film is deposited, and then light receiving is performed. A method of manufacturing a solid-state imaging device, characterized in that a thick electrode film in a portion is removed and a gate electrode is formed using two layers of electrode films having different thicknesses. 12. In a method for manufacturing a solid-state imaging device using a light receiving element having an MIS type light receiving/accumulating section, a thick electrode film is formed on the gate insulating film in the gate electrode contact forming portion, and then a thick electrode film is formed on the thick electrode film and the gate electrode. 1. A method of manufacturing a solid-state imaging device, comprising depositing a thin electrode film on a portion where a light receiving portion is to be formed to form a gate electrode.