JPH0232485A - Plotting control system - Google Patents

Abstract

PURPOSE:To improve a plotting speed by providing a barrel shifter and rotating the input/output data of a picture memory according to a bit offset value. CONSTITUTION:A plotting control processor 10 sets an offset value N to a register 20 before plotting one word picture data. At the time of plotting, an address outputted by the processor 10 addresses a bit width W outputted by the register 20 to memories 30-37 together with a bit offset value (n). The memories 30-37 store the value of an expression I formed with an address width W and offset numbers N and (n). The value of the expression I is the address value of the memory having a 1-bit data width corresponding to the 2<x>-th order of the data of the processor 10 with the offset value (n) as 0. Further, the input/ output data of picture memories 40-47 corresponding to the data to address the memories 30-37 are rotated by a barrel shifter 50. Thus, the plotting can be done with one-time memory access, and at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a drawing control method when drawing image data to an image memory in an image display device using a rask scan method.

[Conventional technology]

The image memory in an image display device using the Rask scan method is generally configured in units of words, and usually one
Drawing is performed by making word image data correspond to word boundaries in the image memory.

In this case, it may be necessary to draw one word of image data across the word boundary of the image memory.

In this way, in order to draw across the word boundary of the image memory, the conventional method is to shift the image data by a bit offset and draw on both sides of the word boundary in a time-sharing manner. It is used.

[Problem to be solved by the invention]

When drawing one word of image data across the word boundary of the image memory, as in the conventional drawing control method described above, the image data is shifted by the bit offset and time-divided on both sides of the word boundary. If drawing is performed using 1 word, there is a problem that one word of image data cannot be drawn in one memory access, and the drawing execution speed becomes slow.

[Purpose of the invention]

The present invention aims to solve the problems of the prior art, and is capable of drawing one word of image data across the word boundary of the image memory in one memory access. The objective is to provide a drawing control method that can improve the drawing execution speed.

[Means to solve the problem]

As shown in the embodiment of FIG. 1, the drawing control method of the present invention provides a drawing control processor 10 with an address space of 2N bits x 2'' words, and an N-bit address space for storing a bit offset value. A register 20 and 2'4 memories 40 to 47 each having a data width of 1 bit, which are image memories.
2' rotates the input/output data of memories 40 to 47 with a data width of 1 bit according to the bit offset value.
In order to address the 4-bit barrel shifter 50 and the 1-bit data width memo 1 40 to 47, the W-bit word address of the drawing control processor 10 and the N-bit bit offset of the register 20 are used (W+N
) data width 1 corresponding to the 2X position of the data of the drawing control processor when the bit offset value is O, that is, when rotation is not performed in the barrel shifter 50.
The memory address of the bit is determined by the drawing control processor 10.
address W and bit offset value n of register 20
W-bit memories 30 to 37 are provided for each.

[Embodiments of the invention]

FIG. 1 is a schematic block diagram showing one embodiment of the present invention, and illustrates an 8-bit drawing processor having an address space of 23 bits x 216 words. That is, in FIG. 1, N=3. W
=16 is shown. Drawing control processor 10
Before drawing 1-word image data consisting of 8 bits, a desired bit offset value n is set in the register 20 consisting of 3 bits.

In the read cycle and write cycle during drawing, the 16-bit address output by the drawing control processor 10 is sent to the memories 30 to 37 as a 19-bit bit address along with the 3-bit bit offset output by the register 20. addressing.

Memories 30 to 37 each have 216 bits x 219
The memory 3X, which is composed of words and addresses the image memory 4X corresponding to the 2X digit of the data of the drawing control processor 10 when the bit offset is 0, contains the address value W of the drawing control processor 10 and the bits of the register 20. For the offset value n, 0 to 47 are addressed by the value shown by the formula 0.

If x=7, then the address of the image memory 47 is always the same as the address of the drawing control processor 0. To simplify the explanation, it is assumed that the memory 37 is present.

FIG. 2 shows addressing to image memories 40-47 in the case of bit offset n=3.

Furthermore, in this case, the positioning of the input/output data of the image memories 40 to 47 is shifted by the bit offset with respect to the positioning of the data of the drawing control processor 10, so the barrel shifter 50 rotates the data by the bit offset. do.

FIG. 3 shows the rotation by the bit offset in the barrel shifter 50 when n=3.

Note that the data in the memories 30 to 37 described above are generally obtained as follows.

Memories 30 to 37 store 8-bit data from 2° to 27°.
The values of X are X=0 to x=7, respectively. Further, in the example of FIG. 1, N=3 and W=6. Therefore, INT ((n+2W-x-1
)/2N) is as shown in FIG. 4, corresponding to the bit offset value n=o to 7. Here, INT [] is []
It shows only the integer part of the value within.

That is, the address value W output by the drawing control processor 10 plus the value shown in FIG.
7 address values.

When the bit offset value n=3 as shown in FIG. 2, the addresses for the image memories 40-47 are as follows.

Address rw+1 given to memories 40 to 42” memory 4
Address "W" given to image memories 40-47 According to the drawing control method shown in this embodiment, bit addressing can be performed from the drawing control processor 10 to the image memories 40-47 in this way.

〔Effect of the invention〕

As explained above, according to the drawing control method of the present invention, when addressing is performed using the word address of the drawing control processor and the bit offset set in the register, indirect processing is performed via the memory storing the address value of the image memory. Since bit addressing is realized by addressing the image memory and rotating the input/output data of the image memory using a barrel shifter according to the bit offset value, there is no word boundary of the image memory. (Thus, one word of image data can be drawn in one memory access, and it is possible to provide an unprecedented and excellent image control method that can improve the drawing execution speed.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of an embodiment of the present invention, FIG. 2 is a diagram showing addressing to the image memory when n=3 in the first embodiment, and FIG. 3 is an implementation of the embodiment of FIG. In the example, FIG. 4 is a diagram showing the rotation in the barrel shifter when n=3, and FIG. 4 is a diagram showing the value to be added to the address value of the drawing control processor. 10... Drawing control processor, 20...
・Registers, 30-37...Memory, 40-4
7... Image memory, 50... Barrel shifter. First patent applicant: Japan Electric Co., Ltd.
Figure 3 (Figure 8P and Pigeon name /%, 1) and Shifter with 1 Teru Knight) Embarrassing Pregnancy 95th Figure 4

Claims (1)

[Claims] (1) For a drawing control processor having an address space of 2^N bits x 2^W words, an N-bit register that stores a bit offset value;
2^N memories with a data width of W bits, which are addressed by a (W+N) bit bit address based on a word address of W bits of the drawing control processor and an N bit offset of the register; and a memory with the data width bits. 2^N memories each having a data width of 1 bit, which are addressed by W bits of data; and a 2^N bit barrel shifter 50 which rotates the input/output data of the memories having a data width of 1 bit according to the bit offset value. and when the bit offset value n is set to 0, the stored data of the data width W bits, which is the address of the memory of the data width 1 bit corresponding to the 2^x position of the data of the drawing control processor, is stored in the drawing control processor. A drawing control method characterized in that W+INT ((n+2^N-x-1)/2^N) for an address W of a control processor and a bit offset value n of the register.