JPH0231446A - Manufacture of semicodnuctor device - Google Patents
Manufacture of semicodnuctor deviceInfo
- Publication number
- JPH0231446A JPH0231446A JP18220788A JP18220788A JPH0231446A JP H0231446 A JPH0231446 A JP H0231446A JP 18220788 A JP18220788 A JP 18220788A JP 18220788 A JP18220788 A JP 18220788A JP H0231446 A JPH0231446 A JP H0231446A
- Authority
- JP
- Japan
- Prior art keywords
- film
- protrusion
- wiring
- contact
- polycrystalline silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title description 9
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 238000005530 etching Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 18
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 8
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 8
- 239000005380 borophosphosilicate glass Substances 0.000 abstract description 7
- 238000000034 method Methods 0.000 abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052782 aluminium Inorganic materials 0.000 abstract description 6
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 5
- 238000010438 heat treatment Methods 0.000 abstract description 3
- GDFCWFBWQUEQIJ-UHFFFAOYSA-N [B].[P] Chemical compound [B].[P] GDFCWFBWQUEQIJ-UHFFFAOYSA-N 0.000 abstract description 2
- 239000011521 glass Substances 0.000 abstract description 2
- 229920001721 polyimide Polymers 0.000 description 3
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 210000004709 eyebrow Anatomy 0.000 description 2
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関し、特に多層配線構
造を有する半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device having a multilayer wiring structure.
従来、多層配線間のコンタクトをとる方法としては、眉
間絶縁膜にコンタクトホールを形成し、その上に上層配
線を形成する方法を行なっていた。Conventionally, as a method for making contact between multilayer interconnections, a method has been used in which a contact hole is formed in an insulating film between the eyebrows and an upper layer interconnection is formed thereon.
第３図（ａ）〜（ｃ）は従来の半導体装置の製造方法の
一例を説明するための工程順に示した半導体チップの断
面図である。第３図（ａ）に示すように、半導体基板等
の上に設けられた酸化シリコン膜１上に、下層配線とし
ての多結晶シリコン膜２を形成する。次に、眉間絶縁膜
としての酸化シリコン膜７を形成した後、コンタクトホ
ールを形成するためのホトレジスト膜３を塗布し、露光
、現像を行なう。次に、第３図（ｂ）に示すように、異
方性エツチングにより、酸化シリコン膜２にコンタクト
ホールを形成し、ホトレジスト膜３を除去する０次に、
第３図（Ｃ）に示すように、コンタクトホール及び酸化
シリコン膜７上に上層配線としてのアルミニウム配線５
を形成し、多層配線構造を有した半導体装置を形成して
いた。FIGS. 3(a) to 3(c) are cross-sectional views of a semiconductor chip shown in order of steps to explain an example of a conventional method for manufacturing a semiconductor device. As shown in FIG. 3(a), a polycrystalline silicon film 2 as a lower wiring is formed on a silicon oxide film 1 provided on a semiconductor substrate or the like. Next, after forming a silicon oxide film 7 as an insulating film between the eyebrows, a photoresist film 3 for forming contact holes is applied, exposed to light, and developed. Next, as shown in FIG. 3(b), a contact hole is formed in the silicon oxide film 2 by anisotropic etching, and the photoresist film 3 is removed.
As shown in FIG. 3(C), an aluminum wiring 5 as an upper layer wiring is formed on the contact hole and the silicon oxide film 7.
A semiconductor device having a multilayer wiring structure was formed.
上述した従来の半導体装置の製造方法では、上下層配線
間のコンタクト抵抗は、コンタクトホールに露出してい
る下層配線の面積すなわち、コンタクトホールの面積に
よって制限されており、コンタクト抵抗を下げるのは事
実上困難であるという欠点があった。In the conventional semiconductor device manufacturing method described above, the contact resistance between the upper and lower layer wiring is limited by the area of the lower layer wiring exposed to the contact hole, that is, the area of the contact hole, and it is true that the contact resistance can be reduced. The disadvantage was that it was difficult to
本発明の目的は、コンタクトホールの面積を増加させず
に、コンタクトホールの抵抗を下げることが可能な半導
体装置の製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a semiconductor device that can reduce the resistance of a contact hole without increasing the area of the contact hole.
本発明の半導体装置の製造方法は、基板上に突起部を有
した第１の配線層を形成する工程と、前記第１の配線層
上に絶縁膜を形成する工程と、前記絶縁膜を前記突起部
側面が露出するまでエツチングする工程と、前記絶縁膜
及び前記突起部上に第２の配線層を形成する工程とを含
んで構成される。A method for manufacturing a semiconductor device according to the present invention includes the steps of: forming a first wiring layer having a protrusion on a substrate; forming an insulating film on the first wiring layer; The method includes a step of etching until the side surface of the protrusion is exposed, and a step of forming a second wiring layer on the insulating film and the protrusion.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ）〜（ｆ）は本発明の第１の実施例を説明す
るための工程順に示した半導体チップの断面図である。FIGS. 1A to 1F are cross-sectional views of a semiconductor chip shown in order of steps for explaining a first embodiment of the present invention.
第１図（ａ）に示すように、半導体基板等の上に設けら
れた酸化シリコン膜１上に、下層配線としての多結晶シ
リコン膜２を例えば、１．７μｍの厚さで形成する。次
に、突起部を形成するためのホトレジスト膜３を塗布し
、露光、現像を行なう。次に、第１図（ｂ）に示すよう
に、多結晶シリコン膜２を例えば；１．２μｍエツチン
グして、突起部８を形成する。次に、第１図（ｃ）に示
すように、基板全面にほう素りんガラス膜（以下、ＢＰ
ＳＧ膜４と称す）を例えば、１．５μｍの厚さで形成す
る。次に、第１図（ｄ）に示すように、ＢＰＳＧ膜４を
熱処理によって平坦化する０次に、第１図（ｅ）に示す
ように、突起部８が例えば、表面から０．２μｍ突出す
るまで、ＢＰＳＧ膜４をエツチングする。次に、第１図
（ｆ）に示すように、ＢＰＳＧ膜４上にアルミニウム配
線５を形成する。これにより、下層配線である多結晶シ
リコン膜２と、上層配線であるアルミニウム配線５との
コンタクトは、突起部の上面ばかりでなく、側面でもし
ていることになる。As shown in FIG. 1(a), a polycrystalline silicon film 2 serving as a lower wiring is formed to a thickness of, for example, 1.7 μm on a silicon oxide film 1 provided on a semiconductor substrate or the like. Next, a photoresist film 3 for forming protrusions is applied, exposed to light, and developed. Next, as shown in FIG. 1(b), the polycrystalline silicon film 2 is etched by, for example, 1.2 μm to form protrusions 8. Next, as shown in FIG. 1(c), a boron phosphorus glass film (hereinafter referred to as BP
A SG film 4) is formed to have a thickness of, for example, 1.5 μm. Next, as shown in FIG. 1(d), the BPSG film 4 is flattened by heat treatment. As shown in FIG. The BPSG film 4 is etched until it is etched. Next, as shown in FIG. 1(f), an aluminum wiring 5 is formed on the BPSG film 4. As a result, the contact between the polycrystalline silicon film 2, which is the lower layer interconnection, and the aluminum interconnection 5, which is the upper layer interconnection, is made not only on the top surface of the protrusion but also on the side surface.
第２図（ａ）〜（ｃ）は本発明の第２の実施例を説明す
るための半導体チップの断面図である。FIGS. 2(a) to 2(c) are cross-sectional views of a semiconductor chip for explaining a second embodiment of the present invention.
本実施例は、第２図（ａ）に示すように、第一の実施例
で説明した第１図（Ｃ）の工程において、絶縁膜として
用いたＰＢＳＧ膜４の替りにポリイミド膜６を塗布した
ものである。本実施例の場合、ポリイミド膜６を塗布し
た時点で、表面が平坦であるため、第１の実施例で行な
った高温熱処理を行なう必要がないという効果がある。In this embodiment, as shown in FIG. 2(a), a polyimide film 6 is applied instead of the PBSG film 4 used as an insulating film in the step of FIG. 1(C) explained in the first embodiment. This is what I did. In the case of this embodiment, since the surface is flat when the polyimide film 6 is applied, there is an advantage that there is no need to perform the high temperature heat treatment performed in the first embodiment.
以下、第２図（ｂ）〜（Ｃ）で、第１の実施例と同様な
工程を行ない、多層配線構造を有した半導体装置を製造
する。Hereinafter, in FIGS. 2(b) to 2(C), steps similar to those in the first embodiment are performed to manufacture a semiconductor device having a multilayer wiring structure.
以上説明したように、本発明は、下層配線に突起部を形
成し、眉間絶縁膜より突出させて上層配線と接触をとる
ことにより、接触面を突起部の上面のみでなく側面にま
で増加させることになるため、コンタクトホールの大き
さを増加することなくコンタクト抵抗を下げることが可
能となる効果がある。As explained above, the present invention increases the contact surface not only to the top surface of the protrusion but also to the side surface by forming a protrusion on the lower layer wiring and making the protrusion protrude from the glabella insulating film to make contact with the upper layer wiring. Therefore, there is an effect that the contact resistance can be lowered without increasing the size of the contact hole.
第１図（ａ）〜（ｆ）は本発明の第１の実施例を説明す
るための工程順に示した半導体チップの断面図、第２図
（ａ）〜（ｃ）は本発明の第２の実施例を説明するため
の半導体チップの断面図、第３図（ａ）〜（ｃ）は従来
の半導体装置の製造方法の一例を説明するための工程順
に示した半導体チップの断面図である。
１・・・酸化シリコン膜、２・・・多結晶シリコン膜、
３・・・ホトレジスト膜、４・・・ＢＰＳＧ膜、５・・
・アルミニウム配線、６・・・ポリイミド膜、７・・・
酸化シリコン膜、８・・・突起部。
ア、２
丈
図
亮
図1(a) to (f) are cross-sectional views of a semiconductor chip shown in the order of steps for explaining the first embodiment of the present invention, and FIGS. 2(a) to (c) are cross-sectional views of a semiconductor chip of the second embodiment of the present invention. FIGS. 3(a) to 3(c) are cross-sectional views of a semiconductor chip shown in order of steps to explain an example of a conventional method for manufacturing a semiconductor device. . 1... Silicon oxide film, 2... Polycrystalline silicon film,
3... Photoresist film, 4... BPSG film, 5...
・Aluminum wiring, 6... Polyimide film, 7...
Silicon oxide film, 8... protrusion. A.2 Jozu Ryozu
Claims (1)
、前記第１の配線層上に絶縁膜を形成する工程と、前記
絶縁膜を前記突起部側面が露出するまでエッチングする
工程と、前記絶縁膜及び前記突起部上に第２の配線層を
形成する工程とを含むことを特徴とする半導体装置の製
造方法。A step of forming a first wiring layer having a protrusion on a substrate, a step of forming an insulating film on the first wiring layer, and a step of etching the insulating film until the side surface of the protrusion is exposed. and forming a second wiring layer on the insulating film and the protrusion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18220788A JPH0231446A (en) | 1988-07-20 | 1988-07-20 | Manufacture of semicodnuctor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18220788A JPH0231446A (en) | 1988-07-20 | 1988-07-20 | Manufacture of semicodnuctor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0231446A true JPH0231446A (en) | 1990-02-01 |
Family
ID=16114227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18220788A Pending JPH0231446A (en) | 1988-07-20 | 1988-07-20 | Manufacture of semicodnuctor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0231446A (en) |
-
1988
- 1988-07-20 JP JP18220788A patent/JPH0231446A/en active Pending
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