JPH0231177A - Circuit inspection apparatus - Google Patents

Abstract

PURPOSE:To detect an erroneous operation generating source easily and rapidly in circuit planning by comparing the simulation result of a logical circuit with an expected value. CONSTITUTION:The output result obtained by simulation is compared with an expected value and, when the whole coincides, inspection is finished. When non-coincidence is detected, a logical circuit diagram is displayed on a graphic display. As one example, when the non-coincidence with the expected value is detected in two output signal values O1, O2 with respect to different input signal patterns, at first, the signal exerting effect on the signal value of the signal O1 is traced toward an input part on a logical circuit with respect to the signal O1 and the propagation route of said signal is displayed, for example, by changing the color thereof. Next, the same operation is performed with respect to the signal O2 and a separate color is superposed. Then, it is estimated that there is an error in the logical element present on the route becoming much in the superposition of colors at last, herein, in a logical element (g).

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a circuit verification device for quickly detecting a source of malfunction in a circuit design.

(Prior art) Conventionally, if the designed circuit is correct, the output signal value obtained as a result of simulation is compared with the corresponding expected value, and the name of the mismatched output signal and its value are displayed on the display. Try to display the following. In such a method, the designer must trace the cause of the malfunction to the input side on the circuit diagram based on the comparison results. Moreover, there is a problem in that a lot of time and effort are required when dealing with large-scale circuits. Also, how to display the results of logical simulation by value (color, line type, etc.)
A method of displaying logic diagrams on a graphic display, for example, is described in Japanese Patent Laid-Open No. 177.637/1982, but this method can be applied to large-scale circuits, but cannot detect errors in the design. Not yet.

(Problem to be solved by the invention) As mentioned above, the display of simulation results and the comparison of expected values have been effective even for large-scale circuits, but it is difficult to easily identify malfunctioning points in the design. It was impossible to find. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to easily and quickly find the source of malfunction in a circuit designed on a display based on a mismatch signal detected by comparison of expected values.

[Structure of the invention]

(Means and actions for solving the problem) When multiple discrepancies are detected between the simulation output results and expected values, the signal propagation paths are traced from those output signals to the input side, and if these paths are It is thought that the overlapping portion is most likely to be the cause of the malfunction. In the present invention, for a case where a plurality of mismatched output signals are detected after simulation, all paths on the input side for each output signal are targeted.

- Generally, this case is the most common, and the above verification method is the simplest method. According to the circuit verification method of the present invention, the suspicious path is displayed on the display, so that the designer can easily find the source of the malfunction. In reality, there may be cases in which the invention is quite complex, but these are outside the scope of the claims.

(Example) In general, the output results obtained by Siminiresion are compared with the expected values, and if they all match, the verification is terminated.

However, if a mismatch is detected, the logic circuit diagram shall be displayed on the graphic display. Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 shows an embodiment of the present invention. - As an example, consider a case where a mismatch with the expected value is detected in two output signal values (01 and 02) for different input signal patterns. Therefore, first, regarding the output signal 01, on the logic circuit, a signal that affects the signal value is traced to the input side, and the propagation path of the signal is displayed, for example, by changing the color of the line (first (shown as a dotted line in the figure). Next, perform the same operation for 02,
Another color (indicated by a broken line in FIG. 1) is layered. It is presumed that there was an error in the logic element on the path that ultimately overlapped the most, in this case logic element g. Here, for simplicity, it is assumed that there are two mismatches in the output results, but if there are K more, the above operation will be repeated in the same way. By using the above verification method, errors in a designed circuit can be detected more quickly than if done manually, and the circuit verification time can be shortened. The present invention is particularly effective when the output result includes a plurality of locations where the output result does not match the expected value, as in the above embodiment, and this is actually the most common case.

Further, the present invention targets all input signals that affect the above-mentioned mismatched output signal, and can be modified and applied in various ways without departing from the spirit thereof.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to easily and quickly detect the source of a malfunction in circuit design, and it is particularly effective when the target circuit is large-scale. The present invention allows designers to save a great deal of effort and time.

[Brief explanation of the drawing]

FIG. 1 is a logic circuit diagram of an embodiment according to the present invention. 11-i6...input signal, 01-08...output signal, a-t...logic element. Agent Patent Attorney Nori Ken Yudo Matsuyama Hikaru 1 Mi, Shishi 1 Yi 1 (1? 121 Ba 1 Ni &, 〜
m + -, shi he Δ - octopus

Claims (1)

[Claims] means for comparing a simulation result of a logic circuit with an expected value; means for displaying a comparison result by the comparison means; means for displaying the logic circuit on a graphic display; 1. A circuit verification device comprising means for displaying a propagation path of an influencing signal.