JPH01217277A - Test pattern preparation - Google Patents

Abstract

PURPOSE:To reduce the load at the time of trouble simulation and to efficiently prepare a test pattern, by detecting trouble even when the input of the test pattern is generated and further minimizing the input of the test pattern. CONSTITUTION:One trouble is preliminarily selected from objective trouble 8 wherein one or more trouble defined by a test pattern input generating means 3 to generate test pattern input 9 capable of detecting said trouble. Next, the detectable trouble 10 on a activated path is calculated by an activated path tracing means 4 and eliminated from the objective trouble 8 by a trouble elimination means 5. An plurality of the test pattern inputs 9 thus formed are minimized by a test pattern input uniting means 6 and trouble simulation is performed on the basis of the test pattern inputs 9 with respect to the objective trouble 8 by a trouble simulation means 7. By this method, a test pattern can be efficiently prepared.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a test pattern creation method, and more particularly to a test pattern creation method for determining whether or not a fault can be detected even when a test pattern is input in a test pattern creation method for logic circuits. .

[Conventional technology]

Conventionally, in this type of test pattern creation method, one or more faults are defined by the fault definition means.
After selecting one fault and generating a test pattern input that can detect the selected fault, fault simulation is performed for the target faults including the selected fault, and the generated test pattern input is used to determine which of the six faults. We were evaluating whether failures could be detected.

In addition, if there is an undetected fault as a result of the evaluation by fault simulation, one more fault is selected from the undetected faults and a test pattern input is generated to detect the selected undetected fault, and the fault simulation is performed. A method was adopted in which the process of conducting and evaluating the results was repeated until satisfaction was achieved (for example, see Ohm Publishing's "LSI Hunt Book", Volume 3, Chapter 2, 1984).

[Problem to be solved by the invention]

In the conventional test pattern creation method described above, unnecessary fault simulation is performed even when it is clear that the generated test pattern input can detect the selected fault. Since unnecessary fault simulations are performed even for faults that are known to be detectable, there is a drawback that memory and machine time are wasted.

In view of the above points, an object of the present invention is to detect faults even when test pattern input occurs, and further minimize test pattern input, thereby reducing target faults targeted for fault simulation and test pattern manpower. It is an object of the present invention to provide a test pattern generation method that can reduce the load during failure simulation and efficiently generate test patterns without wasting memory or machine time.

Means for Solving Problem C] The test pattern generation method of the present invention is a test pattern generation method for a logic circuit, which includes a test pattern input generation means for generating a test pattern input for a selected fault, and a test pattern input generation means for generating a test pattern input for a selected fault; an activation path tracing means for tracing the activated path from a fault detection point in the input generation means to find a detectable fault on the path; and a detectable fault on the path found by the activation path tracing means. Fault deletion means for deleting a fault from target faults, and merging a plurality of test pattern inputs generated after the processes by the test pattern input generation means, the activation path tracing means, and the fault deletion means are repeated. Using a test pattern input merging means and the test pattern input merged by the test pattern input merging means, a fault simulation is performed for the target fault from which the detectable fault has been deleted by the fault deletion means. It has a detection rate and a fault simulation means for creating a test pattern.

[Effect]

In the test pattern generation method of the present invention, the test pattern input generation means generates a test pattern input for a selected fault, and the activation path trace means is activated from the fault detection point in the test pattern input generation means. The path is traced to find a detectable fault on the path, the fault deletion means deletes the detectable fault on the path found by the activated path tracing means from the target fault, and the test pattern input merging means extracts the test pattern. The plurality of test pattern inputs generated after the processing by the input generation means, the activation path tracing means, and the fault deletion means are repeated are merged, and the fault simulation means merges the test pattern inputs by the test j/bang input collapse means. Using the input test pattern, a fault simulation is performed for the target fault whose detectable fault has been removed by the fault deletion means to create a detection rate and a test pattern.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of a test pattern creation method according to an embodiment of the present invention. The test pattern creation method of this embodiment includes a logic circuit 1, a fault definition means 2, a test pattern input generation means 3, an activation path tracing means 4, a fault deletion means 5, a fault simulation means 6,
It is composed of an eggplant 1-bang input merging means 7, a target fault 8, a test pattern input 9, a detectable fault 10 on the path, a detection rate 11, and a test pattern 12.

Next, the operation of the test pattern creation method of this embodiment configured as described above will be explained.

The fault definition means 2 defines a target fault 8 by assuming one or more faults in the logic circuit 1 in advance.

The test pattern input generating means 3 generates one of the target faults 8.
One fault is selected to generate a test pattern input 9 that can detect the selected fault.

Next, the activation path tracing means 4 starts fan-in tracing from the selected failure detection point, and if the output value of the fan-in side element is D or D, the activation path tracing means 4 starts the fan-in tracing from the selected failure detection point, and if the output value of the fan-in side element is D or D, the line to the determined fan-in side element is Since the above fault is a detectable fault, it is defined as detectable fault 10 on the path. Further, even if the output value of the fan-in side element is D or not D, the activation path tracing means 4 next determines the trace element and the fan-in side from the type of the trace element and the output value of the fan-in side element. If the line between the element and the element is a line in which a fault can be detected, it is determined as a detectable fault 10 on the path.

In addition, D is the value of the signal that indicates "'1" when normal and °'0°" when a failure occurs (indicating a stuck-at-0 fault), and D indicates "0" when normal and indicates "1" when a fault occurs (stuck-at-1). This is the value of the signal (indicating a failure).The output value of the fan-in side element is D
Or if it is D, this is the path through which the fault has propagated, so it is possible to detect the stuck-at-0 fault (when D) and the stuck-at-1 fault (when 15) on the line. Therefore, when the output values on the fan-in side are D and D, it is determined that there is a detectable fault 10 on the path.

Ma f, -1 For example, the type of trace element is 2 manual A
In the case of an ND (AND) gate, if the normal output values of the fan-in side elements are both "1" for the stuck-at-0 fault of the output of the two-man power AND gate, then the two lines on the fan-in side element side Input A when there is no fault on
Since the output value of the ND gate is "P1" and the output value of the input AND gate is "O" when a fault exists, a stuck-at-0 fault on the two lines on the fan-in side element side can be detected. In this way, a fault on a line that can be detected based on the type of trace element and the output value of the fan-in side element is defined as a detectable fault 10 on the path.

The activation path tracing means 4 performs fan-in tracing on all paths of the logic circuit 1 to extract detectable faults 10 on the paths.

Next, the target fault deletion means 5 deletes the detectable fault 10 on the path from the target fault 8.

The above process is repeated and a plurality of test pattern inputs 9 are generated.

After the multiple child stop inputs 9 are generated, the test I.
The button input merging means 6 inputs a plurality of test patterns.
Minimize (merge) 9.

Here, the merging process of the test pattern inputs 9 by the test pattern input merging means 6 will be explained.

For example, as shown in Figure 2, three test pattern inputs a
, b and C are generated.

Since there is no contradiction even if the test pattern input a and the test pattern input are overlapped, the test pattern input merging means 6 merges the test pattern input a and the test pattern input into j test pattern inputs d. . Therefore, the test pattern inputs 9 used for fault simulation in the fault simulation means 7 are test pattern inputs C and d. Note that X is a test pattern input value of an input terminal of a path that does not affect the selected fault.

Thereafter, the fault simulation means 7 performs a plurality of tests after the test pattern input merging means 6 performs merging processing on the target fault 8 from which the detectable fault 10 on the path has been deleted by the fault deletion means 5. A failure simulation is performed using a pattern input 9, and a test pattern 12 and a detection rate 11 are determined.

At this time, as shown in FIG. 3, for example, the detectable fault IO on the path when generating the test pattern input a, when generating the test pattern input A, and when generating the test pattern input C shown in FIG. Assuming B and C, the target fault 8 to be subjected to fault simulation by the fault simulation means 6 is the fault in the shaded area.

If the detection rate 11 is not sufficient, the process returns to the test pattern input generation means 3 and the above process is repeated.

〔Effect of the invention〕

As explained above, the present invention performs fault detection even when test pattern input occurs, reduces detectable faults from target faults, and further minimizes test pattern input.
Reduces the load during fault simulation by reducing the number of target faults and test pattern inputs for fault simulation.
Eliminate wasteful use of memory and machine time due to unnecessary failure simulations and efficiently
~It has the effect of being able to create patterns.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a test pattern creation method according to an embodiment of the present invention, FIG. 2 is a diagram for explaining the merging process in the test pattern input merging means in FIG. 1, and FIG. FIG. 2 is a diagram illustrating target faults when the fault simulation means in FIG. 1 performs fault simulation. In the figure, 1... logic circuit, 2... fault definition means, 3... test pattern input generation means, 4... activation path tracing means, 5... fault deletion means, 6... Test pattern input merging means, 7... Fault simulation means, 8... Target fault, 9... Test pattern input, 10... Detectable fault on path, 11... Detection rate, 12. ...This is a test pattern.

Claims (1)

[Claims] In a test pattern generation method for a logic circuit, a test pattern input generating means generates a test pattern input for a selected fault; an activation path tracing means for tracing the detected path to find a detectable fault on the path; a fault deletion means for deleting the detectable fault on the path found by the activation path tracing means from target faults; a test pattern input merging means for merging a plurality of test pattern inputs generated after the processing by the test pattern input generation means, the activation path tracing means, and the fault deletion means is repeated; fault simulation means for creating a detection rate and a test pattern by performing a fault simulation on a target fault whose detectable fault has been deleted by the fault deletion means using the test pattern input merged by the merging means; A test pattern creation method characterized by having the following.