JPH02306739A - Signal transmitter - Google Patents

Abstract

PURPOSE:To decrease the number of signal lines by applying frequency division operation based on a synchronous signal from a synchronous signal generating circuit, converting a parallel data into a serial data based on the output of a 1st frequency division circuit and converting the serial data into the parallel data in response to the output of a 2nd frequency division circuit. CONSTITUTION:A transmitter 3 is constituted of a 1st oscillation circuit 6, a frequency division circuit 7 frequency-dividing an output from the oscillation circuit 6, and a parallel/serial conversion circuit 9 converting a data in parallel bit from a detector 5 into a serial data synchronously with the output of the frequency division circuit 7. A receiver 4 is provided with an oscillation circuit 13 oscillated in the same frequency as an oscillated frequency of the oscillation circuit 6, the output of the oscillation circuit 13 is frequency-divided by a frequency division circuit 14 and given to a serial/parallel conversion circuit 16. Absolute position information from an absolute type position detector 5 is transferred synchronously with the parallel/serial conversion circuit 9 and the serial/ parallel conversion circuit 16 based on the synchronous signal given to the frequency division circuit 7 of the transmitter 3 and the frequency division circuit 14 of the receiver 4. Thus, the number of signal lines is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal transmission device for transmitting data signals from a transmitter to a receiver.

Conventional technical numerical value i? In ILI-controlled (abbreviated as NC) machine tools and robots, a large number of position detectors are used to determine their mechanical displacements. There are two types of 0-position detectors: absolute type and incremental type.

Although the incremental type has the advantage of a simple structure and a small number of signals, it has the disadvantage that the absolute position signal is lost when the power is cut off. On the other hand, although absolute position detectors can output absolute position information in any situation, they require multiple wires, and especially when using a large number of position detectors, the number of signal lines becomes enormous. The biggest problems associated with this are increased costs and decreased reliability.

A typical prior art is shown in FIG.

Electric power is supplied to the absolute position detectors D1 to D4 through two power lines la, and in order to derive the absolute position information, for example, 16
In the case of a bit, 16 output signal lines tb are connected to each other, and these lines lrt and lb are connected to the receiver 1 for each absolute type position detector.

Although the prior art shown in FIG. 8 has the advantage of being able to constantly receive the output signals of all the absolute position detectors D1 to D4, it has the disadvantage of having a large number of signal lines.

Other prior art is No. 9 [! It is shown in l. Power is supplied to each of the absolute position detectors DIl to DL4 via two power lines la, and the output signal is transmitted from the line lc to the receiver 1 by interconnecting the 16 lines and making a wired OR connection. give to Selection of each absolute position detector D11 to D14 is performed via two selection signal lines ld.

In the prior art shown in FIG. 9, each of the 16 output signal lines from each of the absolute position detectors Dll to D14 is connected to a common 16 output signal line lc, whereby the signal line The number is reduced. Therefore, in the prior art shown in FIG. 9, although it is possible to reduce the number of signal lines compared to the prior art shown in FIG.
The output signals of 11 to D14 have the disadvantage that they can only be selectively received by a selection signal via line ld. In addition, these absolute type position detectors D11 to D14
Wired OR processing of the output signals is required on the
If the arrangement of signal lines 4 is dispersed, this wiring process may even eliminate the advantage of reducing the number of signal lines.

Problems to be Solved by the Invention An object of the present invention is to provide a signal transmission device that can reduce the number of signal lines.

Means for Solving the Problems The present invention provides a signal transmission device for transmitting a data signal from a transmitter to a receiver, comprising: a first oscillation circuit; a first frequency divider circuit that suspends the frequency division operation when the synchronization signal is at a predetermined level and divides the output of the first oscillation circuit when the synchronization signal is at a predetermined other level; The receiver includes a parallel/serial conversion circuit that synchronously converts and derives parallel data into serial data.

a second oscillation circuit, which receives a synchronization signal and stops the frequency division operation when the synchronization signal is at the predetermined one level, and when the synchronization signal is at the other predetermined level, outputs the output of the second oscillation circuit;
A second frequency divider circuit that divides the frequency so that a pulse having the same frequency as the output of the first frequency divider circuit is output; Serial/Convert serial data to parallel data
The transmitter or the receiver is a signal transmission device characterized in that the transmitter or the receiver includes a synchronization signal generation circuit that optically generates a synchronization signal and supplies it to the first and second frequency dividing circuits.

According to the present invention, the frequency division operation ft of the first and second frequency dividing circuits is performed based on the synchronization signal from the synchronization signal generation circuit provided in the transmitter or the receiver. Second
The frequencies of the output pulses of the frequency dividing circuits are the same, and the parallel/serial conversion circuit converts and derives parallel data into serial data based on the output of the first frequency dividing circuit, and the output of the second frequency dividing circuit In response, the serial/parallel conversion circuit converts the serial data into parallel data, thus making it possible to significantly reduce the number of signal lines.

Embodiment FIG. 1 is an electrical circuit diagram of an embodiment of the present invention. This signal transmission device transmits a serial data signal from a transmitter 3 to a receiver 4 via a line 11.

The data signal to be transmitted is, for example, absolute position information of the absolute position detector 5. The oscillator 3 includes a first oscillation circuit 6 that oscillates at, for example, 8MHz, a frequency division circuit 7 that divides the output from the oscillation circuit 6, and a frequency division circuit 7 that responds to the output from the frequency division circuit 7 via a line 8. 0 including a parallel/serial conversion circuit 9 that synchronously converts parallel bit data from the absolute position detector 5 into serial data.
Frequency divider circuit 7 receives a synchronization signal via line 12;
When the synchronization signal is at one predetermined level, ie, low level in this embodiment, the frequency dividing ear is paused and the output remains at low level.

When the synchronization signal is at the other predetermined level, that is, the high level, this frequency dividing circuit 7 divides the output from the oscillation circuit 6 into, for example, 1/8 and outputs it to the line 8 via the inverter 7a. do. The parallel/serial conversion circuit 9 reads parallel data from the absolute position detector 5 when the synchronization signal is at one predetermined level, that is, low level in this embodiment, and converts the parallel data to the other predetermined level of the synchronization signal, that is, the low level in this embodiment. After going high, in response to a frequency divider pulse from line 8, data is brought out bit by bit in a predetermined order on line 11.

Power for the transmitter 3 may be supplied from any source, but in this embodiment, power is supplied from the receiving fi 4 via the line 13.

The receiver 4 includes an oscillation circuit 13 that oscillates at the same frequency as the oscillation frequency of the oscillation circuit 6 described above, that is, 8 MHz. The output of this oscillation circuit 13 is given to a frequency dividing circuit 14, and a pulse frequency-divided to 1/8 is derived from a line 15 and given to a serial/parallel conversion circuit 16. The serial/parallel conversion circuit 16 has a predetermined synchronization signal level,
That is, in this embodiment, after the frequency changes from a narrow level to a high level, serial data sent from the line 11 is sequentially read and converted into parallel data in synchronization with the rising edge of the frequency division pulse from the frequency dividing circuit 14 via the line 15. The data is converted and then output as parallel data to the memory means 17, such as a register, at the moment the synchronization signal becomes low level.

Frequency divider circuit 14 also connects line 18 to 1/(8×16)
A pulse whose frequency is divided into 1 and 2 is derived and applied to the monostable circuit 19.

The monostable circuit 19 responds to the falling waveform of the pulse from the line 18 and outputs a pulse that maintains a low level for a preset time to the line 12 as a synchronizing signal. The synchronization signal derived on line 12 is also applied to the frequency divider circuit 14 via line 14. The zero frequency divider circuit 14, like the frequency divider circuit 7, is configured such that the synchronization signal via line 14 is at a low level. The frequency division operation is stopped when the signal is at a high level, and the frequency division operation is performed when the signal is at a high level.

211th Nt! - Refer to and explain the operation. receiver 4
The oscillation circuit 13 derives an oscillation pulse shown in FIG. 2 (1), and the frequency dividing circuit 14 derives a pulse frequency-divided to 1/8 as shown in FIG. 2 (2) on a line 15. The 0 frequency divider circuit 14 internally divides 1/(8) as shown in FIG. 2 (3).
X2), and as shown in Figure 2 (4), divide the frequency by 1/(8X4), and then again as shown in Figure 2 (5).
), the frequency is divided by 1/<8X8), and from line 18, the frequency is divided by 1/(8
×16) is derived. One monostable circuit derives a synchronization signal lasting a predetermined time W1 at the trailing edge of the pulse via line 18, as indicated by the second [J(7).

In the transmitter 3, the oscillation circuit 6 generates a pulse as shown in FIG. 2 (8), and this pulse is transmitted to the oscillation circuit 13.
The zero frequency divider circuit 7, which may be out of phase with the pulse of
The frequency of the pulse that the 0 frequency dividing circuit 14 derives on the line 15 and the frequency of the pulse that the frequency dividing circuit 7 derives on the line 8, which derives the frequency divided pulse shown by There is. In this way, parallel/serial conversion circuit 1
6 derives the parallel bit data from the absolute position detector 5 via the line 11 every time the 211J (9) pulse rises, and outputs the parallel bit data from the absolute position detector 5 to the serial/parallel conversion circuit 1.
6 reads the serial data on the line 11 every time the pulse rises as shown in FIG.

Here, the parallel/serial conversion circuit 9 and the serial/parallel conversion circuit 16 are connected to each other based on the synchronization signal given to the frequency divider circuit 7 of the transmitter 3 and the frequency divider circuit 14 of the receiver 4 via the line 12.14. It will be explained that data is transferred synchronously and sequentially for corresponding bits. FIG. 3(1) shows the pulses derived from the oscillator circuit 13 of the receiver 4, and FIG. 3(2) shows the pulses derived by the divider circuit 14 on line 15, synchronized from the monostable circuit 19. The waveform of the signal is as shown in FIG. 3 (3). When this synchronizing signal is at a low level, the frequency dividing circuits 7 and 14 stop the frequency dividing operation fl'' as described above, and set the line 8 at a high level and the line 15.
remains at low level.

When this synchronization signal rises at time t2, which is at a low level during the period W1 from time t1 to t2, the frequency division circuit 14 starts frequency division operation, and the frequency division circuit 14 receives the signal from the oscillation circuit 13. The oscillation pulse is frequency-divided to 1/8 and becomes a high level at time t3, and the oscillation pulse is further frequency-divided and becomes a low level at time t4. The oscillation pulse waveform given from the oscillation circuit 6 of the transmitter 3 to the frequency dividing circuit 7 is as shown in FIG.
, the frequency division operation of the oscillation pulse from the oscillation circuit 6 is started, a level that becomes low at time t 3 a is derived on the line 8, and the pulse from the oscillation circuit 6 is further divided, and the level becomes high at time t 4 a. Line 8 is the pulse that becomes the level.
Derived as follows. Line 8. of such frequency divider circuit 7.14.
Although the pulses derived at line 15 are shifted by at most one period of the oscillator circuits 6 and 13, the parallel/serial conversion circuit and the serial/parallel conversion circuit responding to the rising edge of the frequency-divided pulse from line 8.15 In this way, the transmitter 3 and the receiver 4 can transmit absolute position information from the absolute position transducer 5 via the line 11 in a synchronized manner without interfering with the operation.

Figure 4 (1) shows the output data of the transmitter 3; Figure 4 (1) shows the output data of the transmitter 3;
2) indicates time tll at which the data on line ll is changed.

FIG. 5 (1) shows the received data of the receiver 4, and FIG.
2) indicates the data read timing. Time t21
At , data on line 11 is read.

FIG. 6 is an electrical circuit diagram of another embodiment of the invention. This embodiment is similar to the previous embodiment and corresponding parts are given the same reference numerals.It should be noted that in this embodiment the output of the monostable circuit 19 is applied to the base of the switching transistor 22; The power supply containing the synchronization signal from the receiver via switching transistor 22 is connected to line t.
5 to the transmitter 3, the frequency dividing circuit 7 as a synchronizing signal, and the power supply circuit 23. The power supply circuit 23 has a rectifying diode 24 and a smoothing capacitor 25, and smoothes the power supply including the synchronization signal via the line 15, and uses it as a power supply for the transmitter 3.

FIG. 7 (1) shows the waveform of the power supply including the synchronization signal derived to the line 15, and in the power supply circuit 23, the 712J (2
) is obtained from line 26, which is a substantially flat DC power source.

According to the embodiment shown in FIG. 6, the power supply line 13 described in connection with FIG. 1 described above is unnecessary, and the number of lines can be further reduced.

The present invention can be implemented not only in connection with absolute position transducers, but also in a wide range of applications for transmitting data.

Although the combination of the frequency divider circuit 14 and the monostable circuit 19 is provided in the receiver 4 in the above-described embodiment, in another embodiment of the present invention, the combination of the frequency divider circuit 14 and the monostable circuit 19 may be replaced with the frequency divider circuit 7 of the transmitter 3. You may also set it up.

Furthermore, it is of course possible to configure the transmitter by integrating it with an absolute position detector.

Effects of the Invention As described above, according to the present invention, a signal transmission device that can reduce the number of signal lines is realized.

[Brief explanation of the drawing]

Figure 1 is an electrical circuit diagram of one embodiment of the present invention, and Figure 2 is the electrical circuit diagram of one embodiment of the present invention.
[Waveform diagram for explaining the operation of the embodiment shown in m,
30 is a waveform diagram for explaining the operation related to the synchronization signal, FIG. 4 is a diagram for explaining the operation of the transmitter 3, and FIG.
6 is a diagram for explaining the operation of the receiver 4, FIG. 6 is an electric circuit diagram of another embodiment of the present invention, and FIG. 7 is a diagram for explaining the operation related to the synchronization signal of the embodiment shown in FIG. A waveform diagram for explanation, No. 80 is a block diagram of a typical prior art, and FIG. 9 is a block diagram of another prior art. 3... Transmitter, 4... Receiver, 5... Absolute type position detector, 6.13... Oscillation circuit, 7, 14
. . . Frequency dividing circuit, 9 . . . Parallel/serial conversion circuit, 10.
20... Power supply circuit, 16... Series/parallel conversion circuit,
17...Memory means, one...monostable circuit, 22.
...Switching transistor, 23... Power supply circuit agent Patent attorney Number of strokes Keiichi Figure 4 tl Figure 5 t'21 Figure 7 0□ Figure 8 σa i.

Claims (1)

[Claims] In a signal transmission device that transmits a data signal from a transmitter to a receiver, the transmitter comprises: a first oscillation circuit; a first frequency divider circuit that divides the output of the first oscillation circuit when the synchronization signal is at the other predetermined level; and a parallel/serial conversion circuit for converting and deriving serial data into serial data, and the receiver includes a second oscillation circuit, and a receiver that receives a synchronization signal and performs a frequency dividing operation when the synchronization signal is at the predetermined one level. the output of the second oscillation circuit when the synchronization signal is at the other predetermined level;
A second frequency divider circuit that divides the frequency so that a pulse having the same frequency as the output of the first frequency divider circuit is output; Serial/Convert serial data to parallel data
A signal transmission device comprising: a parallel conversion circuit, wherein the transmitter or the receiver includes a synchronization signal generation circuit that generates a synchronization signal and supplies it to the first and second frequency dividing circuits.