JPS6189757A - Signal transmission device - Google Patents

Abstract

PURPOSE:To keep the frequency of a trasmitted serial signal constant even if the frequency of a parallel signal is changed, by converting a clock pulse to a signal having a certain integer-fold frequency of the parallel signal and using this clock pulse to convert the parallel signal to the serial signal and transmitting the serial signal. CONSTITUTION:A frequency converting means 106 consists essentially of a PLL; and when the clock pulse whose frequency is changed to integer-fold frequencies such as 5MHz, 2.5MHz, and 1.25MHz is given to the means 106 as an input signal Pa, the means 106 outputs a high-speed clock pulse. This pulse Pc is given to a load signal generating circuit 107 together with the pulse Pa to obtain a load signal Pd. This signal Pd is given to a parallel-serial converting circuit 109 and is used as the load signal of the parallel signal.

Description

DETAILED DESCRIPTION OF THE INVENTION "Industrial Application Field" The present invention relates to a signal transmission device used when, for example, computers are connected to each other or a computer and a terminal device are connected by an optical cable and the two are connected by optical signals.

``Prior art'' When devices are connected using optical cables and signals are exchanged between devices, parallel signals are generally used within the devices, but in order to transmit optical signals, they must be converted to serial signals. It is common to transmit

``Problems to be Solved by the Invention'' When transmitting signals using optical cables, the signal is generally converted into a serial signal with a fixed repetition frequency and then transmitted. The reason for this is that when the frequency of the optical signal changes significantly, the pulse width of the signal changes greatly, causing errors. For this reason, the repetition period of the optical signal has conventionally been selected to be constant.

- Depending on the blade device, the repetition period of the parallel signal may change depending on the state. For example, 1.25 MHy.

There are some that change to various frequencies such as 2, 5 MHz, and 5 MHz. If the repetition frequency changes in this way, the pulse width of the optical signal will vary greatly, resulting in low reliability.

``Means for Solving the Problems'' This invention is configured to convert signals of various frequencies given into serial signals of integral multiples of mutually equal frequencies, and to transmit this serial signal through an optical cable. .

In this invention, a frequency converting means is provided for converting a clock pulse parallel signal synchronized with the parallel i signal into a signal having a constant frequency which is an integral multiple of the highest frequency which is sufficiently higher than the frequency, and from this frequency converting means. The parallel signal is converted into a serial signal using the obtained high-speed clock pulse, and the serial signal is transmitted as an optical signal.

Therefore, according to the present invention, even if the frequency of the parallel signal changes, the frequency of the serial signal transmitted through the optical cable is held constant. Therefore, signals of all repetition frequencies can be transmitted in the best condition.

"Embodiment" FIG. 1 shows an embodiment of the present invention. In the figure, 100 is a transmitting side, 200 is a receiving side, and 300 is an optical cable.

On the transmitting side 100, 101 is a clock input terminal;
2 indicates a parallel signal input terminal. Clock input terminal 101
The clock pulse Pa (FIG. 2A) applied to is delayed by the delay time given to the parallel signal by the delay circuit 103 and is applied to the drive circuit 104. The drive circuit 104 drives the electro-optical converter 105 and provides the optical signal La to the optical cable 300. For example, a laser diode can be used as the electro-optical converter 105. In this way, the clock pulse pa is converted into an optical signal La having the input waveform t, and is sent to the receiving side 200.

106 indicates frequency conversion means. This frequency conversion means 1
The details of 06 will be described later, but it is mainly composed of a phase-locked loop, and the input signal is, for example, 5 MHz,
When a clock pulse that varies by an integer multiple such as 2.5 MHz or 1.25 MHz is given, it outputs a high-speed clock pulse l'c of, for example, 20 MHz (Fig. 2 C) in synchronization with the clock pulse. .

This high-speed clock pulse Pc is used as an input clock, pulse P
a to the load signal generation circuit 107, and the load signal generation circuit 107 obtains the load signal Pd shown in the second figure. This load signal Pd is given to a parallel-to-serial conversion circuit 109, which will be described later, and is used as a load signal for parallel signals.

Parallel signal pb applied to input terminal 102 (FIG. 2B)
This example shows the case of 4-pin parallel signals. Which parallel signal Pb is applied to the latch circuit 108, and is latched by the latch circuit 108 at the timing of the rising edge of the input clock signal Pa. The latch output of the latch circuit '108 is applied to parallel-to-serial conversion circuits 10 and 9. The clock input terminal CK of the parallel-to-serial conversion circuit 109 is supplied with a high-speed clock signal, osis Pc, whose polarity is inverted by an inverter 110, and converted into a direct signal f synchronized with the high-speed pulse Pc. be done. An example of the waveform of the series signal 4pf is shown as Pg in FIG. 2G. □
The serial signal Pg may have a long H or L reading.

For this reason, if this is converted into an optical signal, the received waveform may deteriorate on the receiving side. Therefore, in this example, when the encoding circuit 112 converts the exclusive OR of the high-speed clock ■ and the serial signal Pg into a Manchester code that has the same pulse as the high-speed clock 100 in the interval where H or L continues. shows. FIG. 2H shows the Manchester encoded serial signal Ph. The Manchester coded serial signal Ph is retimed by a high speed clock in the retiming circuit 114 to remove the skew of the input data and adjust the waveform. FIG. 2 shows the retiming output signal Pi.

The retiming output signal Pi is amplified in the drive circuit 116 and the optical signal I4. The signal is converted into , inputted into the optical cable 300 and sent to the receiving side 200 .

FIG. 2J shows the waveform of the red half clock pulse Po- applied to the electro-optical converter 105, and the delay circuit 1 is arranged to delay the retiming output signal Pi by a short time d1.
03 delay time is set.

Optical signal La sent to the receiving side through optical cable 300
and Ll) are converted into spot signals by optical-to-electrical conversion means 201 and 202 provided on the receiving side 200. A clock pulse Pa shown in the third diagram is obtained from the optical-electrical conversion means 201. Further, from the optical-electrical conversion means 202, a serial signal P encoded as a manten star shown in FIG. 3A is output.
i is obtained.

This serial signal Pi and the clock signal PQ are input to the clock extraction circuit 203. The clock shown in FIG. 3F is obtained.

The clock extraction circuit 203 extracts all the rising and falling edges of the serial signal Pi shown in FIG. The edge mask EM shown in FIG. 3C is used to remove the clock signal, and the clock shown in FIG. 3F is obtained.

The clock obtained in the clock extraction circuit 203 is delayed by a time d1 in the delay circuit 204, and the /e pulse shown in FIG. The serial-parallel conversion circuit 205 takes in the serial signal Pi in synchronization with the clock. Every time a 4-bit serial signal is stored in the serial-parallel conversion circuit 205, the latch circuit 206 takes in the signal taken into the conversion circuit 205 as a parallel signal.

That is, the latch circuit 206 performs a latch operation in response to a latch signal applied from a latch command signal generator 209 constituted by a quaternary counter 207 and a flip-flop 208. Therefore, a latch command pulse is given from the latch command signal generator 209 every four clocks input to the serial-parallel conversion circuit 205, and is converted into a parallel signal Pb (FIG. 3G) every four bits. The parallel signal P'b latched by the latch circuit 206 is timed by the rising edge of the clock pulse pa in the retiming circuit 210 and output as parallel data p//b (Fig. 3) to the output terminal 2.
It is output from 11. FIG. 3J shows the clock pulses output from output terminal 212.

FIG. 4 shows an embodiment of the frequency conversion means 106.

The frequency conversion means 106 includes two time constant circuits 401 and 4.
02, and two D-type flip-flops 403 and 4 that read the charging voltage state of the time constant circuits 401 and 402.
04, a variable frequency divider 405 whose frequency division ratio changes according to the logic signals applied to the two input terminals A and B, a phase comparator 406, and a low frequency filter that filters the comparative output of the phase comparator 406. It can be configured by a pass filter 407 and a voltage controlled oscillator 408 whose oscillation frequency is controlled by the ripple output of the low pass filter 407.

The two time constant circuits 401 and 402 are made with different time constants. l) 1, 25 MHz as shown in Figure 5G
During the half cycle of the clock Pa3, as shown by H and H in FIG. For the 2.5 MHz clock Pa2 shown in Figure 5, the voltage of one time constant circuit 401 becomes L logic at the rising edge of the next cycle, but the voltage of the other time constant circuit 401 becomes H logic. A time constant is set to .

Furthermore, for the 5 MHz clock Pa1 shown in FIG. 5A, two time constant circuits 4 are activated at the rising edge of the next cycle.
01 and 402 are time constant circuits 40 so that both have H logic.
Set the time constants of 1 and 402.

The latch circuits 403 and 404 detect the presence or absence of the voltage applied to the data terminal from the time constant circuits 401 and 402 every time the clock pulse Pa rises, for example, and
Determine the frequency of the virus Pa. That is, variable frequency divider 405
When both input terminals A and B are at H logic, the clock pulse Pa is determined to be 5 MHz. When A and B are L logic and H logic, it is determined to be 2.5 MHz. When both A and B are L logic, it is determined that the frequency is 1.25 MHz.

The variable frequency divider 405 operates, for example, as a 1/4 frequency divider when terminal A and BKH logic are applied, and operates as a 1/8 frequency divider when L logic and H logic are applied to terminals A and B. However, when L logic is applied to both terminals A and B, it operates as a 1/16 frequency divider.

The voltage controlled oscillator 408 has a free running frequency of 20 MT (z). This 20 MHz oscillation signal is applied to the variable frequency divider 405. For example, H logic is applied to the input terminals A and B of the variable frequency divider 405. This variable frequency divider 4
05 operates as a 1/4 frequency divider, and divides the 20 MHz signal applied to the clock terminal CK to 1/4 frequency to obtain a 5 MT (z signal). This 5 MHz signal is sent to the phase comparator 406. At this time, the other input terminal of the phase comparator 406 receives a 5MT (z clock) from the input terminal 101, compares the phases of signals of the same frequency, and calculates the phase. The stain pressure control oscillator 408 is controlled by the comparison output, and its oscillation frequency is 20M1 (
It operates so that z.

On the other hand, the frequency of the input clock pulse Pa is 2.5MHz
, L logic and H logic are applied to input terminals A and B of the variable frequency divider 405. As a result, variable frequency divider 4
05 operates as a 1/8 frequency divider, converts the 20 MHz oscillation signal into a 2.5 MHz signal, and supplies the signal to the phase comparator 406. On the other hand, if the clock pulse given to the input terminal 101 changes to 1.25 Ml (z), the variable frequency divider 4
05 operates as a 1/16 frequency divider, and the phase comparator 406
A signal of 1.25 RIIHz is applied to.

In this way, the frequency of the clock pulse applied to the input terminal 101 is 5 MHz%'2.5'MHz,
If the frequency changes to 1.25 MHz, the variable frequency divider 405 also outputs 5 MHz.

2,5 MHz and 1.25 MHz are output, and the phases of signals of the same frequency can be compared in the phase comparator 406.
08 is 2 synchronized with the input clock/Nll system
It can output high-speed pulses of 0 MHz.

"Operations and Effects of the Invention" As described above, according to the present invention, when a parallel signal is converted into a serial signal and this serial signal is converted into an optical signal and transmitted, the frequency of the parallel signal changes as an integral multiple. However, the frequency of the series signal does not change.

Therefore, since the frequency of the optical signal is always maintained at a constant frequency, it is possible to reduce the incidence of errors on the receiving side. Therefore, a highly reliable optical signal transmission device can be provided.

Although the case where the parallel signal is 4 bits has been described above, the present invention is applicable not only to this number of bits but also to cases where other bit numbers are selected. Furthermore, although a case has been described in which Manchester encoding is performed on the transmitting side, it is not necessarily necessary to perform this encoding.゛

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIGS. 2 and 3 are waveform diagrams for explaining the operation of the transmitting side and receiving side shown in FIG. 1, and FIG. 4 is a block diagram showing an embodiment of the present invention. FIG. 5 is a waveform diagram for explaining the operation of FIG. 4. 100: Transmission side, 200: Receiving side, 300: Optical cable, 101: Clock signal input terminal, 102: Parallel signal input terminal, 105, 116: Electrical-optical converter, 106 Two-frequency conversion means, 112: Parallel-serial conversion circuit, 201.
202: Optical-electrical converter, 205: Series-parallel conversion circuit.

Claims (1)

[Claims] 1. In a signal transmission device that converts a parallel signal in which the same wave number repeatedly changes as an integer multiple to a serial signal and transmits the same, a clock pulse synchronized with the parallel signal is set to a clock pulse that is an integer sufficiently higher than the highest frequency of the parallel signal. A signal transmission device comprising frequency converting means for converting into a signal with a double constant frequency, and configured to convert the parallel signal into a serial signal and transmit the serial signal using a high-speed clock pulse obtained from the frequency converting means.