JPH0230546B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pattern recognition device that processes and recognizes image information.

Conventionally, pattern recognition devices have been configured as shown in FIG. 1 or 2, for example, by temporarily storing input image information in a shift register, image memory buffer, etc., and then storing it in a memory inside a computer. In other words, in the pattern recognition device shown in FIG. The image information stored in the shift register 13 is stored temporarily in the register 13.Then, the image information stored in the shift register 13 is stored in the memory in the computer 14 and predetermined calculations are performed. This monitors the image of the object photographed by the ITV camera 11 or the image of the object binarized by the quantization circuit 12.

Figure 2 shows the configuration of a pattern recognition device using an image memory buffer.
The image information input from 1 is stored in an image buffer memory 17 via an A/D (analog/digital converter 16). D/A conversion with 18 and TV
In addition to being displayed on the monitor 19, the above image information is sent to the computer 14 via the data input/output path D-BUS.
is configured to be supplied to, processed and recognized.

However, since the device shown in Figure 1 that has been put into practical use industrially processes image information by binarizing it, there are many restrictions on pattern recognition conditions such as changes in illuminance of the subject, dirt and scratches on the pattern, etc. , which has the disadvantage of poor recognition rate.

In addition, in the apparatus shown in FIG.
Since the information is read into the internal memory of the computer 14 and processed and recognized by the computer 14, there is a large amount of information to be processed, and the processing speed depends on the calculation speed of the computer 14, so a sufficient increase in speed cannot be expected. There is.

Although image processors are capable of high-speed processing, they are expensive. High-speed image processing processors are intended to calculate Fourier transforms and other orthogonal transforms at high speed, and are mainly used in medical, meteorological, scientific and technical calculations, etc. However, it is expensive and unsuitable for industrial use.

As mentioned above, all pattern recognition devices have drawbacks when used for industrial purposes, and currently, there are few restrictions on pattern recognition conditions, high-speed processing is possible, mass production is possible at low cost, and control programs are also comparable. A simple pattern recognition device is desired.

The present invention has been made in view of the above circumstances, and its purpose is to provide an arithmetic unit and a multiplier/accumulator that calculate the correlation coefficient between the drawing line input signal and the reference pattern signal, which are provided outside the computer. It is an object of the present invention to provide a pattern recognition device which enables high-speed processing and has almost no restrictions on identification patterns by performing pattern recognition by performing arithmetic processing in parallel.

An embodiment of the present invention will be described below with reference to the drawings.

Figure 3 shows the configuration of the photoelectric exchanger 2.
The image information read from 0 is sent to the A/D converter 2.
1 and subjected to A/D conversion. The digital output of the A/D converter 21 is supplied to gate circuits _{G 1} and 22.
TV via the D/A converter 23 depending on the open/close state of the
It is monitored on the monitor 24 or stored in the image memories M1 and M2 via the pass line C-BUS. The storage locations of the image memories M1 and M2 are determined by the address generation units A1 and A2, respectively, and the image memory M1 constituting the first memory stores the pattern to be recognized, and the image memory M2 stores the reference pattern. . The outputs of the image memories M1 and M2 are the path lines A-BUS and B-BUS, respectively.
The signals are read out and monitored on the TV monitor 24 via the gate circuits G ₁₇ , G ₁₈ , G ₂ and the D/A converter 23 . Also, during pattern recognition, the output of the image memory M1 is output from the arithmetic unit ALU and the multiplier/accumulator MA.
A predetermined calculation is performed by.

The above calculation unit ALU has logical product (addition), logical sum (subtraction), pass (1 addition), 1's complement (1 subtraction), 2
It has functions such as complement of , logical product accumulation (addition accumulation), logical sum accumulation (subtraction accumulation), etc.
The MA has functions such as multiplication, addition and accumulation after multiplication, and subtraction and accumulation after multiplication.

The outputs of the arithmetic unit ALU and the multiplier/accumulator MA are supplied to the working memory M3 constituting the second memory via the bus line C-BUS, and the outputs thereof are supplied to the bus lines A-BUS and B-BUS. This working memory M3 stores a detection pattern of a part of the reference pattern stored in the image memory M2, and the address to be output is determined by the address generation section A3, and the detected pattern of the reference pattern stored in the image memory M1 is determined. Multiply/accumulator MA with pattern
and the correlation coefficient is calculated. Each of the above circuits is controlled by a program of a control section CNT, and a control signal from the host computer 25 is supplied to this control section CNT. Further, the host computer 25 is connected to bus lines A-BUS and B-BUS so that signals can be transferred.

Next, in the above configuration, the timing charts in FIGS. 4 to 6 and the timing charts in FIGS.
The operation will be explained using a diagram showing the data structure of each image memory shown in the figure.

FIG. 4 is a timing chart when image data is input. The gate circuit 22 is controlled by the control unit CNT, gates G ₃ and G ₁₉ are opened, and the image is A/D converted by the A/D converter 21. Reads information to bus line C-BUS. And gate G ₄ ,
_G5 is opened and the input image data is stored in the image memories M1 and M2. This cycle is repeated to store all data of the input image specified in advance.

FIG. 5 is a timing chart when input image data is monitored. When reading image data M1, graphs G ₆ , G ₁₇ and G ₂ are opened and the image data is sent to the D/A converter 23. This analog signal is supplied to the TV monitor 2 and converted to D/A.
Display on 4. Further, the data in the image memory M2 is displayed on the TV monitor 24 by opening the gates G ⁷ , G ₁₅ and G ₂ in the same manner as above.

FIG. 6 is a timing chart showing the operating procedure when performing pattern recognition. A reference detection pattern (recognition pattern) is registered in the working memory M3, and its first address is controlled by the control unit CNT. The address generator A3 is controlled and set. After reading the data from working memory M3, the contents of address generation section A3 are transferred to the control section.
“1” is added by CNT. Image memory M
The data structure of working memory M3 is shown in FIG. 7, and FIG. 8 shows the data structure of working memory M3. here,
The reference pattern shown in FIG. 8 is part of the data in the image memory M2 shown in FIG.

Image memory M1 in which image input signals are stored
When performing recognition processing with the reference data M3, the first address of the working memory M3 is set to the control unit.
CNT also sets "0" to the address generation part A3, and after reading the image information from the image memory M1, the address generation part A
Add "1" to the contents of 3. Further, after the m-th readout, the control unit CNT is set to add (M−m) to the contents of the address generation unit A3.

The calculation procedure will be explained below. First, it is necessary to store reference data in the working memory M3 before calculation for pattern recognition, and in this case, the image information of the reference object is transferred to the photoelectric converter 2.
0, stored in the image memory M2 via the A/D converter 21 and the gate circuit 22. Then, a pattern of a predetermined portion to be recognized from the storage means of the image memory M2 is stored in the working memory M3 and used as reference data. After that, gate _G6 is opened and the contents of image memory M1 are transferred to bus line A-BUS.
Output to. At the same time, gates G ₉ and G ₁₁ are opened and the contents of the bus line A-BUS are set to the arithmetic unit ALU and multiplier/accumulator MA, and the graphs G ₁₆ and G ₁₂ are
, and sets the reference data in working memory M3 to multiplier/accumulator MA via bus line B-BUS. An addition/accumulation start signal S _ALU is supplied to the arithmetic unit ALU, and a multiplication/accumulation start signal S MA is supplied to the multiplier/accumulator _MA from the control unit CNT to start the computation. At this time, the data are each sampling point Xi,
Calculation is performed sequentially for each j, Yi, and j. Here, Xi,
j is each coordinate position of the input data group, Yi, j
is the coordinate position of the reference pattern.

By repeating the above calculation m+1 times,
_The calculation unit ^ALU has (m
+1) data is stored in the multiplier/accumulator MA as (m+1) of " _n 〓 ⁱ⁼⁰ Xi,j・Yi,j" (j=o)
The sum of the multiplications is calculated. After this calculation is _completed , ^the previously set value of (M−m) is added to the calculation generator A1 and the calculation ^is repeated in the _same way. j” is in the multiplier/accumulator MA as “ _o 〓 ⁱ⁼⁰ _n 〓 ⁱ⁼⁰ Xi,
j・Yi,j” is obtained.

By the calculations up to this point, the correlation coefficient between the part of the image input (broken line 26) in FIG. 9a and the reference pattern in FIG. 9b is determined.

Similarly, the initial value of the address generation section A1 is changed and recognition processing is performed in accordance with the above-described procedure, and the same pattern as the reference pattern shown in FIG. 9b is detected from the image data of FIG. 9a.

As explained above, according to the present invention, input image data and reference pattern storage, recognition processing, etc., which were conventionally performed inside a computer, can be performed by externally provided image memory, arithmetic unit, multiplier/accumulator, control unit, etc. Since it is configured to perform calculation processing in parallel, it enables high-speed calculation processing and high-speed data input that could not be obtained even with conventional large-scale computers and large-scale array processors, and the pattern recognition device has almost no restrictions on identification patterns. can get. In addition, it is fully applicable industrially, and the pattern recognition device of this invention can replace the current human visual inspection of pellet bonding alignment and mark detection to determine good and defective products. , significant labor savings can be achieved. Furthermore, since the device is relatively inexpensive compared to an array processor and the pattern recognition time is short, multiple photoelectric converters can be connected in parallel to perform multi-processing, and the device cost can be significantly reduced.

[Brief explanation of drawings]

1 and 2 are block diagrams showing the configuration of a conventional pattern recognition device, respectively. FIG. 3 is a block diagram showing the configuration of a pattern recognition device according to an embodiment of the present invention, and FIGS. 4 to 6. are respectively the third
Timing charts for each operation in the illustrated apparatus and FIGS. 7 to 9 are diagrams showing the data structure of each image memory, respectively. 20...Photoelectric converter, 21...A/D converter, 23
...D/A converter, 24...TV monitor, M1, M2
...image memory (M1: first memory), M3...working memory (second memory), ALU...calculation unit,
MA...multiplier/accumulator, CNT...control unit.

Claims (1)

[Scope of Claims] 1. A photoelectric conversion means for inputting image information of a subject, an analog/digital conversion means for converting the image information input from the photoelectric conversion means into analog/digital, and the above-mentioned analog/digital converted image. a first memory means in which information is stored;
By performing a logical operation on the information stored in the first memory means, and assuming that each coordinate position of the sampling point of the input image information is Xi,j, _n 〓 ⁱ⁼⁰ Xi,j (j=0~
n and m are the number of bits in one row of the first memory means;
n is the number of bits in one row of the first memory means); and a calculation means that operates in parallel with the calculation processing of the calculation means to multiply the input data of the first memory means by the data of the reference pattern. When accumulation is performed and each coordinate position of the sampling point of the input image information is Xi,j, and the coordinate position of the sampling point of the reference pattern is Yi,j, _n 〓 ⁱ⁼⁰ Xi,
a multiplication/accumulation means for calculating the sum of multiplications of j·Yi,j (j=0 to n, m is the number of bits in one row of the first memory means, and n is the number of bits in one column of the first memory means); A second memory means for storing the reference pattern and the processing results of the arithmetic means and the multiplication/accumulation means, and a control means for controlling each of the circuits, and a correlation coefficient between the image input signal and the reference pattern signal. A pattern recognition device characterized in that pattern recognition is performed by performing arithmetic processing in parallel with the arithmetic means and the multiplication/accumulation means.