JPH0757075A - Processor element of one-chip parallel processor for pattern processing - Google Patents

Abstract

PURPOSE:To enable a high functional and high speed pattern processing by making a register into a 1-bit register in the processor element of a one-chip parallel processor for pattern processing which is used for fetching the pattern information on a high speed visual sensor, etc., and processing the information at a high speed. CONSTITUTION:In a processor element 11 composed of plural sensors 12 sensing pattern information, the register of a one-chip parallel processor for pattern processing where plural processor elements 11 coupled with each picture element processing outputs of these sensors 12 or a picture element group composed of a few picture elements by 1 to 1 are integrated on an integrated circuit and a computing element, the computing element is composed of the computing element 22 of a bit serial arithmetic system and the register is composed by connecting plural 1-bit registers 21 with the computing element 22 in parallel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor element used in a one-chip parallel processing device for pattern processing, which is used for fetching pattern information from a high-speed visual sensor or the like and processing it at high speed.

[0002]

2. Description of the Related Art In many cases, pattern information processing such as image processing has high parallelism, and parallel processing of data is often effective. Utilizing this fact, many parallel processing devices for specific applications have been developed so far in fields where high-speed pattern processing is required, such as visual inspection of products on the production site.

However, these parallel processing devices for pattern processing are large-scale and complicated, and are therefore expensive. For image processing applications, most of the CCD (Ch
Since the arge coupled device) camera is used, the upper limit of the processing speed of the processing device is limited to the speed of capturing an image from this CCD camera (30 frames or 60 frames per second).

Generally, since the pattern information has a huge amount of data, the communication path between the sensor and the processing device has been an obstacle to speeding up the processing device. Increasing the speed of the communication path or increasing the capacity in order to solve this is not desirable in terms of wiring cost and reliability.

In order to solve the problem of the communication path while avoiding such complicated wiring, a sensor array for sensing pattern information and a processor array for processing pattern information in parallel are integrated on an LSI. A one-chip parallel processing device for pattern processing that has been realized is effective. That is, in the one-chip parallel processing device for pattern processing,
By implementing the sensor array and the processor array by one LSI, it is possible to solve the wiring problem by taking out a small amount of high-quality information as an output. At the same time, excellent effects such as high speed, small size, light weight, low price, and low power consumption can be obtained. At that time, since the number of gates on one LSI is limited, in order to process a pattern of higher resolution, the circuit scale of each processor element constituting the processor array should be minimized to mount a sensor and a processor. We must try to increase the number.

However, generally, when the circuit scale of the processor element is reduced, the arithmetic function is lost accordingly. Therefore, in order to realize a parallel processing apparatus for pattern processing having a certain degree of versatility, it is important to reduce the circuit scale of the processor element without degrading the function.

On the other hand, the processor element of the one-chip parallel processing device for pattern processing, which is the object of the present invention, cannot have an external storage device for the same reason as the above-mentioned wiring problem, so that it is necessary for the calculation. All of the data needs to be held in registers within the processor element. Therefore, in order to maintain the arithmetic function, the register structure of the processor element becomes important. That is, in a general microprocessor, the register is a storage area that can be read and written at a higher speed than a memory outside the processor, and the main purpose is to reduce the frequency of memory access. Since the register of the target processor element is the only storage area that the processor element can have, a register configuration that can effectively use this small storage area is required.

As a conventional example of a processor element of a one-chip parallel processing device for pattern processing aiming at such integration, “Masatoshi Ishikawa: Local pattern processing LSI using parallel processing and its application to a tactile sensor” (Proceedings of the Society of Instrument and Control Engineers, Vol. 24, No. 3, pp. 228-235 (1988)). FIG. 4 is a schematic diagram showing the configuration of the processor element of the pattern processing LSI according to this conventional example. In this conventional processor element, three 8-bit registers are used.
The shift register 41 is used, and each shift register 41 is connected to the arithmetic unit 42 through a multiplexer 43. Further, the 8-bit shift register 41 has a function of exchanging upper 4 bits and lower 4 bits in one step.

[0009]

In the above-mentioned conventional example, 8bi is used.
When performing calculation of data having a number of digits smaller than t, the data had to be moved to the input terminal of the calculator 42. Therefore, as a mechanism for moving this data, a shift mechanism for the register 41 and a mechanism for exchanging the upper 4 bits and the lower 4 bits were prepared.
It is a step that simply moves data and has nothing to do with arithmetic.

In order to effectively use a small number of registers, for example, two 4-bit shift registers 41 are provided in the 4-bit shift register 41.
In the case of storing data, it is necessary to temporarily save the data in the lower 4 bits in order to perform the operation on the data in the upper 4 bits, which also involves an operation unrelated to the operation. That is, when dealing with data having a bit width smaller than the bit width of a register (8 bits in the above-mentioned conventional example), these unnecessary operations must be performed, resulting in an increase in the number of program steps and The processing speed will decrease.

Upper 4 bits of the register described in the conventional example
By the function of exchanging the lower 4bits with the lower 4bits in one step, the reduction of the processing speed is improved to some extent as compared with the case of using only the shift register, but the exchange unit is 4bi.
Since it is fixed at t, it has almost no effect on data whose number of digits is not 4 bits.

In the 1-chip parallel processing device for pattern processing which is the object of the present invention, binarized data is often handled as the pattern data, and therefore the operation result is 4
It is often less than a bit.

Therefore, according to the present invention, as a register configuration,
The purpose is to eliminate the above-mentioned problems by adopting a structure that can efficiently handle data of 4 bits or less.

[0014]

To achieve the above object, the processor element of the present invention has a register configuration in which a plurality of 1-bit registers are arranged. That is, the processor element of the present invention is a one-chip parallel processing device for pattern processing in which a plurality of sensors for sensing pattern information and a plurality of processor elements for processing output signals of these sensors are integrated on one integrated circuit. The processor element is composed of a bit-serial arithmetic operation unit and a plurality of 1-bit registers connected in parallel to the operation unit.

[0015]

In the processor element of the one-chip parallel processing device for pattern processing of the present invention, since the arithmetic unit uses bit serial arithmetic, the arithmetic unit only needs to have an arithmetic circuit for 1 bit. The register is a 1-bit register,
Arrange the required number in parallel. The number of 1-bit registers is determined based on a request from an algorithm to be realized on the one-chip parallel processing device for pattern processing and a constraint on the number of gates of the LSI. Each register is a signal line for reading the register connected to the input terminal of the arithmetic unit,
It is connected to the write signal line from the output terminal of the arithmetic unit. By assigning a unique address to each register, a register for reading data and a register for writing a calculation result can be independently selected.
Since this processor element is intended to process the sensor signal, each processor element can directly capture the output signal of the sensor. Further, in order to configure the parallel processing device, each processor element has a mechanism for communicating with a neighboring processor element.

In the processor element of the present invention, as a result of using the 1-bit register, 1-bit operation can be executed by one instruction. For example, when an operation is performed on the data A and the data B to obtain the result C, the type of operation, the address of the register in which the data A and B are stored, and the address of the register in which the result is written are specified. As a result, the data is read from the register and the calculation result is stored in the register.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an embodiment in which the processor element of the present invention is applied to an LSI type visual sensor for detecting a feature amount of an object, and the processor elements are combined in a lattice form integrated on a one-chip integrated circuit. The photosensor array and the processor array are shown. The size of the array depends on the number of transistors that can be integrated in the LSI and the number of transistors of the processor element 11,
It depends on the area required for the optical sensor 12, but here, it is assumed that it is about 64 × 64. In this embodiment,
Since it is assumed that the optical sensor 12 that senses image pattern information outputs 1 when the light hits, the captured image is a binary image.

Each processor element 11 is connected to each optical sensor 12 in a one-to-one correspondence, and can directly capture the output signal of the sensor. It should be noted that one processor element may be coupled to a plurality of photosensors grouped into a small number.

Further, each processor element 11 can directly perform data communication with the processor elements 11 in four neighborhoods, and the neighborhood calculation for each pixel is performed in parallel with the binary image data obtained by the photosensor array. Run. Therefore, it is possible to perform pattern processing such as contour line extraction, thinning, and pattern matching at an extremely high speed.

In the present embodiment, the connection network of the processor elements 11 is in the form of a 4-neighbor connection grid for simplification, but other than this, an 8-neighbor connection or a hexagonal or triangular connection network is also conceivable. It is also conceivable to combine the processor elements in a straight line, depending on the application.

FIG. 2 shows the configuration of the processor element 11 of the parallel processing device for pattern processing, which is composed of ten 1-bit registers 21 and an arithmetic unit 22 for performing a bit serial operation.

In this processor element 11, as a device for reducing the circuit scale, bit serial operation is adopted for the operation unit, and SIMD (Single Instruction Stream Multiple Da) is adopted.
ta Stream) type parallel processing method was adopted. The bit serial operation is effective for reducing the circuit scale of the processor element because the circuit of the arithmetic unit needs only 1 bit. Also,
The SIMD type parallel processing method is a method in which all the processor elements operate with the same instruction, so that the control of the processor elements is simple and effective in reducing the circuit scale.

The register read signal line 23a and the register read signal line 23b are connected to the input terminals A and B of the arithmetic unit 22, and the register write signal line 25 is connected to the output terminal C. Each 1-bit register 21 is connected in parallel between the register read signal line 23a or the register read signal line 23b and the register write signal line 25.

The arithmetic unit 22 has three types of logical operations (logical product,
It is composed of a logical circuit that performs addition and subtraction. Other logical operations, multiplications, etc. can be realized by a combination of these operations, but an arithmetic unit equipped with these arithmetic circuits can be used if necessary. Ideally, in the program to be executed, it is optimal to prepare the arithmetic circuit that is used most frequently in the arithmetic unit 22.

The register 21 is used to hold data such as a picked-up image, a calculation result, a calculation coefficient, and an intermediate calculation result, and one register can hold only 1-bit data. The image data obtained from the optical sensor 12 is 1 bit, but the bit width of the data inevitably increases as the calculation process progresses.
When holding t data, for example, four registers are used to hold 4-bit data. A unique address is assigned to each of these registers 21, and each register 21 has a read gate 2 to be described later.
1b and a writing gate 21c are provided. By selecting opening / closing of these gates, the register 21a for reading / writing data can be selected. Therefore,
There is no multiplexer provided in the conventional example shown in FIG.

Although the number of 1-bit registers 21 is 10 in FIG. 2, this number is actually determined by a request from the application program to be executed by the processor element 11 and a constraint from the circuit scale. . For example, when performing a product-sum operation with image data of 4 neighborhoods, if the weighting coefficient for each pixel is 4 bits, the pixel data will be 1 bit.
, The result of multiplication with neighboring pixel data is 4bit.
The result of round addition is 7 bits, and at least 12 bits of registers are required. However, here, in order to minimize the number of registers used at the same time, the addition is performed immediately after the multiplication with each neighborhood. That way,
This is because it is not necessary to store the four multiplication results in total. In this embodiment, it is assumed that the weight coefficient of the product-sum calculation is 3 bits, and in this case, 10 registers are sufficient.

On the other hand, 3 used in a general image processing apparatus
The × 3 filter needs a product-sum operation with pixel data in 8 neighborhoods. In this case, if the weight coefficient is 4 bits, the multiplication result is 4 bits, and the result of adding 8 times is 9
14 bits are required for calculation. Furthermore, in order to improve the accuracy of the result, it is necessary to increase the bit width of the weight coefficient. For example, if the coefficient is set to 8 bits,
A 22-bit register is required.

Further, if the number of neighbors is further increased, the number of types of filters that can be realized increases, but the number of registers required also increases. As described above, if the number of registers per processor element is increased, the application range of the visual sensor of the present embodiment is expected to be expanded, but the circuit scale of the processor element is correspondingly increased, which makes integration difficult. As another example of image pattern processing,
Examples include detection of a moving object based on the difference between two images, extraction of a contour line of an object, and thinning using a logical operation. Since these processes mainly involve logical operations, they do not require as many registers as the product-sum operation and can be executed by the processor element of this embodiment.

Further, in FIG. 2, the 1-bit register 21 and the arithmetic unit 22 are connected as described above.
Since calculation cannot be performed between the registers connected to the same register read signal line, it is conceivable to divide the registers into three groups and connect them to the arithmetic unit 22 through a multiplexer as in the conventional example. Besides this, all 1
Various connection methods are conceivable, such as connecting a bit register or a part of 1-bit registers to both input terminals of the arithmetic unit 22 through an appropriate selector. However, if the multiplexer is used, the circuit scale of the processor element is increased accordingly.

The instruction to the processor element 11 is given as a micro instruction from a control circuit (not shown) outside the processor element 11. Each gate 21 in the processor element 11
A control line to which a micro command is sent is connected to b and 21c. Further, the constant used for the calculation is also directly sent to the register read signal line 23a and the register read signal line 23b as a part of the micro instruction.

FIG. 3 shows the details of the 1-bit register 21 shown in FIG. 2. The 1-bit connected to the register read signal line 23 and the register write signal line 25 via the read gate 21b and the write gate 21c. The register 21a is shown. A read gate control line 36 and a write gate control line 37 are connected to the read gate 21b and the write gate 21c in order to control the opening and closing of each.

Normally, the read gate 2 of all registers
1b and the writing gate 21c are closed. 1bi
The data read from the t register 21a is performed by opening the read gate 21b by the read gate control line 36.

Similarly, writing of data to the 1-bit register 21a is performed by opening the writing gate 21c by the writing gate control line 37 and connecting the 1-bit register 21a and the register writing signal line 25.

[0034]

According to the present invention, since the arithmetic unit of the bit serial arithmetic system is used as the arithmetic unit, the circuit of the arithmetic unit only needs to be 1 bit, which is effective for reducing the circuit scale of the processor element.

Further, according to the present invention, in the processor element of the one-chip parallel processing device for pattern processing, which often handles mainly data of a small bit width, by connecting the 1-bit register in parallel to the arithmetic unit, any register can be processed. Since the reading and writing are done in one step, it is possible to eliminate unnecessary movement of data. In the processor element of the conventional example, the register is an 8-bit shift register. Therefore, when mainly processing data with a small bit width such as a binary image, the intermediate result of the operation is stored in the register and then stored in the operator. Before reaching, 5 steps (4 steps for shift operation and 1 step for exchanging upper 4 bits and lower 4 bits of the register) are required, while the processor element of the present invention has 1 bit of register, the same operation is performed. Can be performed in one step. Therefore, as compared with the processor element using the shift register, the number of steps of the program is reduced, so that the execution speed is significantly improved.

When a shift register is used,
When allocating data with a small bit width to each register, it was necessary to optimally allocate the data in consideration of the valid period of data and the operation sequence. Since it does not affect the execution speed even if it is placed at, it can be said that the degree of freedom of data placement is greater than when using a shift register. This leads to the effective use of a small number of registers,
It means the improvement of the function of the processor element.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a processor element of a 1-chip parallel processing device for pattern processing.

FIG. 2 is a diagram showing a configuration of a processor element.

FIG. 3 is a diagram showing a configuration example of a 1-bit register.

FIG. 4 is a schematic view of a conventional example.

[Explanation of symbols]

 11 processor element 12 optical sensor 21 1bit register 21a 1bit register 21b read gate 21c write gate 22 arithmetic unit 23a, 23b register read signal line 25 register write signal line 36 read gate control line 37 write gate control line 41 8bit shift register 42 arithmetic unit 43 multiplexer

Claims (2)

[Claims] 1. A processor element of a one-chip parallel processing device for pattern processing, wherein a plurality of sensors for sensing pattern information and a plurality of processor elements for processing output signals of these sensors are integrated on one integrated circuit. A processor element of a one-chip parallel processing device for pattern processing, comprising a bit-serial operation type arithmetic unit and a plurality of 1-bit registers connected in parallel to the arithmetic unit. 2. A plurality of sensors for sensing pattern information, and a plurality of processor elements for processing the outputs of these sensors, which are connected to each pixel or to a pixel group consisting of a small number of pixels in a one-to-one correspondence. A processor element of a 1-chip parallel processing device for pattern processing integrated on an integrated circuit, comprising a register and a computing unit, wherein the computing unit is a computing unit of a bit serial computing system, and the register includes a plurality of 1-bit registers. A processor element of a one-chip parallel processing device for pattern processing, which is connected in parallel to arithmetic units.