JPH02304652A - Error address collecting system - Google Patents

Abstract

PURPOSE:To omit or miniaturize a part related to sending out an error address of a storage controller and to miniaturize the scale of a device by providing an access origin processor consisting of an actuating means for actuating a service processor, etc. CONSTITUTION:An actuating means 131 in an access origin processor 117 realizes an operation for actuating a service processor 115 by a firmware in accordance with a notice from a fault informing means 125 in a storage control ler 113. In this state, an error address of a main storage device 111 to be reported to the processor 117 is collected by the processor 115 through a firm ware executed on the processor 117. Also, a fact that a fault is generated and a part of the error address held in an error address holding means 123 are informed the processor 117 from the means 125, and in the processor 115, a part of the error address and the contents of plural means 123 are compared, and the error address is specified. In such a way, an error address sending-out part of the device 113 is omitted or miniaturized, and the scale of a device can be miniaturized.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Action Examples ■, Correspondence between the Examples and FIG. 1 ■ , First Example ■, Second Example ■0 Modifications of the Invention Effects of the Invention [Summary] Error address in which addresses of the main storage device held in the access pipeline in the storage control device are collected. Regarding the collection method, for the purpose of reducing the device scale of the storage control device, a plurality of access pipelines, a plurality of error address holding means for holding error addresses,
A storage control device having a failure notification means for notifying the occurrence of a failure; a service processor that collects the contents held in the error address holding means; and a main storage device that is an access source and receives notification from the failure notification means. an access source processor having a startup means for starting the service processor in response to an error, and a storage control means for storing error addresses collected by the service processor in a main memory, the service processor collecting error addresses in the main memory. Configure it to do so.

Furthermore, the fault notification means notifies the access source processor of the occurrence of a failure and a part of the error address held in the error address holding means, and the service processor sends a part of the error address and the collected error address holding means to the access source processor. The configuration is configured to identify an error address by comparing the contents held in each of the addresses.

[Industrial application field]

The present invention collects addresses of the main memory held in an access pipeline in the storage controller when an error occurs in the main memory in a computer system that accesses the main memory via a storage controller. The present invention relates to an error address collection method.

[Conventional technology]

The overall configuration of a computer system having a storage control device is described in the ninth section.
As shown in the figure.

In the figure, 911 is a central processing unit (CPU),
Performs processing such as program execution and data calculations. 91
3 is a main storage unit (MSU) composed of semiconductor memory, and the central processing unit 911 is connected to a storage control unit 91 to be described later.
It can be directly read and written via 5.

Further, 917 is a channel control device (CHP), and channel devices (CH) 919 and 92 are used for accessing input/output devices such as disk devices and displays (not shown).
1.

Further, 915 is a storage control unit (MCU), and central processing units 911. Main storage device 913. Channel control device 9
Exchange of data and instructions between the 17 devices is performed via this storage control device 915.

Furthermore, 931 is a service processor (SVP),
When a failure occurs in each component, the failure information necessary to analyze the failure is collected. This service processor 9
31 receives a notification of the occurrence of a failure from, for example, the central processing unit 911, and based on this notification, collects the contents of the hardware inside the central processing unit 911 by scanning out to obtain failure information.

By the way, the operating speed of the semiconductor memory that constitutes the main memory device 913 is very slow compared to the operating speed of the central processing unit 911, etc., and the main memory is slow because the next access is performed after one access is completed. The access efficiency of the device 913 will deteriorate. Therefore, attempts have been made to improve access efficiency by using techniques such as interleaving or access pipelines.

Interleaving is a technique that configures the main memory device 913 into multiple banks. By associating adjacent addresses with different banks and accessing these banks in parallel, the overall access efficiency of the main memory device 913 is improved. can be raised.

One bank is composed of a plurality (for example, several tens) of memory elements.

In addition, the access pipeline is divided into processors (central processing unit 911, channel control unit 9) depending on the difference in operating speed.
This is to avoid the waiting state of 13). When an access instruction to the main storage device 913 is supplied from the processor to the storage control device 915, this access instruction is immediately sent to the main storage device 911 and is also supplied to an access pipeline within the storage control device 915. The access instruction supplied to the access pipeline is sequentially shifted between a plurality of registers constituting the access pipeline, and is taken out after a predetermined period of time corresponding to the access speed of main storage device 913 has elapsed.

The storage control device 915 performs bus control and the like in accordance with the access instruction taken out from the access pipeline and processes the access results.

By the way, when a memory error such as a bit error occurs in the main storage device 913, it is necessary to specify the address where the error has occurred and perform processing such as separating the page containing this address. For this purpose, it is connected to the later stage of the access pipeline, and when an error occurs, the address included in the access instruction held in this access pipeline is converted into an error address (hereinafter, this error address is called the FS).
It is necessary to take it out as an address (referred to as the A address) and send it to the central processing unit 911.

FIG. 10 shows the configuration of a storage control device 915 focusing on FSA address transmission.

In the figure, 941,943,945,947 are access pipelines, and 951,953,955,957 are FSA registers (FSA registers that temporarily hold FSA addresses).
-R) and 961 indicate an FSA address sending circuit, respectively.

For example, an access instruction supplied to any of the four access pipelines is sequentially shifted between multiple registers that make up the access pipeline, and
It is output after a predetermined period of time corresponding to the operating speed. At this time, if an error occurs in the operation of the main memory device 913 (for example, a bit error when reading data), the corresponding FSA registers 951 to 957 will be updated to the address of the access destination output from the access pipeline (main memory device 913).
13 address) is held as the FSA address. Furthermore, this held FSA address is sent to the central processing unit 911 via the FSA address sending circuit 961, and the central processing unit 911 stores the FS address at a fixed address in the main storage device 913.
A address is stored and the operating system (O
5), the error is reported by machine check interrupt. The operating system is stored in main memory 9
13. The FSA address is taken out from the fixed address and processing such as page separation is performed.

[Problem to be solved by the invention]

By the way, in the conventional method described above, as the number of access pipelines increases or the address length of the main storage device f913 increases, the FSA address sending circuit 96
There is a problem in that the circuit scale of No. 1, that is, the device scale of the storage control device 915 becomes large.

In the FSA address sending circuit 961, the FSA register 9
In order to select one of the FSA addresses supplied from each of 51 to 957 and send it to the main storage device 911,
It is necessary to provide internal selectors corresponding to the number of FSA registers and FSA address length, and registers that hold FSA addresses, and the scale of these increases in proportion to the number of access pipelines and the number of bits of the address bus, that is, the address length. do.

The present invention was created in view of these points, and an object of the present invention is to provide an error address collection method that reduces the size of the device.

[Means to solve the problem]

FIG. 1 is a principle block diagram of the error address collection method of the present invention.

(i) Invention of claim 1 In FIG. 1, a storage control device 113 is a main storage device 1
A plurality of access pipelines 121 that sequentially store access instructions to 11, and this access pipeline 121
, a plurality of error address holding means 123 that hold the address of the main storage device 111 included in the access instruction as an error address when a failure occurs in the main storage device 111, and a plurality of error address holding means 123 that hold the address of the main storage device 111 included in the access instruction as an error address when a failure occurs in the main storage device 111; and a fault notification means 125 to notify the user of the problem.

The service processor 115 collects the contents held in the error address holding means 123.

The access source processor 117 is the source of access to the main storage device 111 and is the activation unit 13 that activates the service processor 115 in response to a notification from the failure notification unit 125.
1, and a storage control means 133 for storing error addresses collected by the service processor 115 in the main storage device 111.

Therefore, the service processor 115 is configured to collect error addresses of the main storage device 111 to be reported to the accessing processor 117 via firmware executed on the accessing processor 117.

(ii) I of claim 2 (2) The error address collection method of claim 2 is based on claim 1.
In the error address collection method, the failure notification means 125 notifies the access source processor 117 of the occurrence of a failure and a part of the error address held in the error address holding means 123, and the service processor 115 notifies the access source processor 117 of the occurrence of a failure and a part of the error address held in the error address holding means 123. The error address is identified by comparing the information stored in the error address storage unit 123 with the contents held in each of the collected error address storage means 123.

[For production]

(i ”; 11) The storage control device 113 has a plurality of access pipelines 121 that sequentially store access instructions to the main storage device 111.
and a plurality of error address holding means 123 corresponding thereto. When a failure occurs in the main storage device 111, the address of the main storage device 111 included in this access instruction is stored in the error address holding means 123 as an error address.

Further, in response to the occurrence of the fault, the fault notification means 125 in the storage control device 113 notifies the access source processor 117 of the occurrence of the fault.

The activation means 131 in the access source processor 117 activates the service processor 115 in response to the notification of the occurrence of a failure in the storage control device 113. The activated service processor 115 collects the contents held in the error address holding means 123 in the storage control device 113 and obtains the error address.

This collected error address is the access source processor 1
17, and is stored in the main storage device 111 by the storage control means 133 in the access source processor 117.

　　.

In the invention of claim 1, the access source processor 117 is notified of the occurrence of a failure, and the service processor 115 collects the error address.

ii) I of Claim 2 In the error address collection method of Claim 2, the failure notification means 125 notifies the access source processor 117 of the occurrence of a failure and a part of the error address held in the error address holding means 123. .

Service processor 115 activated in response to this notification
In the invention of claim 2, the error address to be collected is characterized by comparing the content held in the collected error address holding means 123 with a part of the error address included in the notification. The access source processor 117 is notified of the occurrence and part of the error address, and the service processor 115 collects the remaining part or the entire error address.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of a computer system in a first embodiment and a second embodiment that utilize the error address collection method of the present invention. Further, FIG. 3 shows the configuration of the storage control device of the first embodiment, and FIG. 6 shows the configuration of the storage control device of the second embodiment.

(2) Correspondence between the embodiment and FIG. 1 Here, the correspondence between the embodiment of the present invention and FIG. 1 will be shown.

The main storage device 111 corresponds to the main storage device 221.

The storage control device 113 corresponds to the storage control device 231.

The service processor 115 is the service processor 24
Corresponds to 1.

The access source processor 117 corresponds to the central processing unit 211.

The access pipeline 121 corresponds to the access pipelines 311, 313, 315, and 317.

The error address holding means 123 stores the FSA register (F
SA-R) 321, 323, 325, 327.

The failure notification means 125 corresponds to the error reporting circuit 331 and the error reporting circuit 631.

The activation means 131 and the storage control means 133 can be realized by firmware 213.

Examples of the present invention will be described below assuming that the correspondence relationship as described above exists.

The computer system of the first embodiment shown in FIG. 2 has a central processing unit (CPtJ) 211. Main storage unit (MSU) 2
21. A storage control unit (MCU) 231 and a service processor (SVP) for monitoring failures, maintenance, etc.
)241.

The service processor 241 collects and analyzes the internal state of each component (for example, the contents held in internal registers) by scanning out, and is provided in a general computer system.

Further, the central processing unit 211 includes firmware 213 that starts the service processor 241 when a failure occurs. The firmware 213 operates, for example, by executing a firmware program stored in a memory area (not shown) inside the central processing unit 211. Also, operating system 2
15 operates by executing an operating system program loaded into the main storage device 221 from an external storage device (not shown), for example.

FIG. 3 shows the configuration of the storage control device 231.

In the figure, 311, 313, 315, and 317 are access pipelines, and 321, 323, 325, and 327 are FSA registers (FSA registers that temporarily hold FSA addresses).
-R), 331 is an error reporting circuit that notifies the firmware 213 in the central processing unit 211 of the occurrence of an error in accessing the main storage device 221, 333 is a register that stores the type of error, and 351 is a register that stores the error occurrence. The error detection circuits that detect the error are shown in each figure.

The storage control device 231 has, for example, four access pipelines 311 to 317, and the central processing unit 211
The access instruction to the main storage device 221 output from
Provided to either access pipeline. Thereafter, this access instruction is sequentially shifted between multiple registers configuring each access pipeline, and is output from the access pipeline after a predetermined time corresponding to the operating speed of the main storage device 221, and is used to control a bus (not shown), etc. used for.

The error detection circuit 351 generates an error signal when detecting an error in the operation of the main storage device 221 corresponding to the access instruction. For example, bit errors in data read from the main storage device 221 are detected based on the error correction code ECC. This error signal is transmitted to the F
It is supplied to SA registers 321-327. Applicable F
The SA registers 321 to 327 hold, as FSA addresses, the addresses of the main storage device 221 included in the access instructions output from the access pipelines 311 to 317 in response to the supply of the error signal.

Further, the error detection circuit 351 stores information regarding the type of error in the register 333 in the error reporting circuit 331 when detecting an error. For example, the register 333 has a capacity of 3 bits, and stores bit data indicating whether a 1-bit error has occurred in read data, bit data indicating whether a 2-bit error has occurred, and focus data indicating whether these errors have occurred.

In this way, the error reporting circuit 331
The firmware 213 of the central processing unit 211 is notified of the information regarding the error type stored in 3.

FIG. 4 shows the operational procedure for collecting FSA addresses in the first embodiment. Further, FIG. 5 shows the operating procedure of the FSAS address collection time-visual processor 241.

The operation of the first embodiment will be described below with reference to FIGS. 2 to 5. It should be noted that each of the symbols ① to ① below corresponds to each symbol shown in FIG. 2.

■If a single bit error or double bit error occurs in the data read from the main memory device 221 (
Step 411), the error detection circuit 351 in the storage control device 231 detects this error and stores the FSA address in the corresponding FSA registers 321 to 327 (Step 412).

Further, the error detection circuit 351 stores information regarding the type of error in the register 333, and the error reporting circuit 331 stores information regarding the type of error in the register 333.
is notified (Ste Nobu 413). For example, this notification may be provided as an interrupt to firmware 213.

(2) Next, the firmware 213 requests the service processor 241 to collect FSA addresses (step 414).

■The service processor 241 that has received the request to collect FSA addresses scans out the storage control device 231 and collects the FSA addresses stored in the FSA registers 321 to 327 inside the storage control device 231 (step 415).

For example, if there are four input ports for access instructions corresponding to the number of access pipelines, and they are respectively designated as A port, B port, C port, and D port (corresponding to access pipelines 311 to 317), the service processor 241 first determines whether an error has occurred at port A (step 511), and if the determination is affirmative, the
The FSA address is collected from the FSA register 321 corresponding to the port (step 515).

If a negative determination is made in step 511, B
Determining whether an error has occurred in the boat (step 512);
Determining whether an error has occurred in the C boat (step 513)
, Determine whether an error has occurred in the D boat (step 514)
), and if a positive judgment is made for each, the corresponding FSA
Collect FSA address from register (step 5)
15).

If a negative determination is made in step 514, an error message indicating that a failure has occurred in the error detection mechanism is output (step 516), and the operation ends.

(2) The service processor 241 sends the FSA address thus collected to the firmware 213.

(2) Next, the firmware 213 stores the FSA address received from the service processor 241 in the main storage device 221 at the fixed address where the FSA address should be stored (step 416).

(2) When the storage of the FSA address in the main storage device 221 is completed, the firmware 213 generates a machine check interrupt, interrupts the operation of the operating system 215 (step 417), and notifies the occurrence of this machine check error.

Thereafter, the operating system 215 performs error analysis processing using a machine check interrupt. During the error analysis process, a 1-bit error in the main storage device 221, 2
When a bit error is detected, the main memory 22
The FSA address stored in the fixed address 1 is read out, and FSA addresses with 1-bit error or 2-bit error are recognized. In the case of a 2-bit error, it cannot be corrected by ECC loading, so the operating system 21
5 performs processing such as page separation.

In this way, when an error is detected in the storage control device 231, the FSA address is stored in the corresponding FSA registers 321 to 3.
27 and notifies the central processing unit 211 of the occurrence of this error. The firmware 213 of the central processing unit 211 starts the service processor 241 in response to this notification, and executes the FS by the service processor 241.
A collection of A addresses is performed. The collected FSA addresses are stored in the main storage 221 by the firmware 213.
is stored in When this storage operation is completed, the firmware 213 interrupts the operating system 215, and the operating system 215 reads the FSA address stored in the main memory 221 and performs fault processing such as page detachment in the case of a 2-bit error. conduct.

Therefore, when an error occurs, the storage control device 231 only needs to notify the central processing unit 211 of the occurrence of the error, and the circuit for sending the FSA address is omitted, reducing the size of the storage control device 231. be able to.

In addition, by notifying only the presence or absence of an error in this way, it is possible to easily cope with the case where the capacity of the main storage device 221 is expanded (because it is not related to the address length).
.

FIG. 6 shows the configuration of the storage control device 611 of the second embodiment. In the storage control device 611 in FIG. 6, the same reference numerals as in the storage control device 231 in FIG. Explain the operation. In the overall configuration of the computer system of the second embodiment, the storage control device 231 in the computer system shown in FIG. 2 is replaced with a storage control device 611.

In FIG. 6, 631 represents an error reporting circuit, 635 represents a selector, and 637 represents an FSA address sending circuit.

When the error detection circuit 351 detects an error and outputs an error signal, the corresponding FSA registers 321 to
327, the FSA address is captured. At this time, a part of each FSA register 321 to 327 (for example, the upper n
bit) is supplied to a selector 635 in the error reporting circuit 631, and a selection operation is performed according to the error signal output from the error detection circuit 351. For example, when the FSA address is held in the FSA register 323 by the error signal output from the error detection circuit 351,
A part of the FSA address output from the SA register 323 is selected based on this error signal.

A portion of the FSA address selected and output by the selector 635 is notified to the firmware 213 of the central processing unit 211 by the FSA address sending circuit 637.

Also, in the same manner as in the first embodiment, the register 333
Information regarding the error type is stored in the central processing unit 2.
The firmware 213 of No. 11 is notified.

FIG. 7 shows the operational procedure for collecting FSA addresses in the second embodiment. Further, FIG. 8 shows the operation procedure of the service processor 241 when collecting FSA addresses.

The operation of the second embodiment will be described below with reference to FIG. 2 and FIGS. 6 to 8. In addition, each symbol of ■ to ■ below is
They correspond to the respective symbols shown in FIG.

■When an error occurs in the data read from the main memory device 221 (step 711), the error detection circuit 351 detects this error and stores the corresponding FSA registers 321-
Store the FSA address in 327 (step 712)
.

Further, a part of the FSA address stored in any of the FSA registers 321 to 327 is transferred to the FSA address via the selector 635.
It is sent to the SA address sending circuit 637. The error reporting circuit 631 receives information regarding the error type in the register 333 stored by the error detection circuit 351 and the FSA.
The part of the FSA address sent to the address sending circuit 637 is notified to the firmware 213 of the central processing unit 211 (step 713).

(1) Next, the firmware 213 requests the service processor 241 to collect FSA addresses (step 714).

■The service processor 241, which has received the request to collect FSA addresses, scans out the storage control device 611 and registers the FSA register 32 of the storage control device 611.
The FSA addresses stored in 1 to 327 are collected (step 715).

For example, as in the first embodiment, there are four input ports for access instructions, corresponding to the number of access pipelines.
Let them be A boat, B port C boat, and D boat, respectively.

First, the service processor 241
Get part of the FSA address included in the notification from 1 (
step 811).

Next, the service processor 241 determines whether an error has occurred in the A port (step 812), and if the determination is affirmative, the service processor 241 determines whether or not an error has occurred in the A port.
It is determined whether the bit matches the part of the FSA address obtained in step 811 (step 813).
). If an affirmative judgment is made here, the service processor 241
collects the remaining portion of the FSA address from the corresponding FSA registers 321-327 (step 820).

If a negative determination is made in step 812 or step 813, the following steps are performed in the same way: determining whether an error has occurred in the B boat (step 814), determining whether a part of the FSA address matches (step 815), and determining whether or not a part of the FSA address matches (step 815). Determining whether an error has occurred (step 816), determining whether part of the FSA address is a one-time loss (step 817), determining whether an error has occurred in the D boat (step 81B), part of the FSA address It is determined whether or not they match (step 819). If a positive determination is made in any of steps 81.5, 817, and 819, the remaining portion of the FSA address is collected from the corresponding F'SA register (step 820).

If a negative determination is made in step 81B or step 819, an error message indicating that a failure has occurred in the error detection mechanism is output (step 821),
Finish the operation.

(2) The service processor 241 sends the collected FSA address to the firmware 213.

Next, the firmware 213 stores the FSA address in the main storage device 221 (Step 9. Step 716).

■When the storage of the FSA address in the main storage device 221 is completed, the firmware 213 interrupts the operation of the operating system 215 (step 717L).
Notify machine check error occurrence (this FSA
(notify the end of the address collection operation).

In this manner, when the storage control device 611 detects an error, it holds the FSA address in the corresponding FSA registers 321 to 327, and notifies the central processing unit 211 of a portion of the FSA address along with the fact that the error has occurred. The firmware 213 of the central processing unit 211 activates the service processor 241 in response to this notification, and the service processor 241 collects FSA addresses.

In collecting this FSA address, the service processor 241 collects the FSA addresses learned from the storage control device 611.
The part of the address is compared with the part of the FSA address collected from the FSA registers 321 to 327, and the matching FSA
Remaining FSA addresses in SA register (all are OK)
to collect. By performing such a comparison operation, when a plurality of errors corresponding to two or more access pipelines occur, it becomes easy to specify one FSA address corresponding to the notification of error occurrence.

The collected FSA addresses are stored in the main storage device 221 by the firmware 213.

When this storage operation is completed, the firmware 2I3 interrupts the operating system 215, and the operating system 215 thereafter reads the FSA address stored in the main storage device 221 and performs failure processing such as page separation in the case of a 2-bit error. conduct.

Therefore, when an error occurs, the storage control device 611 only needs to notify the central processing unit 211 of the error occurrence and a part of the FSA address. The scale of the device can be reduced.

Further, by notifying the occurrence of an error and a part of the FSA address in this way, it is possible to easily cope with the case where the capacity of the main storage device 221 is expanded. in this case,
The capacity of the main storage device 221 may be expanded by extending the length of addresses other than a part of the FSA address to be notified.

■Note: In the embodiment of the present invention described above, when an error occurs, 3-bit information regarding the type of error stored in the register 333 is notified. Only information indicating whether or not an error has occurred will be notified, and the type of error and FSA
The addresses may be collected by the service processor 241.

In addition, in ``correspondence between Examples and Figure 1'',
Although the correspondence between the present invention and the embodiments has been described, those skilled in the art will easily assume that the present invention is not limited to this and that there are various modifications.

〔Effect of the invention〕

As described above, in the invention of claim 1, the storage control device notifies the access source processor of the occurrence of a failure, and the service processor collects the error address. By omitting this section, the scale of the storage control device can be reduced.

Further, in the invention of claim 2, since the storage control device notifies the access source processor of the occurrence of a failure and a part of the error address, and the service processor collects the error address, an error in the storage control device It becomes possible to reduce the size of the storage control device by reducing the size of the portion related to address sending.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of the error address collection method of the present invention. FIG. 2 is a configuration diagram of an embodiment to which the error address collection method of the present invention is applied. FIG. 3 is a configuration of a storage control device according to the first embodiment. 4 is an explanatory diagram of the operation of FSA address collection in the first embodiment, FIG. 5 is an explanatory diagram of the operation of the service processor of the first embodiment, and FIG. 6 is a configuration diagram of the storage control device of the second embodiment. , Fig. 7 is an explanatory diagram of the operation of FSA address collection in the second embodiment, Fig. 8 is an explanatory diagram of the operation of the service processor of the second embodiment, Fig. 9 is a configuration diagram of the computer system, and Fig. 10 is the conventional FIG. 2 is a configuration diagram of a storage control device. In the figure, Ill is a main storage device, 113 is a storage control device, 115 is a service processor, 117 is an access source processor, 121 is an access pipeline, 123 is an error address holding means, 125 is a failure notification means, 131 is a starting means, 133 is a storage control means, 211 is a central processing unit (CPU), 213 is a firmware, 215 is an operating system, 221 is a main storage unit (MSU), 231 is a storage control unit (MCU), 241 is a service processor (SVP), 311.3-
13, 315, 317 are access pipelines, 321, 323, 325, 327 are FSA registers (FSA registers).
SA-R), 331.631 is an error reporting circuit, 333.661, 663, 665, and 667 are registers, 351 is an error detection circuit, 635 is a selector, and 637 is an FSA address sending circuit. Saizen F3 day training D...Zu Fig. 1 Fig. 2, 1st change, f'l'J ty> 4. Figure 1. Lightly specifies the ψ force f1 of Bisfo Ren and Tsubu. Figure 5.
Figure 7 Figure 8

Claims (2)

[Claims] (1) A plurality of access pipelines (121) that sequentially store access instructions to the main storage device (111), and corresponding to each of the access pipelines (121),
a plurality of error address holding means (123) for holding the address of the main storage device (111) included in the access instruction as an error address when a failure occurs in the main storage device (111); a storage control device (113) having a failure notification means (125) that notifies the error address; a service processor (115) that collects the contents held by the error address holding means (123); and the main storage device (111). ), the activation means (131) is an access source of the service processor (115) and uses firmware to realize an operation of activating the service processor (115) in response to a notification from the failure notification means (125); storage control means (111) for storing the collected error addresses in the main storage device (111);
an access source processor (117) having: an access source processor (117) having an access source processor (133); An error address collection method characterized by being configured to be collected by a service processor 115. (2) In the error address collection method according to claim 1, the fact that the failure has occurred and the error address holding means (123
) from the failure notification means (125) to the access source processor (117).
and the service processor (115) identifies the error address by comparing a part of the error address with the collected contents of each of the plurality of error address holding means (123). error address collection method.