JP4749812B2 - Test equipment - Google Patents

Description

  The present invention relates to a test apparatus. In particular, the present invention relates to a test apparatus for obtaining a repair solution for replacing a defective memory cell of a memory under test with a spare cell.

2. Description of the Related Art Conventionally, there is known a memory test apparatus that calculates a repair solution (for example, see Non-Patent Document 1) for replacing a defective memory cell in a semiconductor memory with a spare cell. A conventional memory test apparatus includes a plurality of test units for detecting defective memory cells and a plurality of analysis processing units provided corresponding to the test units. Each analysis processing unit obtains a repair solution for the corresponding semiconductor memory based on information on the defective memory cell detected by the test unit.
In addition, the memory test apparatus includes a large number of test units, so that a large number of semiconductor memories are tested in parallel to improve processing efficiency.

Jin-Fu Li, 6 others, "A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy", INTERNATONAL TEST CONFERENCE, INTERNATONAL TEST CONFERENCE 2003 PROCEEDINGS, September 30, 2003, p.393-402

  By the way, in a conventional memory test apparatus, an analysis processing unit having a processor such as a CPU (Central Processing Unit) is provided for each test unit. For this reason, the conventional memory test apparatus uses a CPU with relatively low capacity or the like as the analysis processing unit to reduce the cost. However, when using a CPU or the like having a low computing capability, a software development environment that can be used in the latest general-purpose CPU cannot be used, which increases the burden on the program developer. Also, if it takes time to analyze a repair solution for only one CPU among a plurality of CPUs analyzing in parallel, the other CPUs must wait without performing the next process, Processing efficiency cannot be improved.

  Accordingly, an object of the present invention is to provide a test apparatus that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims. The dependent claims define further advantageous specific examples of the present invention.

According to the first aspect of the present invention, there is provided a test apparatus for testing a plurality of memories under test, each of which is provided corresponding to each memory under test, and a test signal for testing the corresponding memory under test is provided. A plurality of test signal supply units for supplying to the memory under test and the corresponding test memory are provided, and the data read from the corresponding memory under test according to the test signal does not match the expected value. A plurality of defect detectors for detecting a failure of the memory under test, and a fail provided for each memory under test, and a failure for specifying a defective memory cell in the memory under test detected by the defect detector A plurality of fail memories for storing information and a fail information stored in the fail memory are provided for each memory under test. Fail information of the memory under test in the group provided in correspondence with each group of a plurality of buffer units for transferring DMA (Direct Memory Access) to the memory and two or more memory under test, and transferred to the buffer memory A plurality of analysis processes for obtaining a repair solution for repairing a failure of the memory under test by replacing a defective storage cell in the memory under test with any spare cell of the memory under test based on And a plurality of hardware analysis units that are provided corresponding to the respective memories under test and that obtain a repair solution by hardware processing based on the fail information stored in the fail memory. Are repaired by the hardware analysis unit corresponding to the memory under test in the corresponding group. Provided is a test apparatus that obtains a repair solution by software processing on the condition that it is not obtained .

The buffer unit is stored in the fail memory on condition that the detection unit detects whether or not the fail information is stored in the fail memory by polling and the detection unit detects that the fail information is stored in the fail memory. And a DMA unit that DMA-transfers the fail information to the buffer memory.
The buffer unit may notify the processor in the analysis processing unit corresponding to the group to which the memory under test belongs by an interrupt that the fail information about the memory under test has been DMA transferred to the buffer memory.

  The above summary of the invention does not enumerate all the necessary features of the present invention, and sub-combinations of these feature groups can also be the invention.

  According to the present invention, repair solutions for a plurality of memories under test can be efficiently calculated.

  Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the scope of claims, and all combinations of features described in the embodiments are included. It is not necessarily essential for the solution of the invention.

  FIG. 1 shows a configuration of a test apparatus 20 according to the present embodiment. The test apparatus 20 tests a plurality of memories under test 10 simultaneously. Then, the test apparatus 20 efficiently calculates a repair solution for replacing the defective memory cell with the spare cell for each memory under test 10 based on the test results. In this embodiment, each memory under test 10 may correspond to the entire semiconductor device, or may correspond to a block obtained by dividing the storage area in the chip of the semiconductor memory.

The test apparatus 20 includes a plurality of test units 21, a plurality of buffer units 22, a plurality of analysis processing units 23, and a host control unit 24.
The plurality of test units 21 are provided corresponding to each of the plurality of memories under test 10 to be tested together. Each test unit 21 includes a test signal supply unit 31, a defect detection unit 32, a fail memory 33, and a hardware analysis unit 34.

  The test signal supply unit 31 supplies a test signal for testing the corresponding memory under test 10 to the memory under test 10. The defect detection unit 32 detects a defect of the memory under test 10 when the data read from the corresponding memory under test 10 according to the test signal does not match the expected value. Specifically, the defect detection unit 32 detects a defective memory cell from among a large number of memory cells included in the memory under test 10. The defect detection unit 32 writes fail information that identifies the detected defective memory cell in the corresponding fail memory 33. The fail memory 33 stores the fail information of the memory under test 10 written by the defect detection unit 32. The hardware analysis unit 34 calculates a repair solution based on the fail information stored in the corresponding fail memory 33. The hardware analysis unit 34 does not include a processor such as a CPU that performs arithmetic processing by executing software, and calculates a repair solution using dedicated hardware.

  The buffer unit 22 is provided corresponding to each memory under test 10 and transfers the fail information stored in the corresponding fail memory 33 in the corresponding test unit 21 to the internal buffer memory by DMA (Direct Memory Access). To do.

The analysis processing unit 23 is provided for each group of two or more memories under test 10. The analysis processing unit 23 reads fail information from the buffer unit 22 for the plurality of memories under test 10 constituting the group. Then, the analysis processing unit 23 calculates each repair solution for the plurality of memories under test 10 constituting the group based on the read fail information. The analysis processing unit 23 includes a processor such as a CPU, and calculates a repair solution by software processing using the processor. When the hardware analysis unit 34 is provided, the analysis processing unit 23 may calculate a repair solution that cannot be obtained by the hardware analysis unit 34. The analysis processing unit 23 may take over the calculation for the memory under test 10 that has not ended the calculation when the hardware analysis unit 34 does not end the calculation within the specified time.
The host control unit 24 controls and manages the entire test apparatus 20.

  Such a test apparatus 20 feeds back the repair solution to the corresponding memory under test 10 by setting the repair solution obtained by the hardware analysis unit 34 and the analysis processing unit 23 in the memory under test 10. When the repair solution is set, the memory under test 10 replaces the access destination from the defective storage cell to the spare cell when there is an access such as data writing or reading to the defective storage cell. Can do.

FIG. 2 shows a flow of defect detection processing by each test unit 21 of the test apparatus 20.
First, the test signal supply unit 31 and the defect detection unit 32 detect a defective memory cell in the corresponding memory under test 10 and obtain fail information for specifying the defective memory cell (step S11). Subsequently, the test signal supply unit 31 and the defect detection unit 32 write fail information in the fail memory 33 (step S12). Subsequently, the fail memory 33 reads the stored fail information by DMA transfer and transfers it to the buffer unit 22 (step S13).

  Subsequently, the memory under test 10 which is a target for detecting defective memory cells is replaced with a new memory under test 10 and connected to each test unit 21 (step S14). Thereafter, each test unit 21 returns to step S11 again, and performs memory detection of a defective memory cell for the new memory under test 10. As described above, the test unit 21 repeats the processing from step S11 to step S14.

FIG. 3 shows a block configuration of the buffer unit 22.
Each buffer unit 22 includes a bus control unit 41, a bus bridge 42, a buffer memory 43, a detection unit 44, and a DMA unit 45. The bus control unit 41 converts the format of data transferred between the bus to which the fail memory 33 is connected and the internal bus of the buffer unit 22. The bus bridge 42 controls data transmission / reception with the analysis processing unit 23 to which the buffer unit 22 is connected. The buffer memory 43 stores the fail information transferred from the corresponding fail memory 33.

  The detecting unit 44 confirms whether or not the fail information is stored in the fail memory 33 by polling the test unit 21. The detection unit 44 notifies the DMA unit 45 of the timing at which the fail information stored in the fail memory 33 is DMA-transferred from the fail memory 33 to the buffer memory 43. After receiving the transfer timing notification from the detection unit 44, the DMA unit 45 DMA-transfers the fail information stored in the fail memory 33 from the fail memory 33 to the buffer memory 43. In addition, after the DMA transfer of the fail information to the buffer memory 43, the detection unit 44 notifies the processor in the analysis processing unit 23 by interruption that the fail information is stored in the buffer memory 43.

FIG. 4 specifically shows the flow of processing of the buffer unit 22.
The detection unit 44 polls the corresponding test unit 21 and confirms the status of the test unit 21 (step S21). For example, the detection unit 44 reads data written in a predetermined register of the test unit 21 and confirms the status of the test unit 21. When it is confirmed that the fail information is stored in the fail memory 33 (YES in step S22), the detection unit 44 gives a transfer start instruction to the DMA unit 45 (step S23). When it is confirmed that the fail information is not stored in the fail memory 33, the detection unit 44 returns to step S21 after a predetermined time and polls again (NO in step S22).

  Subsequently, when receiving a transfer start instruction from the detection unit 44, the DMA unit 45 reads the fail information from the fail memory 33 and performs DMA transfer to the buffer memory 43 (step S24). Specifically, the DMA unit 45 burst-transfers data stored in a predetermined storage area of the fail memory 33 to the buffer memory 43.

When the DMA transfer of the fail information to the buffer memory 43 is completed, the DMA unit 45 subsequently notifies the processor in the analysis processing unit 23 corresponding to the group to which the memory under test 10 belongs by an interruption. Notification is made (step S25). When the processor in the analysis processing unit 23 is notified of the end of transfer by an interrupt, the processor accesses the buffer unit 22 that has notified the interrupt, and stores the fail information stored in the buffer memory 43 of the buffer unit 22. Is read (step S26). The analysis processing unit 23 calculates a repair solution for the corresponding memory under test 10 based on the read fail information. When the detection unit 44 determines that reading of the fail information by the analysis processing unit 23 is completed (step S27), the detection unit 44 returns to step S21 again to perform polling.
As described above, the buffer unit 22 can sequentially transfer the fail information from the fail memory 33 to the analysis processing unit 23 by repeating the processing from step S21 to step S27.

  According to the test apparatus 20 as described above, the analysis processing unit 23 is provided for each group of two or more memories 10 to be tested. For this reason, according to the test apparatus 20, even if a high-speed processor is applied to the analysis processing unit 23, the cost of the entire apparatus can be reduced. Therefore, according to the test apparatus 20, since a high-speed processor can be used, a program executed by the analysis processing unit 23 can be easily developed, and a general-purpose operation system that is easy to develop can be provided. It can also be installed.

Further, according to the test apparatus 20, a buffer unit 22 that DMA-transfers fail information from the test unit 21 to the analysis processing unit 23 is provided corresponding to each memory under test 10. For this reason, according to the test apparatus 20, it is possible to reduce the time from when the fail information is stored in the fail memory 33 to when the reading is completed, and to improve the test throughput.
Further, according to the test apparatus 20, the number of the memory under test 10 processed by one analysis processing unit 23 and the combination of the memory under test 10 included in the group may be arbitrary, and the analysis performance of the test apparatus 20 and The test can be performed with an appropriate setting according to the test contents for the memory under test 10 and the like.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above-described embodiment. It is apparent from the scope of the claims that the embodiments added with such changes or improvements can be included in the technical scope of the present invention.

1 shows a configuration of a test apparatus 20 according to the present embodiment. The flow of the defect detection process by each test unit 21 of the test apparatus 20 is shown. The block structure of the buffer part 22 is shown. The flow of processing of the buffer unit 22 is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Memory under test 20 Test apparatus 21 Test unit 22 Buffer part 23 Analysis processing part 24 Host control part 31 Test signal supply part 32 Defect detection part 33 Fail memory 34 Hardware analysis part 41 Bus control part 42 Bus bridge 43 Buffer memory 44 Detection Part 45 DMA part

Claims (3)

A test apparatus for testing a plurality of memories under test,
A plurality of test signal supply units that are provided corresponding to the respective memories under test and supply test signals for testing the corresponding memories under test to the memories under test;
A plurality of detection circuits for detecting a failure of the memory under test when the data read out from the corresponding memory under test according to the test signal does not match an expected value. A defect detection unit of
A plurality of fail memories that are provided corresponding to the respective memories under test and store fail information for specifying defective storage cells in the memories under test detected by the defect detector;
A plurality of buffer units provided corresponding to each of the memories under test, for transferring fail information stored in the fail memory to a buffer memory by DMA (Direct Memory Access);
Based on the fail information of the memory under test in the group provided corresponding to each group of two or more memory under test and transferred to the buffer memory, a failure in the memory under test is determined. A plurality of analysis processing units for obtaining a repair solution for repairing a defect of the memory under test by replacing the memory cell with any spare cell of the memory under test ;
A plurality of hardware analysis units which are provided corresponding to the respective memories under test and obtain the repair solution by hardware processing based on the fail information stored in the fail memory,
The test apparatus that obtains the repair solution by software processing, on the condition that the repair solution is not obtained by the hardware analysis unit corresponding to the memory under test in the corresponding group . The buffer unit is
A detecting unit for detecting by polling whether the fail information is stored in the fail memory;
A DMA unit that DMA-transfers the fail information stored in the fail memory to the buffer memory on the condition that the detection unit detects that the fail information is stored in the fail memory. The test apparatus described. The buffer unit notifies the processor in the analysis processing unit corresponding to the group to which the memory under test belongs by an interrupt that the fail information about the memory under test has been DMA transferred to the buffer memory. The test apparatus according to claim 1 or 2 .

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