JPH02303141A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH02303141A JPH02303141A JP12510289A JP12510289A JPH02303141A JP H02303141 A JPH02303141 A JP H02303141A JP 12510289 A JP12510289 A JP 12510289A JP 12510289 A JP12510289 A JP 12510289A JP H02303141 A JPH02303141 A JP H02303141A
- Authority
- JP
- Japan
- Prior art keywords
- side substrate
- substrate
- support
- reduced
- alloy layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title description 9
- 238000004519 manufacturing process Methods 0.000 title description 8
- 239000000758 substrate Substances 0.000 claims abstract description 80
- 239000002184 metal Substances 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims abstract description 15
- 239000000956 alloy Substances 0.000 abstract description 13
- 229910045601 alloy Inorganic materials 0.000 abstract description 13
- 239000010949 copper Substances 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 7
- 229910052802 copper Inorganic materials 0.000 abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 230000008569 process Effects 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000005275 alloying Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 230000020169 heat generation Effects 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910052788 barium Inorganic materials 0.000 description 1
- DSAJWYNOEDNPEQ-UHFFFAOYSA-N barium atom Chemical compound [Ba] DSAJWYNOEDNPEQ-UHFFFAOYSA-N 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔（既要〕
半導体装置の製造方法に係り、特にＳｏｌ構造基板に形
成する半導体装置の製造方法に関し。DETAILED DESCRIPTION OF THE INVENTION [(Already required)] The present invention relates to a method of manufacturing a semiconductor device, particularly a method of manufacturing a semiconductor device formed on a Sol structure substrate.
各素子の電位の浮遊を抑制し且つ温度上昇を防止するこ
とを目的とし。The purpose is to suppress floating potential of each element and prevent temperature rise.
支持側基板、絶縁層、素子の形成された素子側基板から
なるＳｏｌ構造基板の該支持側基板に。To the supporting side substrate of a Sol structure substrate consisting of a supporting side substrate, an insulating layer, and an element side substrate on which elements are formed.
金属を拡散させて該支持側基板を合金化する半導体装置
の製造方法により構成する。It is constructed by a method of manufacturing a semiconductor device in which the supporting substrate is alloyed by diffusing metal.
本発明は半導体装置の製造方法に係り、特にＳｏｌ構造
基板に形成する半導体装置の製造方法に関する。The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device formed on a Sol structure substrate.
高速、高密度、耐放射線ＬＳＩ用基板として。As a high-speed, high-density, radiation-resistant LSI substrate.
Ｓｉ層／酸化膜／ Ｓ ｉ構造のＳＯｒ措造築造基板用
である。This is for a built-in substrate with a Si layer/oxide film/Si structure.
近年、システムの巨大化、高速化に伴い。In recent years, systems have become larger and faster.
ＬＳＩの集積度、動作速度の向上が要求されている。こ
の要求を満たすため、チップの消費電力が著しく増大し
、素子の発熱による温度上昇をいかにして抑制するかが
、集積度、動作速度の向上にとって大きな問題となって
いる。There is a demand for improvements in the degree of integration and operating speed of LSIs. In order to meet this requirement, the power consumption of the chip increases significantly, and how to suppress the temperature rise due to heat generation of the elements has become a major problem for improving the degree of integration and operating speed.
［従来の技術］
従来、ＬＳＩ基板ではパッケージの外部に冷却機構を付
加することによって素子の発熱による温度上昇を防止し
ている。しかし、素子を形成するＳｉ層と支持側基板の
間に酸化膜のあるＳｏｌ構造基板では、酸化膜の熱伝導
率が小さいので１通常のバルク基板より素子の温度が上
昇しやすく、全体としての熱伝達の効率を向上させるた
めに、素子を形成したあと支持側基板をできるだけ薄く
シて金属のパッケージにダイボンディングすることが行
われる。[Prior Art] Conventionally, in an LSI board, a cooling mechanism is added to the outside of the package to prevent temperature rise due to heat generation of the elements. However, in a Sol structure substrate with an oxide film between the Si layer that forms the element and the support side substrate, the thermal conductivity of the oxide film is low, so the temperature of the element increases more easily than a normal bulk substrate, and the overall In order to improve the efficiency of heat transfer, after forming the device, the supporting substrate is made as thin as possible and die-bonded to the metal package.
素子の温度上昇を防ぐためには、支持側基板の厚さは薄
いほど良いが、 Ｓｉの機械的強度があまり太き（ない
ため、ラップ加工では２００μｍ程度が限界である。In order to prevent a rise in the temperature of the element, the thinner the supporting substrate is, the better; however, since the mechanical strength of Si is not very thick, the limit for lapping is about 200 μm.
さらに薄くして熱抵抗を下げるためには、支持側基板の
機械的強度を高めることが必要である。In order to further reduce the thickness and lower the thermal resistance, it is necessary to increase the mechanical strength of the supporting substrate.
さらに、支持側基板の熱伝導率を上げることも有効であ
る。Furthermore, it is also effective to increase the thermal conductivity of the supporting substrate.
また、Ｓｏｌ構造では、各素子が絶縁層で支持基板と完
全に分離されるため、各素子が電気的に浮遊状態になる
。このため、外部若しくは内部ノイズによって各素子が
誤動作することがある。これを防止するためには、支持
側基板の電気伝導性を高め、支持側基板との容量性結合
により各素子の電位を固定する必要がある。Furthermore, in the Sol structure, each element is completely separated from the support substrate by an insulating layer, so each element is in an electrically floating state. Therefore, each element may malfunction due to external or internal noise. In order to prevent this, it is necessary to increase the electrical conductivity of the supporting substrate and fix the potential of each element through capacitive coupling with the supporting substrate.
ところが、支持側基板の機械的強度、熱伝導率。However, the mechanical strength and thermal conductivity of the supporting substrate.
電気伝導率については、はとんど検討されていない。Electrical conductivity has hardly been studied.
従って１以上述べた問題点を踏まえてＳＯＩ構造の特徴
を発揮して高性能のＬＳＩを実現するためには、支持側
基板に大きな電気伝導率、大きな熱伝導率、大きな機械
的強度を実現することが要求される。Therefore, in order to take advantage of the features of the SOI structure and realize a high-performance LSI based on the problems mentioned above, it is necessary to realize high electrical conductivity, high thermal conductivity, and high mechanical strength for the supporting substrate. This is required.
本発明は、これらの問題点に応えるＳｏｌ構造を有する
半導体装置の製造方法を提供することを目的とする。An object of the present invention is to provide a method for manufacturing a semiconductor device having a Sol structure that addresses these problems.
〔課題を解決するための手段］
上記課題は、支持側基板１．絶縁層２．素子の形成され
た素子側基板３からなるＳＯ■構造基板の該支持側基板
１に、金属を拡散させて該支持側基板１を合金化する半
導体装置の製造方法によって解決される。[Means for solving the problem] The above problem is solved by the support side substrate 1. Insulating layer 2. The problem is solved by a method of manufacturing a semiconductor device in which metal is diffused into the supporting substrate 1 of an SO2 structure substrate consisting of an element-side substrate 3 on which an element is formed, and the supporting substrate 1 is alloyed.
〔作用］
本発明では、支持側基板ｌに金属を拡散することによっ
て支持側基板１を合金化し、支持側基板１の電気伝導率
、熱伝導率２機械的強度を向上させている。[Function] In the present invention, the supporting substrate 1 is alloyed by diffusing metal into the supporting substrate 1, thereby improving the electrical conductivity, thermal conductivity 2, and mechanical strength of the supporting substrate 1.
機械的強度を向上させることにより、支持側基板ｌを薄
層化することができる。このことは熱伝導率の向上と相
まって素子から発生する熱を除去する作用を効果的にす
る。By improving the mechanical strength, the supporting substrate l can be made thinner. This, combined with the improvement in thermal conductivity, makes the effect of removing heat generated from the element more effective.
電気伝導率の向上は素子が電気的に浮遊状態になること
を抑制する作用を持つ。Improving electrical conductivity has the effect of suppressing the element from becoming electrically floating.
さらに、支持側基板１に金属を拡散する工程は素子側基
板３に素子を形成した後に行っているので、素子側基板
３がその金属に汚染される心配がない。もし、素子形成
前に支持側基板１に金属を拡散する工程を行うと、素子
形成のプロセスで素子側基板３がその金属に汚染される
おそれがある。Further, since the step of diffusing metal into the support side substrate 1 is performed after forming the elements on the element side substrate 3, there is no fear that the element side substrate 3 will be contaminated with the metal. If a step of diffusing metal into the support-side substrate 1 is performed before element formation, there is a risk that the element-side substrate 3 will be contaminated with the metal during the element formation process.
第１図（ａ）乃至（ｅ）は本発明の詳細な説明するため
の図であり１１は支持側基板、ｌａは厚さを滅じた支持
側基板、２は絶縁層、３は素子の形成された素子側基板
、４は金属層、５は合金層、５ａは厚さを滅じた合金層
を表す。1(a) to (e) are diagrams for explaining the present invention in detail, 11 is a support side substrate, la is a support side substrate with reduced thickness, 2 is an insulating layer, and 3 is an element. In the formed element side substrate, 4 is a metal layer, 5 is an alloy layer, and 5a is an alloy layer with reduced thickness.
以下、第１図（ａ）乃至（ｅ）を参照しながら実施例に
ついて説明する。Examples will be described below with reference to FIGS. 1(a) to 1(e).
第１図（ａ）参照
表面に絶縁層２としてＳｉＯ□膜の形成された２枚の６
インチＳｉウェハを張り合わせた支持側基板１゜絶縁層
２．素子側基板３からなるＳＯＩ構造基板の素子側基板
３に９通常のプロセスでＬＳＩを形成する。FIG. 1(a) Two 6 sheets with a SiO□ film formed as an insulating layer 2 on the reference surface.
Support side substrate 1° insulating layer 2. inch Si wafer pasted together. 9. An LSI is formed on the element side substrate 3 of the SOI structure substrate consisting of the element side substrate 3 by a normal process.
各部の厚さは次の如（である。The thickness of each part is as follows.
１、支持側基板（Ｓｉ） ０．６ ｍｍ２、絶
縁層（ＳｉＯｚ） １ ／／ｍ３、素子側基
板（Ｓｉ） ０．６ ｍｍ第１図（ｂ）参照
支持側基板ｌを、厚さが０．３ｍｍ程度になるまでラッ
プする。１ａは０．３ｍｍ程度に厚さを滅じた支持側基
板を表す。1. Supporting side substrate (Si) 0.6 mm2, Insulating layer (SiOz) 1 // m3, Element side substrate (Si) 0.6 mm See Figure 1(b) Supporting side substrate l, thickness 0 .Wrap until it is about 3mm thick. 1a represents a support side substrate whose thickness has decreased to about 0.3 mm.
第１図（ｃ）参照
厚さを減じた支持側基板ｌａ上に銅（Ｃｕ）を約２μｍ
の厚さに蒸着し、金属層４を作る。Figure 1 (c) Copper (Cu) is deposited to a thickness of approximately 2 μm on the support side substrate la with the reference thickness reduced.
The metal layer 4 is formed by vapor deposition to a thickness of .
第１図（ｄ）参照
４００ ’Ｃ，１０時間の熱処理を行う。銅（Ｃｕ）は
厚さを滅した支持側基板１ａに拡散して支持側基板１ａ
のＳｉと合金化し、厚さを滅じた支持側基板１ａはＳｉ
とＣｕの合金層５となる。Refer to FIG. 1(d), heat treatment is performed at 400'C for 10 hours. Copper (Cu) is diffused into the support side substrate 1a whose thickness has been reduced and becomes the support side substrate 1a.
The support side substrate 1a is alloyed with Si and its thickness is reduced.
and Cu form an alloy layer 5.
第１図（ｅ）参照
合金層５を厚さが０．１ｍｍ程度になるまでラッピング
することにより、厚さを減じた合金層５ａを形成する。By lapping the reference alloy layer 5 in FIG. 1(e) until the thickness becomes about 0.1 mm, an alloy layer 5a with a reduced thickness is formed.
このラッピングの際１合金層５の形成により支持側基板
の機械的強度が上がっているので、破壊することはない
。During this lapping, the mechanical strength of the supporting substrate is increased due to the formation of the first alloy layer 5, so that it will not break.
その後、チップに切断し、パッケージにグイポンディグ
する。Then, cut into chips and dig into packages.
このようにして、熱伝導率、電気伝導率がともに高い支
持側基板を持つＳＯＩ構造の半導体装置が実現する。In this way, a semiconductor device with an SOI structure having a supporting substrate with high thermal conductivity and high electrical conductivity is realized.
なお、厚さを減じた支持側基板１ａ上に蒸着する金属と
して、銅（Ｃｕ）の他に金（Ａｕ）、 バリウム（Ｂ
ａ）等４５０“Ｃ以下の温度でシリコン（Ｓｉ）と合金
化する金属を用いることができる。合金化のための熱処
理温度が４５０°Ｃを超えると、配線のＡ１がｓｉと反
応して断線したり、ｐｎ接合を破壊したりするので望ま
しくない。In addition to copper (Cu), gold (Au) and barium (B
a) Metals that alloy with silicon (Si) at temperatures below 450°C can be used. If the heat treatment temperature for alloying exceeds 450°C, A1 of the wiring will react with Si and break. This is undesirable because it may damage the pn junction.
また、厚さを滅じた支持側基板１ａ上に泪を茎着すると
き、その支持側基板１ａを４５０“Ｃ以下に加熱し、蒸
着と合金化を同時に行ってもよい。Further, when depositing the resin on the supporting substrate 1a whose thickness has been reduced, the supporting substrate 1a may be heated to 450"C or less, and vapor deposition and alloying may be performed simultaneously.
（発明の効果〕
以上説明した様に１本発明によれば７支持側基板の機械
的強度を増大して支持側基板のラッピングによる薄層化
を可能にし、さらに支持側基板の熱伝導率を増大して素
子から発生する熱の流れに対する熱抵抗を低減し、素子
の温度上昇を防ぐことができる。(Effects of the Invention) As explained above, according to the present invention, the mechanical strength of the supporting substrate 7 can be increased, the supporting substrate can be thinned by wrapping, and the thermal conductivity of the supporting substrate can be increased. It is possible to reduce the thermal resistance to the increased flow of heat generated from the element and prevent the temperature of the element from rising.
また、支持側基板の電気伝導率の向上により。Also, due to improved electrical conductivity of the supporting substrate.
各素子の電位の浮遊を抑制することができ、ノイズによ
る素子の誤動作を防ぐことができる。It is possible to suppress floating potential of each element, and prevent element malfunction due to noise.
第１図は実施例
である。図において。
１は支持側基板であってシリコン基板。
１ａは厚さを減じた支持側基板。
２は絶縁層であって５ｉＯｚ膜。
３は素子の形成された素子側基板であってシリコン基板
。
４は金属層であってＣｕＮ。
５は合金層。
５ａは厚さを減じた合金層
（ｅ）
曳 施 例
第 １ 図FIG. 1 shows an example. In fig. 1 is a support side substrate, which is a silicon substrate. 1a is a support side substrate with reduced thickness. 2 is an insulating layer, which is a 5iOz film. 3 is an element side substrate on which elements are formed, which is a silicon substrate. 4 is a metal layer made of CuN. 5 is an alloy layer. 5a is an alloy layer with reduced thickness (e) Figure 1
Claims (1)
子側基板（３）からなるＳＯＩ構造基板の該支持側基板
（１）に、金属を拡散させて該支持側基板（１）を合金
化することを特徴とする半導体装置の製造方法。A metal is diffused into the support side substrate (1) of the SOI structure substrate consisting of a support side substrate (1), an insulating layer (2), and an element side substrate (3) on which an element is formed. ) is alloyed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1125102A JP2775848B2 (en) | 1989-05-18 | 1989-05-18 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1125102A JP2775848B2 (en) | 1989-05-18 | 1989-05-18 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02303141A true JPH02303141A (en) | 1990-12-17 |
| JP2775848B2 JP2775848B2 (en) | 1998-07-16 |
Family
ID=14901901
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1125102A Expired - Lifetime JP2775848B2 (en) | 1989-05-18 | 1989-05-18 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2775848B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007514321A (en) * | 2003-12-10 | 2007-05-31 | ザ、リージェンツ、オブ、ザ、ユニバーシティ、オブ、カリフォルニア | Low crosstalk circuit board for mixed signal integrated circuits |
| US7541644B2 (en) | 2003-05-23 | 2009-06-02 | Renesas Technology Corp. | Semiconductor device with effective heat-radiation |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60186036A (en) * | 1984-03-05 | 1985-09-21 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor substrate and manufacture thereof |
-
1989
- 1989-05-18 JP JP1125102A patent/JP2775848B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60186036A (en) * | 1984-03-05 | 1985-09-21 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor substrate and manufacture thereof |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7541644B2 (en) | 2003-05-23 | 2009-06-02 | Renesas Technology Corp. | Semiconductor device with effective heat-radiation |
| JP2007514321A (en) * | 2003-12-10 | 2007-05-31 | ザ、リージェンツ、オブ、ザ、ユニバーシティ、オブ、カリフォルニア | Low crosstalk circuit board for mixed signal integrated circuits |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2775848B2 (en) | 1998-07-16 |
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