JPH02302072A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To align a plurality of laminated plate-like objects (e.g. a semiconductor substrate) precisely and to combine desired positions each other by forming an optically transparent window for alignment to a bottom of a recessed part which is formed at a part of a platelike object having a semiconductor layer containing a semiconductor device, by carrying out optical alignment through the window, and by combining a plurality of platelike objects mutually. CONSTITUTION:Recessed parts 52, 53, 54 for alignment are provided to substrates 101, 102, 103, 104 and optical transparent windows W11, W12, W13, W14, W21, W22, W23, W24 and W31, W32, W33, W34 are provided to bottoms thereof. A beam of B1 is detected at a position of D1, a beam of B2 at a position of D2, and a beam of B3 at a position of D3 by using parallel light such as laser light, and then, alignment is carried out. Thereafter, the substrate 104 and the substrate 103 are combined first, and its three-dimensional structure is fixed. Then, the substrate 103 and the substrate 102 are combined, its three- dimensional structure is fixed, and the substrate 102 and the substrate 101 are combined and fixed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method of manufacturing a semiconductor device comprising a laminated plate-like object.

(Prior art) As a conventional semiconductor device consisting of a laminated plate-like object,
For example, there are three-dimensional devices and semiconductor acceleration sensors.

First, as an example of three-dimensional devices, see "International Electron Device Meeting Technical Digest (International.

Electron Devices Meeting
Technical Digest.

1984, p816 M, Yasumoto et al.
romisin< newfabrication p
rocess developed for 5tac
There is a method described in kedLSI's) J.

In this method, two wafers are pasted together and devices on the upper and lower wafers are bonded and fused using wire connections.

Further, as a general example, there is a laminated substrate type three-dimensional structure as described in "Nikkei Micro Device, July 1985 issue, pages 175 to 192."

On the other hand, as an example of a semiconductor acceleration sensor made of a laminated plate-like object, "International Conference on Solid State Sensors and Actuators (Int.
organization'al conference
5 solid 5tate 5 sensors an
d Actuators 1987p 112H
, Nakamura et al. “Novel Electroc
chemical micro machining and
It,s Application for S
em1conductor Acceleration
There is one described in 5ensor I C"J.

FIG. 6 is a sectional view of the semiconductor acceleration sensor described above.

FIG. 6 shows a three-layer stack structure in which a stopper part 91 is formed by processing Si wafer chips on the upper and lower parts of the cantilever 92 in an IC chip 90 including a semiconductor acceleration sensor having a cantilever part 92. ing.

In the above example, in order to prevent part of the cantilever from being damaged due to excessive acceleration, wafer chips that function as stoppers and are formed from separate Si wafer chips are installed at the top and bottom of the cantilever. An IC chip with a bonded Si wafer chip is mounted in a ceramic package.

[Problem to be solved by the invention]

In the conventional laminated substrate type three-dimensional configuration as described above,
Align multiple stacked substrates at desired positions,
When realizing a configuration in which double the amount of transmission is performed between one board and another by fusing them at a predetermined electrode part, precisely align the facing bonding parts between multiple boards. The problem is that there is no practical manufacturing method for precisely aligning and bonding the wiring pattern, etc. of one board and the opposing wiring connection part of another board with IC precision. There was a point.

In addition, in the conventional laminated substrate type semiconductor acceleration sensor as described above, it is still difficult to precisely align the substrates, so there is a substrate that serves as the upper stopper, a substrate for the semiconductor acceleration sensor body, and a substrate that serves as the lower stopper. The problem is that it is difficult to laminate and bond and fuse the opposing joints of each other with precise alignment, and there is no manufacturing method that can perform high-precision alignment with good productivity. there were. The present invention has been made to solve the problems of the prior art as described above, and is a method for aligning a plurality of laminated plate-like objects (for example, semiconductor substrates, etc.) and bonding desired parts to each other. The purpose is to provide a highly accurate and practical manufacturing method.

[Means to solve the problem]

In order to achieve the above object, the present invention is constructed as described in the claims.

That is, in the present invention, a concave portion is formed in each plate-like object to be stacked, and small optical transmission windows of a predetermined shape for alignment are formed on the bottom surfaces of the four parts, that is, the thinner part of the plate-like object. It is formed using IC pattern technology. And a plurality of plate-shaped objects that formed such optically transparent windows.

An optical method using the above-mentioned optical transmission window (details will be described later; for example, irradiating a parallel light beam onto a plurality of laminated plates and adjusting the position of each plate so that the parallel light beam passes through the optical transmission window of each plate) After being aligned by the method, the plurality of plate-like objects are bonded to each other by adhesion or fusion, thereby forming a stacked laminated structure.

〔Example〕

FIG. 1 is a sectional view showing one embodiment of the present invention. 1st
In the figure, a substrate 101, a substrate 102, a substrate 103, and a base 104 are substrates each made of a semiconductor wafer including elemental devices constituting a three-dimensional device. A three-dimensional device, a device constituting a three-dimensional IC, etc. are formed in each of the above-mentioned substrates. It is possible to construct a three-dimensional device in a hybrid manner using a plate-like object such as a wafer, and FIG. 2 illustrates an example of the structure including a method for connecting element devices.

Hereinafter, before explaining the positioning method and structure of the present invention, a substrate for a three-dimensional device having a recessed portion will be explained based on FIGS. 2 and 3.

FIG. 2 is an enlarged cross-sectional view of a portion of the three-dimensional device similar to FIG. In FIG. 2, a semiconductor substrate 10 is shown on the top.
There is 1. This semiconductor substrate 101 has, for example, an SOI semiconductor structure, and has etched holes (recesses) 22 formed therein. Further, the substrate semiconductor portion IA other than the etch hole 22 also has an isolated structure. Further, a field oxide film 2 is provided on the surface of the semiconductor substrate 101,
Further, an insulating film 3 is provided on the inner surface of the etched hole 22 for the purpose of edging the recess. Furthermore, two MOS transistors, for example, are formed in the upper semiconductor rds 4 and 13 of the SO structure.

Further, in order to transmit signals between the bottom surface of the recess and the upper part of the semiconductor substrate 101, a low resistance region 6 made of low resistance n'' polysilicon insulated from the surroundings by an N film 5 is formed. , wiring electrodes 7A, 7 are provided on the back side of the recess.
B is provided.

The MOS transistor formed on the right side of the semiconductor substrate 101 has a source 8, a drain 9, and a silicon gate 11, and a signal on the back side of the substrate is transmitted to a low resistance region 6.
The signal is transmitted to the gate 11 via the aluminum wiring #1A, 12A, 12B.

On the other hand, another MOS transistor is formed in the semiconductor M4.13 on the SOI substrate on the left side of the semiconductor substrate 101 in the drawing. This S.

One layer 14 of the mechanical structure is formed of an oxide film or the like.

The MOS transistor on the left side is composed of an n+ source 15, a drain 16, a gate electrode 18, a so-sumi electrode 19, and an upper type m20 of the drain. The drain 16 described above is formed of n+ poly-Si or deep diffusion, and penetrates through the semiconductor layer 13.4 and the first layer 14 to reach the bottom surfaces of the four parts on the back surface.

The output of this transistor is connected to both the upper fiLm20 and the back electrodes 21A and 21B of the recess.

The semiconductor substrate 101 (upper substrate) as described above is
It is combined with one semiconductor substrate 102 (lower substrate) at a predetermined position to form part of a three-dimensional device.

The bonding state near the recess 22 will be further explained below.

``The lower substrate 102 includes a CMOS inverter. This lower substrate 102 consists of a plate with an n bulk 26 and a p
A well 27 and a P+ well contact 29 are formed. On the other hand, a substrate contact 30, a p+ source 31, and a p+ drain 32 are formed in the n-type substrate portion. Also,
The P well 27 has a drain 33. An n source 34 is formed, poly-Si gates 35 and 36 are set for p-channel and n-channel transistors, and gate insulating films 37 and 38 are formed to have a predetermined thickness. An inter-wiring insulating film 39 is also provided. In addition, Vss electrode 41, VDD electrode 40, CMO8 output electrode 42. C
MOS gate input electrode 43A and the like are formed by a normal method.

As shown in FIG. 2, an upper substrate 101 and a lower substrate 102
One example of a method for fusing these at a desired electrode portion is the method described in "International Electron Device Meeting Technical Digest 1984. pat 6" shown as the above-mentioned conventional example.

FIG. 2 shows a case in which a laminated structure is formed by a fused layer method, which is substantially the same as the method described in the above-mentioned literature.

In the above method, first, two layers of A are placed on the A2 electrode.
Form the u/Ti layer. Next, this Au/Ti layer is coated with a polyimide layer to the same height as the electrode, and after etching with plasma 02, the Au/Ti electrode is exposed and planarization is also performed at the same time.

Such an electrode structure is formed on the back surface of the upper substrate 101 and the main surface of the lower substrate 102 shown in FIG.

Next, the above two substrates are aligned at desired positions and fused together by thermocompression bonding.

For example, when fusing the electrode 21B on the back surface of the upper substrate 101 and the gate electrode 43A on the lower substrate 102, an Au alloy/146U whose level matches that of polyimide R1J44 is formed on the AQ electrode 21B, Similarly, lower board 1
An Au alloy layer 46L having the same level as the polyimide layer 45 is also formed on the gate electrode 43A of No. 02. When fusing the semiconductor substrate 101 and the semiconductor substrate 102 at other places, for example, at the electrode 7B and the electrode 43B, by forming the Au alloy layers 47U and 47L and thermocompression bonding, multiple points can be welded at the same time. can do. In addition, polyimide, 1
944.45 is effective in both stress relief and insulation. Furthermore, if the manufacturing method is improved, it is possible to fill the recess 22 with polyimide.

In the configuration shown in FIG. 2 as described above, the upper substrate 101
The CMOS common gate 43A in the lower substrate 102 can be opened by the drain output of the N-channel MOS transistor.

Further, although it is not shown where the lower wiring electrode 43B is connected in the figure, for example.

When this electrode is connected to the V ou of another CMOS inverter on the lower substrate 102, the V of the lower wiring electrode 43B. Due to the high output power, the gate electrode 11 of the N-channel MOS transistor on the right side of the upper substrate 101
You can move your heel.

In the configuration of the present invention, the method of bonding or fusing the upper and lower substrates is not particularly limited, and other bonding or fusing methods may be used.

The basic configuration of the present invention is 7B-7A-6-1 in FIG.
As shown in the path 2B-12A, a connection means between the main surface and the back surface of the substrate via a recess formed by the low resistance region 6, or an active device having three or more active terminals using the same recess ( In the example in Figure 2, source 1"5, drain 1"
6. Connection means for connecting the main surface and the back surface of the substrate in a form including a switch mechanism through one active terminal (drain in FIG. 2) of a MOS transistor having a gate 18. As will be described later, this method is characterized by a method of optically aligning via an optical transmission window provided in a recess for alignment.

The diversity of the means for connecting the main surface and the back surface of the substrate based on the structure of the present invention as described above is as follows:
It can be effectively used when configuring dimensional devices.

In addition, in FIG. 2, isolation by the insulating film 5 is used as a means to isolate the low resistance region 6 from the surroundings, but if the surrounding voltage distribution is appropriately selected and designed, reverse bias isolation of the n 4P p junction can be achieved. It's not that you can't use it.

In addition, as shown in the embodiment shown in FIG.
It does not matter if active device terminals such as the drain output of a transistor are mixed together.The main point is that the voltages applied to each terminal can be independently set using the contact terminals on the bottom of the recess provided on the back of the substrate. It will be good if it is satisfied.

Alternatively, one substrate may have a plurality of recesses, and each recess may include a plurality of recess rear surface terminals as described above.

FIG. 3 is a plan view of a case where there are multiple recesses in one board and there are a plurality of recessed back terminals in the recesses, as seen from the back of the board. shows.

In FIG. 3, 8x2 contact terminals 51 are provided in each of the recesses A, B, C, and D.

With this configuration, 16-bit signals can be transferred between the main surface and the back surface of the substrate.

In the example shown in FIG. 3, there are four recesses each having a 16-bit terminal. Among these, for example, all of the recesses A may be coupled by low resistance regions. Further, for example, all of the recesses B may be formed by one terminal of an active device such as the drain terminal of a MoS transistor.

Also, when considering the exchange of upper and lower signals with multiple boards,
As considered in the embodiment of FIG. 2, there is a signal flow that does not enter from the top and a signal flow that goes from the bottom to the top. therefore,
The recesses C and D in FIG. 3 may be recesses that respectively share and transmit the flow of these signals.

Further, as shown in FIG. 1, when a plurality of substrates are stacked and used, the concave portions of the substrates that are in contact with each other are set at shifted positions so that they do not overlap. In FIG. 1, the recesses (etched holes) at positions B1→D1, B2→D2, and B3→D3 are provided for alignment and scribing using the method of the present invention, and will be described later. explain.

With the four-layer configuration shown in Figure 1, the 2x8 bits of the etch channel switch connector shown in Figure 3 can be
, B, C, and D, the 32-bit downward signal (signal from the upper board to the lower board) and the 32-bit upward signal (signal from the lower board to the upper board) can be processed in parallel at the same time. It is possible to effectively utilize the characteristics of three-dimensional stacked devices.

The semiconductor device of the present invention is effective when a three-dimensional device is formed by fusing a plurality of substrates as described above.

Furthermore, in the embodiments described so far, the case where a Si substrate and an SOI substrate were used as the semiconductor substrate was exemplified, but Si on Glass substrate and 5OS (Si
Even in the case of a (on 5apphire) substrate, the structure of the present invention can be created using the Si layer portion. In addition, for G1ass substrates and Sapphire substrates, holes are made on the back side of the substrates by etching, RIE, etc.
Recesses up to the layers can be provided.

Figure 2 shows the case of an SOI (Si-8in, -8i) substrate, but in addition, a monolithic three-layer (sometimes n-layer) three-dimensional device has already been fabricated using methods such as laser annealing, such as a 5ion Si substrate. The configuration of the present invention can be applied even to the following. In this case, if the bottom substrate of an nR monolithic multilayer three-dimensional device is thick, the back surface of the bottom substrate can be etched to form a recess, so that the semiconductor substrate with the features of the present invention can be used. It can be considered.

Therefore, the semiconductor substrate in the description of the present invention can be broadly defined as a substrate containing a semiconductor layer in all cases as described above.

According to such a configuration method, a signal transmission area is provided at the bottom of the recess that reaches from the main surface side of the substrate to the back surface, and the transmission of No. 48 can be performed between the main surface and the back surface via this area. As a result, various effects such as those described below can be obtained.

(1) It has become possible to transmit signals between the back side of the board and the main surface of the board, which was previously difficult. This signal transmission is simple and basic, in addition to wiring connections using low-resistance ohmic regions, and signal transmission and control using the active terminals of active differential chairs, such as the drains of Mos + - transistors, using the same recess. , it can also be used in common with the switch function.

(2) Problems with conventional highly integrated planar ICs, namely:
It is possible to improve problems such as: (1) chip size increases, wiring length increases within the chip, causing signal delays; (2) there are many constraints on cell placement and wiring layout; and low zero yield.

Note that metal wiring used in current LSI wiring inevitably has wiring resistance. for example,
There is a problem in that the wiring from the contact 21A at the bottom of the recess 22 to the contact 21B on the back surface of the wafer shown in the embodiment shown in FIG. 1 is longer than in the case of a planar IC in terms of distance.

To solve this problem, it is conceivable to make the thickness of the substrate as thin as possible and to make the wiring material even lower in resistance.

In this way, 3D devices have excellent features that conventional ICs do not have, but the problem with 3D device configurations made of stacked plate-like objects is that the wafers, etc. that make up the structure are not transparent, so when stacking However, there was a problem in that it was difficult to align the substrates with each other. The method of the present invention solves the above problems.

A detailed explanation will be given below based on FIG. 1.

In FIG. 1, substrates 101.102.103.104
is a plate-like object such as a Si wafer.

In addition, in order to effectively align Si chips or Si wafers with each other, it is effective to use a parallel light beam from a laser beam or other light source.
B2 and B3 are parallel light beams set for alignment.

In addition to the above-mentioned recesses for electrical connection between the main surface and the back surface of the substrate (for example, the etched hole 22, etc.), the substrates 101, 102, 103, and 104 each have recesses 52, 53, and 53 for positioning. 54 are provided at their bottoms, i.e. in the thinned area of the substrate, optically transparent windows W1, W1□, W13 . W14 etc. are provided. Further, at other positions on each substrate, optical transmission windows W 2 x -W 22, W2 . , W2. and W3. , WS2, W3. , W3. is provided.

Adjusting the alignment of each wafer or chip so that the alignment light beams such as B1, B2, and B3 pass through the corresponding optical transmission windows (for example, W1□ to W1.) is performed using a mask aligner. It is also possible to configure it using a minute movement mechanism similar to the above.

After alignment, the method of gluing or fusing is the second method described above.
You can use the method described in the previous section.

The order of bonding or fusing is determined by first bonding substrate 104 and substrate 103 and fixing their three-dimensional structure. Next, the substrate 103 and the substrate 102 are bonded, and the three-dimensional structure is fixed and determined. Further, the substrate 102 and the substrate 101 are combined and fixed. The order of fixing and determining the structure is as follows:
It is also possible to start from the substrate 101 in the opposite way to the above.

The reason why such opaque substrates can be overlapped and aligned is that by providing an optical transmission window as described above and using parallel light such as a laser beam, the light beam of B1 is detected at the position of Dl, Similarly, this is based on the fact that the luminous flux of B2 can be detected at the position of B2, and the luminous flux of B3 can be detected at the position of B3. Note that using parallel light such as a laser beam is not affected by the number or thickness of the laminates.
This is to facilitate the setting of the optical system for alignment, and photodetectors (not shown) are provided at the positions D1, B2, and B3.

Further, the above-mentioned optical transmission window for alignment need only have a structure that allows the light beam to pass therethrough.

For example, in FIG. 2, Wl, W2. W3 shows the case of small holes with a predetermined pattern, but instead of small holes, 5in2. Of course, an optical transmission window constructed using a transparent insulating film such as Si3N or the like may also be used. Furthermore, if the semiconductor is thin, it is possible to configure the semiconductor to transmit the light beam. In this regard, in the present invention, since the optical transmission window is provided on the bottom surface of the recess, that is, on the thin part of the substrate,
This part is originally extremely thin, and it is easy to form transparent films, small holes, etc.

As described above, the optical transmission window for positioning in the present invention does not have a specified structure, but may have the function of transmitting the above-mentioned light beam for positioning.

In addition, in FIG. 1, recesses (52 to 54) for positioning are provided separately from the recesses for electrical connection between the main surface and the back surface of the substrate (for example, the etched holes 22, etc.). Although the case where an optical transmission window for positioning is provided at the bottom is illustrated, it is also possible to provide an optical transmission window for positioning in a part of the recess for electrical connection.

Furthermore, if the intention is to improve the functionality of optical alignment, it may be possible to provide each optical transmission window with a micro-optic member such as a micro-lens formed using IC technology. . Further, a parallel light beam for positioning is not an absolute requirement, and depending on the selection of the optical system, a projection light beam from a lens system or the like may be sufficient.

Next, optical alignment windows W1, W2, W3,...W
The position of i and its arrangement on each object on the board will be explained.

From the perspective of mass-producing three-dimensional devices, it is first necessary to align, fix, and bond wafers over large areas, such as wafers, by adhesion or fusion. for example,
Assuming wafer level adhesion and fusion, the line B1→D1 in FIG.

The line B2→D2, the line B3→D3, etc. may be considered to be arranged on the scribe line.

In that case, the region surrounded by the Bl-Dl line and the B2-B2 gland is a three-dimensional device at the chip level. Similarly, the area surrounded by lines B2-B2 and B3-B3 has a three-dimensional hybrid chip configuration in another chip.

By using such wafer-level positioning and fixing by adhesion or fusion, it is possible to manufacture a three-dimensional device having a three-dimensional multilayer plate-like structure with an ultra-high degree of integration, which is highly effective.

A plate-like structure such as such a wafer must have a concave portion for each chip in an appropriate arrangement, and ■ Au
The parts other than the alloy layer are flattened with a polyimide layer, etc. At the same time, the physical properties of the polyimide layer make it easy to create stress relief. The wafer has a convenient structure in which even if pressure is applied to the wafer, the wafer will respond flexibly so that it is unlikely to be damaged.

Further, after fixing a predetermined number of sheets by adhesion or fusion at the wafer level, the plate-like structures (wafers) constituting each layer can be separated using a laser scriber or the like. In addition, since the laser scriber removes the scribed portion by evaporation or other means, the desired portion is removed without transmitting unnecessary stress to each chip of the wafer or the underlying plate-like structure (wafer) that is bonded in the wafer state. It can be cut. In addition, each board 101.102°103
．． If the laser cut height is different for each 104,
It is necessary to vertically align the focal point of the laser beam and the scribe cut position for each substrate. Further, since the scribe position is easily cut by the recess, it is possible to use an ordinary mechanical scriber depending on the case. Furthermore, it is also possible to use a laser scriber and a mechanical scriber in combination depending on the case.

Next, a case where each chip is stacked in a hybrid manner will be described.

The need to stack the plate-like structures shown in FIG. 2 on a chip-by-chip basis arises in the following cases.

In other words, ■ the substrate 101.1 constituting the three-dimensional device;
If the yield of any of the chips such as 02, 103, 104, etc. is poor, it is necessary to strictly align the positions of chips such as 101, 102, 103, 104, etc. on each substrate from the relative relationship of fine devices, optical devices, etc. If there is, then .

In such a case, 1For example, 1B1- in FIG.
It may be considered that Dl to B3-Da is one chip and has already been separated.

In that case, in the chip, W2. in B2-D2. ,
W2 W2. , W24 optical transmission window. If three or more such optical transmission windows are provided in the same chip, alignment can be performed for each chip.

As with the conventional mounting technology, the above-mentioned alignment for each chip is individual and may pose a problem in productivity. However, in the case of a chip having an optical transmission window as in the present invention, the substrates 101, 102, 103,
104 +'7' (7) selection and placement in a predetermined position, and alignment and fusing of each board chip above and below;
It is also possible to have automatic manufacturing and assembly equipment perform the fixing.

That is, in the configuration of the present invention, output light from three or more optical transmission windows in the chip is detected by a photodetector installed at a predetermined position, and a combination of the signals is calculated by an electronic circuit. , the most difficult 101 in this assembly process,
This is because it is possible to determine the optimum conditions for alignment of chips such as 102, 103, and 104.

As mentioned above, in the conventional technology, there were problems in alignment due to the size of the chip, and there were problems in precise alignment, fusing, and fixing in the assembly process, but in the present invention, optical By providing a transparent window and a micro-movement mechanism for each stacked chip, high-precision automated assembly was made possible, which is highly effective.

The method for manufacturing a multilayer substrate three-dimensional device according to the present invention as described above can significantly alleviate the manufacturing problems and constructional difficulties of conventional planar ICs as described below.

(1) Compared to a completely monolithic multilayer three-dimensional structure formed by laser annealing or the like, the bonding or fusion method requires fewer steps, so the manufacturing yield can be increased.

(2) The first board is the sensor IC, the second board is the memory IC
1 By designing the third board as a calculation IC, the fourth board as a comparison IC, etc., and combining them appropriately, it is possible to construct a three-dimensional device with different performance and functions. , the degree of freedom in design can be increased.

Next, as another embodiment of the present invention, a three-dimensional device configuration and manufacturing method of a semiconductor acceleration sensor using the positioning and fusion method of laminated plate-like objects will be described.

As explained in the above-mentioned problems of the conventional example, in the conventional semiconductor acceleration sensor shown in FIG. , there was no good method for gluing and mounting while maintaining the optimal positional relationship of the convex parts. However, by using the method of the present invention, alignment accuracy can be significantly improved over the prior art.

FIG. 4 is a sectional view of an embodiment of a semiconductor acceleration sensor having a three-dimensional stacked structure according to the present invention.

In FIG. 4, a substrate 201 is a wafer on which a plurality of upper stoppers are formed by selective etching, electrochemical etching, or the like. Further, the substrate 202 is a Si wafer including a plurality of semiconductor acceleration sensor chips. A wafer containing this acceleration sensor chip is formed using IC technology and micromachining technology such as electrochemical etching. Further, the substrate 203 is a wafer including a plurality of lower stoppers, and is manufactured using the same various etching techniques as the substrate 201.

After positioning the substrate 201 and the substrate 202, they are fixed.
The fusion method is the same as the method for manufacturing the three-dimensional plate-like device shown in FIGS. 2 and 3 above.

Next, FIG. 5 is a sectional view showing an embodiment of the above-mentioned positioning and fusing method. Although the dimensions and shape of the acceleration sensor chip in Figure 5 are slightly different from those of the wafer containing the acceleration sensor chip in Figure 4, the alignment and fusing method are essentially the same. It is.

First, the outline will be explained using FIG. 4.

In FIG. 4, a substrate 20 including a plurality of upper stoppers
1 is equipped with optical transmission windows for positioning similar to those in FIG. 1, such as U1□, U2□, U31, etc.
Part B forms an upper stopper. In addition, the substrate 20
2 is a wafer including a plurality of acceleration sensor chips, including cantilever parts 58A, 58B and weight parts 61A, 61.
'B, signal processing IC sections 62A, 62B, etc. Further, in the recessed portion (etched hole) of the substrate 203, there are lower stopper portions 60A and 60B.

Next, details of the alignment and fusion method will be explained using FIG. 5.

In FIG. 5, a substrate 201 with a wafer structure including an upper stopper chip has an insulating film 67 such as an Sio2 film on the back surface of the substrate, aluminum films 68A and 68B at fixed locations for the number of fusion parts,
68C, Au/Ti layer on AQ electrode 69A, 69B
, 69C, and a polyimide layer 70 that has been planarized to the same height as the Au/Ti layer. In addition, etch holes 71A, 7 formed by electrochemical etching
Etch hole 8 formed by 1B and RI etching method
It also has a 5th class.

On the other hand, the substrate 202 is a substrate containing an acceleration sensor chip, and has a 5iO1 film 72 on its upper surface, and aluminum films 73A, 73B, 73C, and AM at a fixed number of fused parts.
A u / T i on the electrode, I! 74A, 74B
, 74C, includes a polyimide layer 75 planarized to the same height as the Au/Ti layer.

It also has etched holes 76A, 77, 79I3 formed by electrochemical etching or the like. Further, a manufacturing process is used in which the etch hole 78 has a structure that penetrates to the upper cavity.

In order to reduce the impact when the Si weight part 65 collides with the upper stopper part 64 due to the retreating speed, it is also effective to protect the upper end of the Si weight part 65 with polyimide or its insulation WA80.

Regarding the wafer 201 including the upper stopper and the sensor chip wafer substrate 202, the laser scribe optical transmission windows U1□ and Ul, , U2° and U2. , U3. Align the two wafers with U3□, etc., fuse them, and then cut them.If you also laser cut the U□ and UR□ points, the signal processing IC section 62A of the semiconductor acceleration sensor chip, It is also possible to expose bonding pads such as 62B.

In addition, the two wafers are fixed by high-precision positioning of multiple A u / Ti layer locations and thermocompression bonding.

The bonding method is almost the same as the wafer stacking method for the three-dimensional device shown in FIG. 2, and therefore will not be described here.

In addition, in the acceleration sensor chip configuration of the solid three-layer plate-like object (wafer) shown in Fig. 4, in addition to the semiconductor wafer chip of the second layer, Si IC is fabricated on the upper surface of the semiconductor wafer of the first layer I. It is also possible to configure the signal processing of the acceleration sensor using a method similar to the signal processing of the multilayer substrate three-dimensional device IC shown in FIGS. 2 and 3.

Note that in the structure of this semiconductor acceleration sensor, the substrate 2
If 011.203 is simply used as an upper stopper or a lower stopper, it is not necessary to use an opaque Si wafer plate, but instead use a glass plate, quartz plate, ceramic plate, etc. processed using IC technology. It's fine. However, in the case of different types of substrates having different coefficients of thermal expansion, it is necessary to use a flexible structure as a bonding method.

According to the semiconductor acceleration sensor of the present invention as described above, the distance between the Si weight portion and the upper stopper and the lower stopper can be controlled to about 10 μm (several μm N can be set up to several tens of μm), which was difficult with the conventional technology, and the wafer process Mass production becomes possible using this method.

〔Effect of the invention〕

As described above, according to the present invention, a recess is formed in a part of a plate-like object, and a predetermined shape for alignment is formed on the bottom surface of the recess, that is, the thinner part of the plate-like object. A plurality of the above-mentioned plate-like objects, each including at least one plate-like object forming a small optically transparent window and having a semiconductor layer containing a semiconductor device, are laminated, and the plurality of plate-like objects are stacked together at a predetermined position through the optically transparent window. By optically aligning them and configuring them to be mutually bonded by adhesion or fusion,
■In the manufacturing method of laminated substrate type three-dimensional devices, the alignment and bonding method of the present invention can largely replace the individual process-based lamination construction method with a wafer processing-like batch process, thereby achieving high precision. The goal is to realize a manufacturing method that allows alignment and is suitable for mass production.

In addition, in the case of stacking each chip, high-yield production can be achieved using automated manufacturing equipment in the hybrid chip stacking assembly method using an optical transmission window for one-position alignment and bonding methods such as thermocompression bonding that can be formed at low temperatures. The effect of realizing the law will come 8 times, etc.

In addition to the above-mentioned common effects, each of the embodiments also has the following effects.

First, in the first embodiment of the three-dimensional laminated substrate device, each of the laminated substrates is set according to a different purpose, and the three-dimensional I
C can be produced at high throughput. As a result, effects such as the ability to realize a microprocessor that uses a large number of ASICs and parallel processing, and an intelligent sensor that has multiple sensor functions at a relatively low cost can be obtained.

In addition, in the semiconductor acceleration sensor that is the second embodiment, the most important of the vertical spacing between the 2/i5 wafer containing the semiconductor acceleration sensor chip and the wafer containing the chip forming a part of the upper stopper of the first layer. Si, which is the part
The distance between the weight part and the upper stopper should be several micrometers to several tens of micrometers.
It can be controlled to an arbitrary value at minute intervals of m, and can be formed by a wafer processing patch process. Further, a substrate including an acceleration sensor chip wafer and a lower stopper chip of the third substrate can be formed in the same manner as described above.

In addition, it has become possible to adopt acceleration sensors and devices using micromachining as a special example of three-dimensional laminated substrate devices, which will help improve the functionality and productivity of various sensors that use micromachining. It becomes possible to stand.

[Brief explanation of drawings]

FIG. 1 is a partial cross-sectional view of a method for manufacturing a three-dimensional device formed by stacking four substrates according to the present invention, and FIG. 2 is a partial cross-sectional view of a method for manufacturing a three-dimensional device formed by stacking four substrates according to the present invention. FIG. FIG. 3 is a partial cross-sectional view showing the means for transmitting signals, and FIG. 3 is a plane view of the wiring electrode patterns in a plurality of recesses on the back surface of one substrate and the signal transmitting means as seen from the back surface of the substrate in the method for manufacturing a three-dimensional device of the present invention. 4 is a cross-sectional view of a wafer having a semiconductor acceleration sensor having a micromechanical structure and a plurality of upper and lower stoppers in the product NJ substrate structure of the present invention, and FIG.
A cross-sectional view showing a manufacturing method in which the semiconductor acceleration sensor chips shown in the figure are aligned and fused together.
FIG. 2 is a cross-sectional view of an example of a semiconductor acceleration sensor having a dimensional structure. Explanation of symbols> 1...Bulk semiconductor 2...Field oxide film 3...Insulating film on the back surface of the substrate 4...Si film of SOI 5...Isolation insulating film 6 in the penetrating part of the recess・
...Through wiring 7 made of a low-resistance wiring member in the recess...Wiring electrode film 8 extending from the bottom of the recess through the slope to the back surface leaking wiring part...Source 9...Drain 11...
・Si gate 12...Gate wiring 13...
Sol Si film 14... SOI insulating film 15...
Source 16...Drain 18...Gate electrode penetrating to the bottom surface 19...Source electrode 20...Drain upper electrode 21A, B...Wiring gold g extending from the bottom surface of the recess to the back surface
! 1 film 22...Etched hole 26...Bulk semiconductor of lower substrate 27...P well 29...P well contact 30...n+ n substrate contact 31...p+ source 32... p+ drain 33...n drain 34...n" source 3
5.36...Silicon gate 3゛7.38...Gate insulating film 39...Interlayer insulating film 40...Voo Electric Works 41/VIIS electrode 42...CMO5 output electrode 43A... 0MO3 input gate electrode 44.45... Polyimide film 46U... Au alloy layer of upper substrate 46L... Au alloy layer of lower substrate 47tJ... Au alloy layer of upper substrate 47L... Au of lower substrate Alloy layer 51... Terminal electrodes 52, 53, 54... Recesses 58A, B for providing optically transparent windows for positioning... Cantilever parts of acceleration sensor chip 59A, B... Upper stopper Part 60A, B... Lower stopper part 61A, B... Acceleration sensor weight part 62A, B...
- Signal processing IC section 63... Cantilever part 64... Upper substrate stopper part 65... Acceleration sensor weight section 66... Signal processing IC section 67... M rim film 68
A, B, C...Aluminum metal electrodes 69A, B, C...Upper substrate Au alloy layer 70...Polyimide layer 71A, B...Etched hole 72...Insulating film on the main surface of the lower substrate 73A, B, C... Aluminum metal electrodes 74A, B, C... Au alloy layer for lower substrate 75...
Polyimide layer 76... Etched hole for positioning 77... Etched hole for cantilever 78... Etched hole 79 connected to the stopper part... Etched hole for alignment 80... Protective insulating film 101, 102, 103.104...Semiconductor substrate 20
1... The first substrate 202 is a wafer for the upper stopper of the semiconductor acceleration sensor... The second substrate is the wafer containing the main body chip of the semiconductor acceleration sensor 2'03... The lower stopper of the semiconductor acceleration sensor Third substrates W11 to Wl, which are wafers, . . . optical transmission windows for positioning among one substrate of a three-dimensional device W21 to W2. ...Another optical transmission window W31 same as above
~W3. ...Another optical transmission window U1□~Ul as above,
...an optically transparent window for alignment in one location of a three-dimensional device

Claims (1)

[Claims] A recess is formed in a part of the plate-like object, and a small optical transmission window of a predetermined shape for alignment is formed on the bottom surface of the recess, that is, the thinner part of the plate-like object, and the semiconductor device is included. A plurality of plate-like objects including at least one plate-like object having a semiconductor layer are stacked, optically aligned at a predetermined position through the optically transparent window, and bonded or fused to each other. 1. A method for manufacturing a semiconductor device, characterized in that: