JP2008288384A - Three-dimensional stacked device and its manufacturing method, and method of junction of three-dimensional stacked device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a three-dimensional stacked device excellent in reliability and its manufacturing method, and a method of the junction of the three-dimensional stacked device. <P>SOLUTION: A plurality of semiconductor wafers 2-5 are laminated to be integrated and thereafter, the integrated body is divided individually into respective devices to constitute the three-dimensional stacked device 1, and in this case, a junction of one semiconductor wafer is formed so as to have a projected shape 6 and a junction of the other semiconductor wafer is formed so as to have a recessed shape 7 while the projected junction 6 of one semiconductor wafer is directly connected to the recessed junction 7 for the other semiconductor wafer to constitute the stacked device. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a three-dimensional laminated device in which a plurality of semiconductor chips are laminated and integrated, a manufacturing method thereof, and a bonding method of the three-dimensional laminated device.

  Conventionally, the integration of semiconductor devices has been dramatically advanced in two dimensions by advances in lithography technology. Two-dimensional integration has physical limitations in lithography. In addition, the required minimum size of semiconductor devices and the required specifications for interconnection between semiconductor devices inside the package are also increasing.

  In addition, when different types of devices, such as different materials used or devices with different manufacturing processes, are used on a single circuit or wafer, a special manufacturing process technology is required. It's not easy.

  Therefore, for example, in order to integrate a large number of devices having different functions such as semiconductor elements, MEMS (Micro Electro Mechanical Systems) elements, sensors, high frequency circuits, monolithic microwave integrated circuits (MMICs), chip level or wafer level Thus, a method of integrating devices in a three-dimensional direction by joining and laminating is employed.

  For bonding at the chip level or wafer level, for example, a method of bonding through an intermediate material layer such as BCB (benzocyclobutene), polyimide, photoresist, or the like, a thin film on the wafer surface as disclosed in Patent Document 1, Alternatively, the material layer is polished to a required surface roughness and then directly joined. By these methods, a large number of devices obtained with different materials and different manufacturing process technologies are integrated in a three-dimensional direction.

Special table 2003-524886

  By the way, in the method of bonding using an intermediate material layer such as BCB, polyimide, or photoresist, thermal stress is generated between the bonded semiconductor wafers due to the difference in thermal expansion coefficient between the intermediate material layer and the semiconductor wafer. It causes changes in device characteristics and reliability. In addition, there is a problem that a thermal budget (thermal history) in mounting after bonding is determined by the heat resistance temperature of the intermediate material layer.

  In the method of directly bonding by thinning the thin film or material on the wafer surface as disclosed in Patent Document 1 to the required surface roughness and directly bonding it, the surface roughness of 5 to 10 mm is applied to the back surface of the bonded wafer by CMP (chemical mechanical polishing). In the case of further polishing and bonding another wafer, there are the following problems. In other words, scratches, microscratches, and the like are introduced into the back surface of the wafer bonded in the first bonding at the stage of the bonding apparatus or the stage of the previous process apparatus, and defects are introduced. For this reason, there is a problem that sufficient surface roughness cannot be obtained on the bonded wafer back surface, and bonding with reliability, that is, bonding of another wafer cannot be performed.

  In view of the above, the present invention provides a highly reliable three-dimensional laminated device, a manufacturing method thereof, and a joining method of the three-dimensional laminated device.

  The three-dimensional laminated device according to the present invention is a three-dimensional laminated device that forms each device after a plurality of semiconductor wafers are laminated and integrated. The bonding part is formed in a convex shape, the bonding part of the other semiconductor wafer is formed in a concave shape, and the convex bonding part of one semiconductor wafer and the concave bonding part of the other semiconductor wafer are directly bonded and laminated. It is characterized by being made.

  In the three-dimensional laminated device of the present invention, in semiconductor wafers stacked adjacent to each other, a convex junction is formed on one semiconductor wafer, a concave junction is formed on the other semiconductor wafer, and both convex and concave shapes are formed. Therefore, no thermal stress is generated between the bonded semiconductor wafers. In addition, since the concave bonding portion is formed on one surface of the semiconductor wafer, the wafer surface having the concave bonding portion cannot be in contact with the stage surface even when the semiconductor wafer is placed on the stage of the manufacturing apparatus. For example, defects such as scratches and micro scratches are not introduced into the joint surface, and a clean joint surface is maintained.

  The manufacturing method of the three-dimensional laminated device according to the present invention includes a step of forming a convex joint on one semiconductor wafer to be stacked next to the other and forming a concave joint on the other semiconductor wafer, A step of directly bonding the bonding portion and the concave bonding portion to laminate one semiconductor wafer and the other semiconductor wafer, and laminating and integrating a plurality of semiconductor wafers through the above steps, and then forming each device It has the process.

  In the manufacturing method of the three-dimensional laminated device of the present invention, a convex joint is formed on one semiconductor wafer to be laminated adjacently, a concave joint is formed on the other semiconductor wafer, and the convex joint is formed. And the concave joint are directly joined. With this direct bonding, the generation of thermal stress is suppressed between the bonded semiconductor wafers, and changes in characteristics and a decrease in reliability are avoided when a device is used. In addition, since a concave bonding portion to be bonded to the convex bonding portion is formed on one surface of the semiconductor wafer, a wafer having a concave bonding portion even when the semiconductor wafer is placed on the stage of the manufacturing apparatus. If the surface is in contact with the stage surface, defects such as scratches and micro scratches are not introduced into the joint surface, and a clean joint surface is maintained. Since the bonding surface is kept clean, the semiconductor wafers stacked adjacent to each other can be bonded well.

  A bonding method of a three-dimensional laminated device according to the present invention is a bonding method of a laminated device when a plurality of semiconductor wafers are laminated and integrated, and then formed on each device to manufacture a three-dimensional laminated device. The convex joint formed on one semiconductor wafer to be laminated and the concave joint formed on the other semiconductor wafer are joined by low-temperature bonding by plasma activation or normal-temperature bonding by Ar ion beam activation. It is characterized by direct bonding.

  In the bonding method of the three-dimensional laminated device of the present invention, a convex bonding portion is formed on one semiconductor wafer to be stacked next to each other, a concave bonding portion is formed on the other semiconductor wafer, and the convex bonding portion is formed. And the concave joint are directly joined. By this direct bonding, generation of thermal stress is suppressed between the bonded semiconductor wafers. Since direct bonding is performed by low-temperature bonding by plasma activation or normal temperature bonding by Ar ion beam activation, there is no thermal influence on elements, wirings, and the like formed on the semiconductor wafer. In addition, since the bonding part of one semiconductor wafer is made convex and the bonding part of the other semiconductor wafer is made concave, the semiconductor wafer is placed on the stage of the wafer bonding apparatus or the stage of another manufacturing apparatus. If the wafer surface having the concave bonding portion is brought into contact with the stage surface, defects such as scratches and micro scratches are not introduced into the bonding surface, and a clean bonding surface is maintained. In addition, since it does not contact the stage surface, transfer of foreign matter on the stage surface can be reduced. As a result, the bonding surface is kept clean and good bonding can be achieved.

According to the three-dimensional laminated device according to the present invention, the generation of thermal stress is suppressed, and defects such as scratches and micro scratches do not enter the joint surface of the joint portion. Therefore, a highly reliable three-dimensional laminated device is provided. Can do.
According to the method for manufacturing a three-dimensional laminated device according to the present invention, since the generation of thermal stress is suppressed and bonding is performed while maintaining a clean bonding surface, a highly reliable three-dimensional laminated device can be manufactured.
According to the three-dimensional laminated device bonding method of the present invention, the bonding reliability can be improved.

  Embodiments of the present invention will be described below with reference to the drawings.

  1 and 2 show an embodiment of a three-dimensional laminated device according to the present invention. As shown in FIG. 1, the three-dimensional laminated device 1 according to the present embodiment includes a plurality of semiconductor wafers, and in this example, four semiconductor wafers 2 to 5 are laminated and integrated so as to have a four-layer structure. A device is formed, that is, each device is separated into pieces. Each solidified three-dimensional stacked device 1 is configured by stacking four semiconductor chips 2A to 5A in a completed state. FIG. 2 is an exploded view of the semiconductor wafers 2 to 5 before the plurality of semiconductor wafers 2 to 5 are bonded and separated into devices.

  In the semiconductor wafers stacked adjacent to each other, the plurality of semiconductor wafers 2 to 5 are formed by forming a convex joint 6 on one semiconductor wafer and forming a concave joint 7 on the other semiconductor wafer. The joints 6 and 7 having both the shape and the concave shape are inserted into each other, and the joint surfaces of the joints 6 and 7 are brought into direct contact with each other without interposing an intermediate material layer.

  In the present embodiment, as shown in FIG. 2, the MEMS structure 11 is formed on the first semiconductor wafer 2. In this example, two MEMS structures 11 are formed corresponding to one semiconductor chip 2A. The MEMS structure 11 is supported in a hollow manner, for example, via a support spring (not shown) formed by etching the semiconductor wafer 2 with respect to the surrounding fixed portion 12. Spaces 13 and 14 are formed between the MEMS structure 11 and the upper and lower second and fourth semiconductor wafers 3 and 5 (see FIG. 1). In this example, the MEMS structure 11 is configured to be electrostatically driven in the XY directions within the wafer surface and displaced in the Z direction in the wafer stacking direction.

  At the peripheral end of the region corresponding to each semiconductor chip 2A in the first semiconductor wafer 2, a convex bonding portion 6 is formed on the first surface, that is, the surface side, and the second surface, that is, the back surface. A concave joint 7 is formed on the side. The joint surface (top) of the convex joint portion 6 is formed as a flat surface made of a silicon wafer, and the joint surface (bottom portion) of the concave joint portion 7 is formed as a flat surface made of a silicon wafer.

  The first semiconductor wafer 2 is a so-called SOI (semiconductor on insulator) in which a buried insulating film (for example, a silicon oxide film) 16 called a BOX layer is formed on a silicon substrate 15 and a silicon layer 17 is formed on the buried insulating film 16. ) Consists of wafers. Although not illustrated, electrodes for electrostatic driving are formed on the side surface of the MEMS structure 11 and the side surface on the fixed portion 12 side, respectively. Further, in order to form the space 13, the surface side is formed in a concave shape 19 except for the convex joint portion 6 at the peripheral end portion, and an electrode pad 18 is formed in the fixed portion 12.

  The MEMS structure 11 can be configured as a so-called physical quantity sensor such as an acceleration sensor, an angular velocity sensor, or a pressure sensor.

  The second semiconductor wafer 3 is a wafer on which a through electrode 21 penetrating the semiconductor wafer 3 is formed, and a logic IC (integrated circuit) to be described later is surfaced from the first semiconductor wafer 2 on which the MEMS structure 11 is formed. It functions as a so-called interposer wafer that relays electrical signals to the third semiconductor wafer 4 formed in the above. In this semiconductor wafer 3, a through hole 22 is formed at a position facing the MEMS structure 11 of the silicon wafer, and an insulating film 23, for example, a silicon oxide film is formed on the entire front and back surfaces of the wafer including the inner surface of the through hole 22. A through electrode 21 is formed in the through hole 22.

  On the first surface of the second semiconductor wafer 3 facing the third semiconductor wafer 4, that is, on the surface side, an electrode pad 24 connected to the through electrode 21 is formed. For example, an insulating film 25 made of a material different from that of the insulating film (for example, silicon oxide film) 23, for example, a silicon nitride film, is formed on the wafer surface so as to cover the electrode pad 24, and the electrode faces the insulating film 25. An electrode (not shown) that is conducted to the pad 24 is formed. The second surface of the semiconductor wafer 3 facing the fourth semiconductor wafer 5, that is, the back surface side, is connected to the through electrode 21 and faces the electrode composed of the silicon layer 17 of the MEMS structure 11. Electrode 26 is formed. Further, an electrode 27 and a conductive bump 28 thereon are formed facing the electrode 18 of the first semiconductor wafer 2.

  Then, at the peripheral end portion of the region corresponding to each semiconductor chip 3A in the second semiconductor wafer 3, a concave bonding portion 7 is formed on the first surface, that is, the surface side, and the second surface, that is, A concave joint portion 7 is formed on the back surface side where the convex joint portion 6 of the first semiconductor wafer 2 is inserted and joined thereto. The concave bonding portion 7 on the front surface side is formed in the insulating film 25, and its bonding surface (bottom surface) is formed as a flat surface by the insulating film 23. The concave bonding portion 7 on the back surface side is formed with a flat surface of the insulating film 23 at its bonding surface (bottom).

  The third semiconductor wafer 4 has a logic IC (semiconductor integrated circuit) 31 formed on the front surface (rear surface in the figure), and an electrode (FIG. 5) that conducts to the electrode pad 24 on the second semiconductor wafer 3 side in the region of the logic IC 31. Conductive bumps 32 connected to (not shown) are formed. Then, an interlayer insulating film (for example, a silicon oxide film) 33 is formed, and the interlayer insulating film 33 is etched away except for a portion that becomes a convex joint portion, whereby each semiconductor chip in the third semiconductor wafer 4 is removed. Convex joint 6 is formed by interlayer insulating film 33 at the peripheral edge of the region corresponding to 4A. The joint surface (top) of the convex joint 6 is formed as a flat surface of the interlayer insulating film 33.

  The fourth semiconductor wafer 5 is a so-called cap wafer for hermetically sealing the inside of the MEMS structure at a low temperature and a low load in order to ensure the reliability of the MEMS structure 11. The first surface of the fourth semiconductor wafer 5, that is, the region facing the MEMS structure 11 on the surface side, has a concave shape 35 so as to form a space 14 (see FIG. 1) with the MEMS structure 11. It is formed. An insulating film (for example, silicon oxide film) 36 is formed on the entire front and back surfaces of the fourth semiconductor wafer 5.

  At the peripheral end portion of the region corresponding to each semiconductor chip 5A in the fourth semiconductor wafer 5, a first surface, that is, a protrusion inserted into the concave joint portion 7 of the first semiconductor wafer 2 on the surface side. A joint portion 6 is formed. The bonding surface (top) of the bonding portion 6 is formed as a flat surface by the insulating film 36.

  These semiconductor wafers 2, 3, 4, and 5 are laminated and integrated by directly joining each other such that the convex joint 6 is inserted into the concave joint 7. The MEMS structure 11 is hermetically sealed so as to be sandwiched between the upper and lower spaces 13 and 14 thereof. With this lamination, the electrodes 18 on the front surface side of the first semiconductor wafer 2 and the conductive bumps 28 on the back surface side of the second semiconductor wafer 3 are electrically connected. In addition, an electrode (not shown) that is electrically connected to the electrode pad 24 on the front surface side of the second semiconductor wafer 3 and the conductive bumps 32 on the back surface side of the third semiconductor wafer 4 are electrically connected in this lamination. Is done.

  The direct joining of the convex joint 6 and the concave joint 7 can be performed at normal temperature by applying a load by activating the joint surfaces of the joints 6 and 7 with, for example, an Ar ion beam. Alternatively, the joint surfaces of both joints 6 and 7 can be activated by plasma, and a load can be applied to join at a low temperature of 400 ° C. or lower, for example, 200 ° C. to 400 ° C. Furthermore, it can also join at high temperature of 700 to 1100 degreeC, without performing an activation process.

  Next, an embodiment of a method for manufacturing a three-dimensional laminated device according to the present invention will be described with reference to FIGS. This example is a case where it is applied to the manufacture of the above-described three-dimensional laminated device 1.

As shown in FIG. 2, the first, second, third and fourth semiconductor wafers 2, 3, 4 and 5 are each formed by forming respective components.
First, as shown in FIG. 3, the first semiconductor wafer 2 is fixed to the lower stage 41 of the wafer bonding apparatus, and fixed or unfixed so that the back surface side having the concave bonding portion 7 is in contact with the surface of the lower stage 41. Arrange in the state of. In addition, the second semiconductor wafer 3 is disposed on the upper stage 42 in a fixed state so that the surface side having the concave joint 7 is in contact with the surface of the upper stage 42.

  The method of fixing the semiconductor wafer to each stage 41, 42 may be either an electrostatic chuck method or a vacuum vacuum method. The wafer surface that contacts the lower stage 41 and the upper stage 42 of the semiconductor wafers 2 and 3 is the side on which the concave joint 7 is formed. That is, in the subsequent process and subsequent steps, the surface on the side having the concave joint 7 is programmed so as to be in contact with the upper stage 42 and the lower stage 41.

  By arranging on the upper stage 42 and the lower stage 41 so that the surface on the concave joint 7 side is in contact, the joint surface of the concave joint 7 will not be scratched or microscratched, and foreign matter will adhere. Without this, a normal joint surface is maintained.

  Next, the upper stage 42 and the lower stage 41 are moved relatively in the vertical direction, and the bonding surfaces of the convex bonding portions 6 and the concave bonding portions 7 to be bonded of the respective semiconductor wafers 2 and 3 are brought into contact with each other directly. Join. As the bonding method, the above-described room temperature bonding method, low temperature bonding method, and high temperature bonding are used. That is, if the heat resistance temperature of the semiconductor wafers 2 and 3 is high, high temperature bonding may be used. Further, when a metal or an organic material is formed, it can be a low-temperature bonding by plasma activation that can be bonded at 400 ° C. or lower, or a normal-temperature bonding by Ar ion beam activation. In the case of high temperature bonding, activation treatment is not required.

  Next, as shown in FIG. 4, a concave bonding portion 7 of the second semiconductor wafer 3 is formed on the bonding wafer 45 obtained by laminating and bonding the first and second semiconductor wafers 2 and 3. It arrange | positions in the state fixed to the upper stage 42 so that the surface side may contact the surface of the upper stage 42. FIG. Further, the fourth semiconductor wafer 5 is arranged on the lower stage 41 in a fixed or unfixed state so that the back surface side where the bonding portion is not formed is in contact with the surface of the lower stage 41.

  Next, the upper stage 42 and the lower stage 41 are relatively moved in the vertical direction, and the bonding surface of the convex bonding portion 6 to be bonded to the first semiconductor wafer 2 in the bonding wafer 45 and the fourth semiconductor wafer 5. These are joined directly to the joint surface of the concave joint 7 to be joined. As the bonding method, the above-described normal temperature bonding method, low temperature bonding method, or high temperature bonding is used.

  Also here, since the bonding portions 7 on the front surface side and the back surface side that contact the surfaces of the bonding wafer 45 and the stage 42, 41 of the fourth semiconductor wafer 5 are concave, the bonding surfaces are not damaged and are clean. The joint surface is maintained. It is possible to shift to the next step of bonding while being kept on a clean bonding surface.

  Next, as shown in FIG. 5, a bonded wafer 45 formed by stacking and bonding the first, second and fourth semiconductor wafers 2, 3 and 5 is formed in the bonded portion 6 of the fourth semiconductor wafer 5. It arrange | positions in the state fixed to the upper stage 42 so that the back side which is not touched the surface of the upper stage 42. FIG. In addition, the third semiconductor wafer 4 is disposed on the lower stage 41 in a fixed or unfixed state so that the back surface side where the bonding portion 6 is not formed is in contact with the surface of the lower stage 41.

  Next, the upper stage 42 and the lower stage 41 are moved relatively in the vertical direction, and the bonding surface of the concave bonding portion 7 to be bonded to the second semiconductor wafer 3 in the bonding wafer 46 and the third semiconductor wafer 4 The joint surface of the convex joint 6 to be joined is abutted and joined directly. As the bonding method, the above-described room temperature bonding method, low temperature bonding method, or high temperature bonding method is used.

  Here, since the bonding portions 6 and 7 are not formed on the surfaces of the bonded wafer 46 and the third semiconductor wafer 3 that are in contact with the surfaces 42 and 41, damage to the bonded surfaces to be bonded is prevented. And is kept on a clean joint surface.

  As a result, as shown in FIG. 6, a four-layer three-dimensional laminated wafer 47 in which the first, second, third and fourth semiconductor wafers 2, 3, 4 and 5 are laminated is formed. Next, the three-dimensional laminated wafer 47 is transferred from the wafer bonding apparatus to a dicing apparatus. In this dicing apparatus, the three-dimensional laminated wafer 47 is diced for each device along the scribe line to obtain the target three-dimensional laminated device 1 shown in FIG.

  In the three-dimensional stacked device of the present embodiment, a MEMS structure chip as the semiconductor chip 2A, a wiring chip including a through electrode as the semiconductor chip 3A, and a logic IC chip as the semiconductor chip 4A are stacked, and further the MEMS structure chip. The integrated MEMS device is configured by laminating a semiconductor chip 2A to be formed and a cap chip that holds the space 14 and is sealed as the semiconductor chip 5A.

  According to the three-dimensional multilayer device 1 according to the above-described embodiment, the joint portions 6 and 7 of the semiconductor chips 2A to 5A that are laminated adjacent to each other are formed in a convex shape and a concave shape, and these convex joint portions 6 are formed. And the concave joint 7 are directly abutted and joined to each other, so that a highly reliable three-dimensional laminated device can be provided. That is, in the laminated semiconductor wafer before singulation, one semiconductor wafer and the other semiconductor wafer laminated next to each other are directly joined by the convex joint 6 and the concave joint 7, and thus joined. Thermal stress due to a difference in thermal expansion coefficient does not occur as when an intermediate material layer such as BCB, polyimide, or photoresist is interposed between semiconductor wafers. By suppressing the generation of this thermal stress, the device characteristics do not change and the reliability is improved.

  In addition, since the concave bonding portion 7 is formed on one surface of the semiconductor wafer, the concave bonding portion 7 is also provided when the semiconductor wafer is placed on the stage of the wafer bonding apparatus or the stage of another manufacturing apparatus. If the wafer surface is in contact with the stage surface, the bonding surface of the concave bonding portion 7 does not directly contact the stage. Therefore, defects such as scratches and micro scratches do not enter the concave joint surface, and foreign matter does not adhere from the stage surface, and a clean joint surface is maintained. Therefore, voids or the like are not generated in bonding, and bonding defects do not occur, and the reliability as a three-dimensional laminated device can be improved.

  According to the method for manufacturing a three-dimensionally laminated device according to the above-described embodiment, a convex joint is formed on one semiconductor wafer to be laminated adjacently, and a concave joint is formed on the other semiconductor wafer. The convex joint and the concave joint are directly joined. With this direct bonding, there is no intermediate material as described above between the bonded semiconductor wafers, the generation of thermal stress due to the difference in thermal expansion coefficient is suppressed, and a highly reliable three-dimensional laminated device can be produced without changing the device characteristics. Can be manufactured.

In addition, since a concave bonding portion to be bonded to the convex bonding portion is formed on one surface of the semiconductor wafer, when the semiconductor wafer is placed on the stage of the wafer bonding apparatus or other manufacturing apparatus However, if the wafer surface having a concave bonding portion is brought into contact with the stage surface, the bonding surface is free from defects such as scratches and microscratches, and no foreign matter adheres from the stage surface. The joint surface can be maintained. Since the bonding surface is kept clean, the semiconductor wafers stacked adjacent to each other can be bonded well, and a highly reliable three-dimensional stacked device can be manufactured.
By using a concave joint, it is possible to maintain a clean joint surface with the device surface structure, and multiple semiconductor wafers can be laminated and joined without any special restrictions on the equipment. A highly reliable three-dimensional laminated device can be manufactured.

  According to the above-described bonding method, the convex bonding portion 6 and the concave bonding portion 7 are directly bonded, so that no thermal stress is generated between the bonded semiconductor wafers due to a difference in thermal expansion coefficient, or generation of thermal stress. Is suppressed. When direct bonding is performed by low-temperature bonding by plasma activation or normal temperature bonding by Ar ion beam activation, a thermal influence on the semiconductor wafer, for example, a thermal influence on elements or wirings formed on the semiconductor wafer. Good bonding is possible without giving Furthermore, as described above, since the bonding is performed using the concave bonding portion, even when contacting with the stage of the manufacturing apparatus, there is no defect such as scratches or micro scratches on the bonding surface, and in a clean bonding surface state. Can be joined.

  Next, an embodiment of a method for forming the concave joint 7 and the convex joint 6 will be described. As described below, the surface roughness of the joint surface (bottom surface) of the concave joint 7 and the surface roughness of the joint surface (top surface) of the convex joint 6 are 1 nm or less, and further 0.5 nm or less. Any method for forming a concave or convex joint may be used as long as it is a method for forming a joint with such a surface roughness.

  In FIG. 7, an example of the formation method of the concave junction part 7 is shown. In this example, after a semiconductor circuit 52 is formed on a semiconductor wafer 51, for example, a silicon wafer, an interlayer insulating film 53 is formed on the entire surface. The interlayer insulating film 53 is etched back and planarized. In the illustrated example, the semiconductor wafer 51 is selectively etched away to a required depth, leaving a region where the semiconductor circuit 52 is formed. Then, the interlayer insulating film 53 in the region 54 to be the junction is etched until the surface of the semiconductor wafer 51 is exposed to form the concave junction 7.

  FIG. 8 shows another example of a method for forming the concave joint 7. In this example, as shown in FIG. 8A, after a silicon nitride film 55 is formed on the entire surface of a semiconductor wafer 51, for example, a region 54 to be a junction on the surface of a silicon wafer, thermal oxidation treatment, that is, selective oxidation (LOCOS) is performed. By processing, a thermal oxide film (SiO 2 film) 56 is formed. Next, as shown in FIG. 8B, the thermal oxide film 56 is selectively removed by etching to form a concave joint 7. The silicon nitride film 55 is removed.

  FIG. 9 shows still another example of the method for forming the concave joint 7. In this example, a resist mask 57 is formed except for a region where a bonding portion is to be formed on the surface of a semiconductor wafer 51, for example, a silicon wafer, and a portion of the semiconductor wafer 51 facing the opening of the resist mask 57 is dry etched or wet etched. Thus, the concave joint 7 is formed.

  FIG. 10 shows still another example of the method for forming the concave joint 7. In this example, a so-called SOI wafer 61 in which a semiconductor layer (for example, a silicon layer) 60 is formed on a surface of a semiconductor substrate (for example, a silicon substrate) 58 via a buried insulating film (for example, an oxide film) 59 is used. The buried insulating film 59 of the SOI wafer 61 is used as an etching stopper layer, and a region where a junction of the semiconductor layer 60 is to be formed is selectively removed by etching. That is, etching is removed until the surface of the buried insulating film 59 is exposed, and the concave joint 7 is formed.

  In FIG. 11, an example of the formation method of the convex junction part 7 is shown. In this example, after an insulating film 62 is formed on the surface of a semiconductor wafer 51, for example, a silicon wafer, the other insulating film 62 is etched until the surface of the semiconductor wafer 51 is exposed, leaving a region 55 where a junction is to be formed. Remove. Thereby, the convex joint 6 is formed by the remaining insulating film 62.

  FIG. 12 shows another example of a method for forming the convex joint 7. In this example, as shown in FIG. 12A, after a silicon nitride film 55 is formed in a region 63 to be a junction on the surface of a semiconductor wafer 51, for example, a silicon wafer, thermal oxidation processing, that is, selective oxidation (LOCOS) processing is performed. Then, a thermal oxide film (SiO 2 film) 56 is formed. Next, as shown in FIG. 12B, the thermal oxide film 56 is selectively removed by etching. The silicon nitride film 55 is removed. As a result, the remaining portion that is not etched is formed as a convex joint 6 made of a semiconductor.

  FIG. 13 shows still another example of the method for forming the convex joint 7. In this example, a resist mask 57 is formed in a region where a bonding portion on the surface of a semiconductor wafer 51, for example, a silicon wafer is to be formed, and the semiconductor wafer 51 is dry etched or wet etched through the resist mask 57. Then, the semiconductor portion remaining without being etched is formed as a convex joint 6.

  FIG. 14 shows still another example of the method for forming the convex joint 7. In this example, a so-called SOI wafer 61 in which a semiconductor layer (for example, a silicon layer) 60 is formed on a surface of a semiconductor substrate (for example, a silicon substrate) 58 via a buried insulating film (for example, an oxide film) 59 is used. The buried insulating film 59 of the SOI wafer 61 is used as an etching stopper layer, and other regions except the region where the junction of the semiconductor layer 60 is to be formed are selectively etched away. That is, etching is removed until the surface of the buried insulating film 59 is exposed. Then, the semiconductor portion remaining without being etched is formed as a convex joint 6.

  According to the method for forming the concave joint 7 and the convex joint 6 described above, the smooth surface of the first semiconductor wafer 51 or the smooth surface of the insulating film formed on the semiconductor wafer 51 Bonding surfaces of the bonding portions 7 and 6 are formed.

  The joint surfaces of the joint portions 6 and 7 can be formed as flat surfaces such as single crystal silicon, polysilicon, amorphous silicon, silicon oxide film, or silicon nitride film. Furthermore, the joint surfaces of the joint portions 6 and 7 can be formed by a flat surface of a metal thin film such as Au, Cu, Al, or an Al alloy.

  As shown in FIG. 15A, the concave joint 7 has a depth h1 that is less than or equal to a height h2 of the convex joint 6, for example, 2 μm or less, preferably 1 μm to 2 μm, and a bottom surface width w1 that is convex. The width w2 or more of the top surface of the joint 6 is, for example, 20 μm or more, preferably 20 μm to 500 μm. As shown in FIG. 15B, the convex joint 6 has a height h2 that is not less than the depth h1 of the concave joint 7, for example, 1 μm or more, preferably 1 μm to 2 μm, and the width w2 of the top surface is concave. The width w1 or less of the bottom surface of the joint 7 is, for example, 20 μm or less, preferably 20 μm to 500 μm.

  If the depth h1 of the concave joint 7 is greater than 2 μm, there will be inconveniences when applying the photoresist, and if it is less than 1 μm, inconveniences such as adhesion of submicron foreign matter will occur. If the width w1 of the bottom surface of the concave bonding portion 7 is smaller than 20 μm, the disadvantage of insufficient bonding strength occurs. If it is larger than 500 μm, the disadvantage of an increase in chip area due to an increase in bonding area occurs.

  If the height h2 of the convex joint 6 is greater than 2 μm, there will be inconvenience when applying the photoresist. If the width w2 of the top surface of the convex joint 7 is larger than 500 μm, there will be a disadvantage of increasing the chip area due to an increase in the joint area, and if it is smaller than 20 μm, there will be a disadvantage of insufficient joint strength.

  FIG. 16 shows another embodiment of the three-dimensional laminated device according to the present invention. The three-dimensional stacked device 65 according to the present embodiment includes a plurality of semiconductor chips, that is, in this example, a semiconductor chip 66A serving as a solid-state imaging element chip, a semiconductor chip 67A serving as a memory chip, and a semiconductor chip serving as a logic IC chip. 68A, a semiconductor chip 69A serving as a MEMS physical quantity chip, and a semiconductor chip 70A serving as a cap chip are stacked and joined to form a so-called composite sensor device. This composite sensor device includes a plurality of semiconductor wafers, that is, a semiconductor wafer 66 on which a solid-state imaging element is formed, a memory wafer 67 on which a memory element is formed, a logic IC wafer 68 on which a logic IC is formed, and a MEMS physical quantity. The MEMS physical quantity wafer 69 on which the sensor is formed is laminated and integrated to be integrated, and further, the cap physical wafer 69 that seals the MEMS physical quantity wafer 69 through a space is laminated and integrated, and then separated into individual pieces. Composed. For example, a MEMS logic IC wafer can be used as the wafer 70 in addition to the cap wafer.

  These semiconductor wafers 66 to 70 are laminated and bonded in the same manner as described above. In the adjacent semiconductor wafers, the convex bonding portion 6 is formed on one semiconductor wafer, and the concave bonding portion 7 is formed on the other semiconductor wafer. It is formed, and it joins directly so that the joint surface of both the junction parts 6 and 7 may be faced | matched. Although schematically shown in FIG. 16, corresponding portions can be configured in the same manner as described above, and detailed description thereof will be omitted.

  As the MEMS physical quantity sensor, for example, an acceleration sensor, an angular velocity sensor, a pressure sensor, or the like can be applied.

  FIG. 20 shows an example of an acceleration sensor as the MEMS physical quantity sensor. The acceleration sensor 101 of this example is formed on an SOI substrate 105 in which an insulating film 103 and a silicon layer 104 are formed on a silicon substrate 102. That is, it has a support portion 106 made of a frame made of an SOI substrate 105, and an SOI substrate at the center of the support portion 106 via four-side elastic support portions 107 [107A, 107B, 107C, 107D] made of a silicon layer 103. A mass part 108 made of 105 is supported. Each elastic support portion 107 [107A to 107D] is provided with a displacement detection means 109 for detecting the displacement of the mass portion. The displacement detection means 109 is composed of, for example, a stress electrical conversion element (piezo element). In this way, the acceleration sensor 101 is configured.

  The operation principle of the acceleration sensor 101 will be described. When acceleration acts on the acceleration sensor 101, the mass portion 108 supported in a floating state by the elastic support portions 107 [107A to 107D] receives a force proportional to the acceleration and is displaced at the center portion of the support portion 106 by the frame. To do. The displacement of the mass portion 108 causes the elastic support portion 107 to bend, and the displacement detection means 109 formed on the elastic support portion 107 has two orthogonal detection axes (X axis and Y axis) on the elastic support portion 107. In addition, corresponding to one detection axis (Z-axis) perpendicular to the elastic support portion 107, acceleration in three axial directions is detected using a Wheatstone bridge circuit configured by four displacement detection means 109 for each axis. .

Next, FIG. 17 to FIG. 19 show modifications in the case where a plurality of semiconductor wafers are laminated and bonded.
In the example of FIG. 17, in a three-dimensional laminated device using a multilayer wafer in which a plurality of semiconductor wafers 81 to 85 are laminated, the intermediate layer semiconductor wafers 82 to 85 excluding the uppermost layer and the lowermost layer respectively have the first surface. For example, a convex joint 6 on the front surface side, a concave joint 7 on the second surface, for example, the back surface side, and the convex joint 6 between the semiconductor wafers stacked adjacent to each other, and The concave joint 7 is directly joined. The uppermost semiconductor wafer 86 is formed with a concave joint 7, and the lowermost semiconductor wafer 81 is formed with a convex joint 6.

  That is, when the structure of FIG. 17 is generalized and described, the first semiconductor wafer is configured to have a convex bonding portion on the first surface, for example, the surface side. The second semiconductor wafer has a convex joint 6 on its first surface, for example, the front surface side, and has a concave joint 7 on its second surface, for example, the back surface side. Similarly, the third semiconductor wafer has a convex joint 6 on the first surface, for example, the front side, and a concave joint 7 on the second surface, for example, the back side. The convex joint 6 of the first semiconductor wafer is joined to the concave joint 7 of the second semiconductor wafer, and the concave joint of the third semiconductor wafer is joined to the convex joint of the second semiconductor wafer. Part 7 is joined. Similarly, each of the fourth to (N-1) th semiconductor wafers has a convex joint 6 on the first surface, for example, the front surface side, and a concave joint 7 on the second surface, for example, the back surface side. It is configured. Bonding is similarly performed from the third semiconductor wafer to the (N-1) th semiconductor wafer. Furthermore, the Nth semiconductor wafer is configured to have a concave bonding portion on the second surface, for example, the back surface side, and is laminated and bonded to the N-1th semiconductor wafer. In this way, a three-dimensional laminated device laminated and bonded to the N layer is configured.

  In the example of FIG. 18, in a three-dimensional stacked device using semiconductor wafers 91 to 93 having a three-layer structure, an intermediate layer semiconductor wafer 92 excluding the uppermost layer and the lowermost layer semiconductor wafers 91 and 93 is concave on both sides. It has a joint 7, and has convex joints 6 on the uppermost and lowermost semiconductor wafers 93 and 91, and these concave joints 7 and convex joints 6 are directly joined. .

  In the example of FIG. 19, in a three-dimensional stacked device using a multilayer wafer in which a plurality of semiconductor wafers 94 to 97 are stacked, a part of the intermediate layer semiconductor wafer 96 excluding the uppermost layer and the lowermost layer has a concave shape on both sides. The remaining intermediate layer semiconductor wafer 95 having the joint 7 has a convex joint 6 on the first surface, for example, the front surface side, and a concave joint 7 on the second surface, for example, the back surface side. These are formed by directly bonding the convex joint and the concave joint between the semiconductor wafers stacked adjacent to each other. The uppermost semiconductor wafer 97 and the lowermost semiconductor wafer 94 are formed with convex joints 6.

It is a block diagram which shows one Embodiment of the three-dimensional laminated device which concerns on this invention. It is an exploded view of the three-dimensional laminated device which concerns on embodiment of FIG. It is a manufacturing process figure (1) which shows one Embodiment of the manufacturing method of the three-dimensional laminated device which concerns on this invention. It is a manufacturing process figure (the 2) which shows one Embodiment of the manufacturing method of the three-dimensional laminated device which concerns on this invention. It is a manufacturing process figure (the 3) which shows one Embodiment of the manufacturing method of the three-dimensional laminated device which concerns on this invention. It is a manufacturing process figure (the 4) which shows one Embodiment of the manufacturing method of the three-dimensional laminated device which concerns on this invention. It is sectional drawing which shows an example of the preparation methods of the concave junction part of the three-dimensional laminated device which concerns on this invention. A, B It is sectional drawing which shows the other example of the preparation methods of the concave junction part of the three-dimensional laminated device which concerns on this invention. It is sectional drawing which shows the other example of the manufacturing method of the concave junction part of the three-dimensional laminated device which concerns on this invention. It is sectional drawing which shows the further another example of the manufacturing method of the concave junction part of the three-dimensional laminated device which concerns on this invention. It is sectional drawing which shows an example of the preparation methods of the convex junction part of the three-dimensional laminated device which concerns on this invention. A, B It is sectional drawing which shows the other example of the preparation methods of the convex junction part of the three-dimensional laminated device which concerns on this invention. It is sectional drawing which shows the other example of the preparation methods of the convex junction part of the three-dimensional laminated device which concerns on this invention. It is sectional drawing which shows the further another example of the manufacturing method of the convex junction part of the three-dimensional laminated device which concerns on this invention. A and B It is sectional drawing with which it uses for description of the magnitude | size of the concave junction part which concerns on this invention, and a convex junction part. It is a typical block diagram which shows other embodiment of the three-dimensional laminated device which concerns on this invention. It is an exploded view which shows the modification in the case of carrying out the lamination | stacking joining of the several semiconductor wafer concerning this invention. It is an exploded view which shows the other modification in the case of carrying out the lamination | stacking joining of the several semiconductor wafer which concerns on this invention. It is an exploded view which shows the other modification in the case of carrying out the lamination | stacking joining of the several semiconductor wafer which concerns on this invention. A and B are a perspective view and a cross-sectional view showing an example of an acceleration sensor which is one of MEMS physical quantity sensors applied to the components of the three-dimensional multilayer device according to the present invention.

Explanation of symbols

  1 .. Three-dimensional laminated device, 2-5 .. Semiconductor wafer, 2A, 3A, 4A, 5A .. Semiconductor chip, 6 .... Convex joint, 7 .... Concave joint, 11 .... MEMS structure Body 13, 14 ... Space, 41 ... Lower stage, 42 ... Upper stage, 65 ... Three-dimensional stacked device, 66-70 ... Semiconductor wafer, 66A ... Chip, 67A ... Memory chip, 68A ... · Logic IC chip, 69A · · MEMS physical quantity chip, 70A · · Cap chip, 81 to 86 · · Semiconductor wafer, 91 to 93 · · Semiconductor wafer, 94 to 97 · · Semiconductor wafer, 101 · · Accelerometer

Claims (19)

A three-dimensional laminated device that forms each device after a plurality of semiconductor wafers are laminated and integrated,
In semiconductor wafers stacked next to each other, the junction of one semiconductor wafer is formed in a convex shape, and the junction of the other semiconductor wafer is formed in a concave shape,
The three-dimensional laminated device, wherein the convex joint of the one semiconductor wafer and the concave joint of the other semiconductor wafer are directly joined and laminated. The intermediate layer semiconductor wafer, excluding the uppermost layer and the lowermost layer semiconductor wafer, has a convex joint on the front surface and a concave joint on the back surface. Three-dimensional laminated device. 3. The three-dimensional laminated structure according to claim 1, wherein the intermediate layer or a part of the intermediate layer semiconductor wafer, excluding the uppermost layer and the lowermost layer semiconductor wafer, has concave joints on both the front surface and the back surface. device. 2. The three-dimensional laminated device according to claim 1, wherein the surface of the joint is formed of a flat surface of single crystal silicon, polysilicon, amorphous silicon, a silicon oxide film, or a silicon nitride film. The three-dimensional device according to claim 1, wherein the surface of the joint is formed by a flat surface of a metal thin film. The three-dimensional stacked device according to claim 1, wherein the device is an integrated MEMS device in which a MEMS structure chip, a wiring chip including a through electrode, and a logic IC chip are stacked. The three-dimensional stacked device according to claim 1, wherein the device is a composite sensor device in which a MEMS physical quantity sensor chip, a solid-state imaging device chip, a logic IC chip, and a memory chip are stacked. Forming a convex joint on one semiconductor wafer to be stacked next to each other, and forming a concave joint on the other semiconductor wafer;
Directly bonding the convex joint and the concave joint, and laminating the one semiconductor wafer and the other semiconductor wafer;
A method of manufacturing a three-dimensional laminated device, comprising: forming a device after stacking and integrating a plurality of semiconductor wafers through the above steps. Forming the convex and concave joints with a flat surface,
The method of manufacturing a three-dimensional laminated device according to claim 8, wherein the direct bonding is performed by low-temperature bonding by plasma activation or normal temperature bonding by Ar ion beam activation. The method of manufacturing a three-dimensional multilayer device according to claim 8, wherein the surface of the joint is formed by a flat surface of single crystal silicon, polysilicon, amorphous silicon, a silicon oxide film, or a silicon nitride film. The method of manufacturing a three-dimensional laminated device according to claim 8, wherein the surface of the joint is formed by a flat surface of a metal thin film. The convex joint is formed by forming a concave region by dry etching or wet etching a region other than the convex joint of the semiconductor wafer, and forming the concave region by the non-etched convex region. The manufacturing method of the three-dimensional laminated device of Claim 8. By selectively oxidizing the convex joint portion in a region other than the convex joint portion of the semiconductor wafer, the selective oxidation layer is removed by etching to form a concave region, and the convex region in which the concave region is not formed. The method of manufacturing a three-dimensional laminated device according to claim 8, wherein the method is formed. The method for manufacturing a three-dimensional laminated device according to claim 8, wherein the concave joint is formed by dry etching or wet etching. The method for manufacturing a three-dimensional laminated device according to claim 8, wherein the concave joint is formed by selectively oxidizing a semiconductor wafer and then removing the selective oxide layer by etching. A method for joining laminated devices when a plurality of semiconductor wafers are laminated and integrated, and then formed into each device to produce a three-dimensional laminated device,
A convex joint formed on one semiconductor wafer to be stacked adjacent to a concave joint formed on the other semiconductor wafer is directly joined by low-temperature joining by plasma activation. Bonding method for three-dimensional laminated device. A method for joining laminated devices when a plurality of semiconductor wafers are laminated and integrated, and then formed into each device to produce a three-dimensional laminated device,
It is characterized in that a convex joint formed on one semiconductor wafer to be laminated next to a concave joint formed on the other semiconductor wafer is directly joined by room temperature bonding by Ar ion beam activation. A method for joining three-dimensional laminated devices. 18. The method for bonding a three-dimensional stacked device according to claim 16, wherein the surface of the bonding portion is formed by a flat surface of single crystal silicon, polysilicon, amorphous silicon, a silicon oxide film, or a silicon nitride film. . The surface of the said junction part is formed with the flat surface of a metal thin film. The joining method of the three-dimensional laminated device of Claim 16 or 17 characterized by the above-mentioned.

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