JPS62216258A - Three-dimensional built-up integrated circuit - Google Patents

Abstract

PURPOSE:To simplify assembly further, and to prevent displacement in the direction of the mutual planes of two-dimensional integrated circuit layers by partially forming one or more of indentations to a two-dimensional integrated circuit layer substrate and positioning the substrate in the direction of a plane. CONSTITUTION:At least one indentations 11 are shaped to each two-dimensional integrated circuit layer 10. Marks capable of being distinctly discriminated physically geometrically are formed to respective two-dimensional integrated circuit layer 10 in an indentation shape for positioning in the direction of a plane in the indentations 11. The indentations 11 are shaped in blind holes, and acquired through etching treatment from one surfaces to substrates 12 in each two-dimensional integrated circuit layer 10 in general. The mutual positive superposition of the indentations is determined by an optical magnification means or an electrical means as the method of the utilization of the indentations 11 being formed. Accordingly, displacement and the quantity of displacement in the direction of the planes of respective two-dimensional integrated circuit layer 10 can be determined, and the reliability and simplicity of positioning are obtained simultaneously.

Description

[Detailed Description of the Invention] (Field of Industrial Application) The present invention relates to a three-dimensional integrated circuit in the electronic technology field or optoelectronic technology field, and particularly relates to a method for assembling and stacking two-dimensional integrated circuit layers that have been manufactured independently of each other in advance. , relates to a three-dimensional assembled integrated circuit in which effective consideration is given to mutual positioning in a plane direction.

<Conventional technology> In information processing technology that uses various semiconductor elements, Josephson elements, even magnetic bubble elements, etc., and uses electric signals, optical signals, magnetic signals, etc. as signal transmission media, it is important to improve the degree of integration and reduce power consumption. In recent years, proposals regarding three-dimensional integrated circuit structures have been frequently made with the aim of reducing the number of circuits, increasing speed, and increasing functionality.

Generally speaking, there are roughly two types of construction methods for realizing such three-dimensional integrated circuits using specific structural members.

One is what can be called a sequential lamination method. This is the existing S
This method uses the concept of OI (silicon-on-insulator) technology. Once a two-dimensional integrated circuit layer is completed, its functional surface is covered with an insulating layer, and polycrystalline silicon is deposited on top of this insulating layer. After forming the polycrystalline silicon layer, the polycrystalline silicon layer is made into a single crystal by laser annealing, and a two-dimensional integrated circuit layer consisting of a predetermined circuit structure is again completed on this single-crystal silicon layer, and the process is repeated in order. It is something. In addition, each two-dimensional integrated circuit layer in the height direction is
It is usually called the active layer or functional level, and sometimes simply called the chip.

On the other hand, the other method is to obtain a three-dimensional integrated circuit by assembling the two-dimensional integrated circuit layers, which have been completed separately, so that they overlap each other at the end. It can be called an assembly method, and the flip chip method is a typical method that has been published.

The flip-chip method uses multiple two-dimensional integrated circuit layers, each with various circuit elements integrated to achieve a desired circuit function on its surface, starting in the final assembly step and electrically connected by bonding pads and solder. It is about connecting.

Therefore, in order to do this, at least one of a pair of adjacent two-dimensional integrated circuit layers must be formed by penetrating the substrate that serves as its physical support member, from the circuit element forming surface on the front surface to the bonding pad portion on the back surface. requires a through hole to make an electrical connection to.

<Problems to be solved by the invention> The above-mentioned sequential lamination method has the highest degree of freedom in circuit design when considering the three-dimensional integrated circuit as a whole, and also has high reliability after it is completed as a product. However, as the name "sequential" suggests, it involves the inherent problem that each two-dimensional integrated circuit layer cannot be created at the same time.

In other words, after completing one 2D integrated circuit layer, you can create the next 2D integrated circuit layer on top of it, so it takes a huge amount of time to complete one 3D integrated circuit. It takes a lot of time.

For example, even if we consider the simplest model in which all two-dimensional integrated circuit layers can have the same configuration, as long as this sequential lamination method is used, the number of layers required to manufacture one two-dimensional integrated circuit layer is It is absolutely necessary to double the amount, and if we were to specifically obtain, for example, a middle-layer three-dimensional integrated circuit, it would probably take more than half a year to manufacture it, without exaggerating it.

For this reason, the so-called turn process from design to results is
The around time becomes extremely long, resulting in extremely poor efficiency, and the yield of devices that have been repeatedly manufactured over a long period of time becomes considerably poor.

Also, as a matter of course, it is impossible to repair just one layer once it has been made. Even if we try to obtain a three-dimensional integrated circuit using the same logic with only one or a few layers having a different circuit structure, each layer cannot be replaced, so it is necessary to repeat the entire process for each specification.
There is no hope for rationality in this regard.

On the other hand, with the batch lamination method or assembly method represented by the above-mentioned flip-chip method, each two-dimensional integrated circuit layer can be fabricated simultaneously and independently from each other, so that the specifications of only one layer may differ. Three-dimensional integrated circuits can be obtained relatively easily through selection in the final assembly process.
It is extremely reasonable because all layers that do not require changes can be used for each specification, and the manufacturing time itself is approximately the same as the time required to form a single two-dimensional integrated circuit layer plus the assembly time for the final process. It will be done.

Therefore, the turn-around time is naturally shortened, and the yield is not considered to be bad.

However, when adopting such a batch lamination method or assembly method, there are problems that must be solved from a different perspective. It is the planar positioning between each two-dimensional integrated circuit layer during the assembly process.

However, until now, this positioning in the planar direction has not been directly discussed. In the above-mentioned flip-chip method, etc., it is only reported that the corresponding bonding surfaces are overlapped, but there is no explanation as to how to overlap them while precisely positioning them in the plane direction. .

However, from a commonly thought perspective, by slightly moving a suitable jig that mechanically holds each two-dimensional integrated circuit layer, the mutual planar positioning of two-dimensional integrated circuit layers adjacent to each other in the overlapping direction can be achieved. However, it is preferable that each of these two-dimensional integrated circuit layers themselves have mutually positioning elements in the planar direction.

If so, the assembly in the final process will be even more
This simplifies the process, and in special cases, it becomes possible to perform stacking assembly with predetermined positioning even between two-dimensional integrated circuit layers having different contour dimensions, for example intentionally or due to manufacturing tolerances.

The present invention was made precisely in view of these points,
In a three-dimensional integrated circuit that employs an assembly method in which two-dimensional integrated circuit layers, which can be manufactured separately and independently, are laminated in an assembly process, each two-dimensional integrated circuit layer adjacent to the other in the overlapping direction or lamination direction has the It is intended to have a positioning element in the planar direction.

However, of course, such positioning elements should never be formed by unreasonable methods and should not impede integration, and if necessary, should be used for photoelectric conversion elements etc. in each two-dimensional integrated circuit layer. It should be something that can have a positive impact on functionality and operation.

Means for Solving the Problems> In order to achieve the above object, the present invention provides a three-dimensional assembled integrated circuit having the following configuration.

1) A three-dimensional assembled integrated circuit formed by assembling and laminating a plurality of two-dimensional integrated circuit layers, each of which has been separately and independently formed on its own substrate in advance, in a superimposed manner; The two-dimensional integrated circuit layer has one or more depressions formed locally in a relatively thick substrate that serves as a physical support for the two-dimensional integrated circuit layer; A three-dimensional assembled integrated circuit characterized in that, when the two-dimensional integrated circuit layers are assembled and laminated together, the depression is used as a positioning element in the planar direction between the adjacent two-dimensional integrated circuit layers.

2) A three-dimensional assembled integrated circuit formed by assembling and laminating a plurality of two-dimensional integrated circuit layers, each of which has been separately and independently formed into a two-dimensional integrated circuit on its own substrate, in a superimposed manner; The two-dimensional integrated circuit layer has one or more depressions formed locally in a relatively thick substrate that serves as a physical support for the two-dimensional integrated circuit layer; When assembling and stacking the layers together, the recess is used as a positioning element in the planar direction between the adjacent two-dimensional integrated circuit layers; A three-dimensional assembled integrated circuit characterized in that: an auxiliary member for positioning is provided that extends through or passes through the three-dimensional integrated circuit, and the auxiliary member mechanically prevents displacement of adjacent two-dimensional integrated circuit layers in the planar direction.

<Operations and Effects> According to the present invention, the recesses obtained by reducing the substrate thickness of each two-dimensional integrated circuit layer are used as planar positioning elements. Therefore, the recess itself may be a blind hole or a transparent hole, but in any case, the advantage is that the positioning element itself is easy to form.

In other words, the present invention discloses the essential feature of forming physically and geometrically clearly distinguishable marks in the form of depressions in each two-dimensional integrated circuit layer for planar positioning. However, the reason why we identified depressions as landmarks is because they can be used in a variety of ways, and yet have minimal impact on two-dimensional and three-dimensional accumulation density.

These points are equally advantageous when the present invention is applied to any three-dimensional assembled integrated circuit consisting of a semiconductor circuit system, a Josephson circuit system, a magnetic bubble circuit system, or a combination circuit system thereof. be.

However, the simplest way to utilize the depressions formed according to the present invention is, for example, to monitor the two-dimensional integrated circuit layers to be stacked from the stacking direction and determine whether or not the depressions are certainly overlapping each other. There is a method of visually checking the overlap using optical magnification means, or intentionally passing a light beam with a diameter that is the same as or slightly wider than the diameter of the recess, and determining the degree of overlap visually or by electrical means.

Particularly when using a method of passing a light beam, a suitable light intensity needle is used to take advantage of the fact that the maximum intensity of light is obtained when all the dimples are aligned in a line, and the distance between each two-dimensional integrated circuit layer is measured. It becomes possible to know the deviation in the plane direction, the amount of deviation, etc. In this case, the light beam can be modulated with a specific signal pattern if necessary, and in this way, regardless of the light beam intensity, the signal strength of the input side and the output side can be compared. Highly accurate positioning in the plane direction is possible with the aid of a precision and high amplification comparison amplifier or lock-in amplifier. These methods can be applied regardless of whether the depression is a blind hole or a transparent hole.

Furthermore, according to the second invention of the present application, since an auxiliary member is used that is fitted into or passes through such a recess, for example, when a long rod-shaped member is selected as the auxiliary member, each two-dimensional integrated circuit layer The two-dimensional integrated circuit layers can be sequentially assembled and laminated by passing the rod-shaped member in series through the through holes used as positioning depressions.

Therefore, not only is the assembly extremely simple, but also it is possible to prevent the two-dimensional integrated circuit layers from shifting from each other in the plane direction even after the assembly is completed.

In this case, if the rod-shaped member is conductive, it can be used as a power line between the two-dimensional integrated circuit layers,
It can also be used as some control lines.

On the other hand, if a blind hole is selected as the recess for positioning,
When selecting a spherical member, a columnar member, etc. as the auxiliary member, this auxiliary member is dropped in advance into a recess that is formed in the lower two-dimensional integrated circuit layer and opens upward, and then the auxiliary member is On the other hand, if the depressions formed in the upper two-dimensional integrated circuit layer and facing downward are positioned so as to fit from above, the adjacent two-dimensional integrated circuit layers are automatically positioned. The same convenience as when using the rod-shaped member described above can be obtained, and the auxiliary member can also mechanically prevent displacement in the plane direction after positioning.

However, even if the recess is a through hole, positioning using the auxiliary member described above is possible if the wall surface thereof is an inclined surface with a tapered cross section.

It is also possible to form a protuberance or protrusion on the entire surface of a certain two-dimensional integrated circuit layer, and to position the protrusion or protrusion so as to fit it into a recess formed in the upper two-dimensional integrated circuit layer.

However, generally when obtaining a blind hole as the depression,
It is easiest and most accurate to perform ordinary etching processing on the substrate. In this case, the blind holes may be formed only on one side of the substrate, or they may be etched from both sides toward the center of the inside of the substrate. When provided on both sides, positioning using the auxiliary member as described above may be performed by forming two layers adjacent to each other above and below a certain two-dimensional integrated circuit layer. can be performed simultaneously on two-dimensional integrated circuit layers.

On the other hand, when a through hole is selected as the recess, a blind hole is first made and then the bottom of the blind hole is extracted using a laser beam or the like to form a through hole. In fact, it is more practical.

However, if highly accurate machining is possible,
The recess defined by the present invention can also be created by mechanical processing, whether it is a blind hole or a through hole.

Furthermore, in the case of either the first invention or the second invention, if the recess defined by the present invention is a blind hole, the blind hole is formed only from one side of the substrate or from both sides. Regardless of whether they are formed equally across the board depth direction, the board thickness at the part where this blind hole is located is always reduced, and therefore a thin layer is formed at the bottom of this blind hole. By using this as a formation site for a photoelectric conversion function section, extremely significant effects can be obtained in terms of interlayer information transmission in this type of three-dimensional integrated circuit.

A photoelectric conversion function section is an integrated structure consisting of a light emitting element such as a semiconductor laser or a light emitting diode, or a light receiving element such as a phototransistor or photodiode, or a group of such light emitting elements or a group of light receiving elements, or a combination thereof. It is a general term that includes circuits.

This has the advantage of allowing signals to be transmitted and received between layers using light, which eliminates the need for through-holes, bonding pads, and other mechanical devices that require manufacturing effort and tend to impede improvements in two-dimensional integration density in the first place. The number of functional elements can be significantly reduced.

In this case, of course, a light-transmitting material is selected for the thin layer portion of each two-dimensional integrated circuit layer formed according to the present invention, but generally the material selected for the forming base layer of this type of integrated circuit is at least specified. Since it is transparent to wavelengths of

Of course, in accordance with the second invention of the present application, when using an auxiliary member such as a spherical member or a columnar member to be fitted into the recess as described above, the auxiliary member also has optical transparency at least with respect to the wavelength of the applied light. It is necessary to select a material for this auxiliary member, but conversely, this auxiliary member is not only used as a mechanical slippage prevention element, but also has an optical function such as a cylindrical lens or spherical lens when transmitting and receiving information by light. You can also have it.

In other words, the function is to converge light from a light emitting element formed in a thin layer of one two-dimensional integrated circuit layer and efficiently send it to a light receiving element formed in a thin layer of the next two-dimensional integrated circuit layer. can be operated. Of course, conversely, it is also possible to simply make an optical fiber or optical rod perform a similar action without the convergence action, and in such a case, the auxiliary member is not limited to a spherical or cylindrical shape. .

Furthermore, when performing such optical information transmission, a light reflecting layer or an absorbing layer may be provided on the back surface of a relatively thick substrate portion other than the thin layer portion. Since light can be incident only on a portion of the substrate, even if a signal processing section for processing the output signal of the photoelectric conversion function section or other normal circuit system is provided on the surface of a relatively thick substrate section, for example, Inconveniences such as light entering these and interfering with their operations can be effectively prevented.

Similarly, in order to reduce the loss of light incident on the thin layer portion, it is preferable to fill the recess with a refractive index matching medium, and this is a problem regardless of whether or not an auxiliary member is used.

Forming the photoelectric conversion function section on the thin layer section formed corresponding to the depression as described above is advantageous for the photoelectric conversion function section formed.

This is because, in the first place, it is preferable to form in the thinner area according to the present invention, rather than forming in the surface layer area of at most several to tens of layers of the surface area of the substrate, which has hundreds of legs, as in the case of the conventional method. However, desirable results such as making isolation between horizontally adjacent elements extremely simple and reliable, preventing the generation of parasitic transistors and diodes, and rationally avoiding the problem of lateral leakage can be achieved. This is because it can be obtained.

In particular, the photoelectric conversion function part formed in the thin layer part is formed with a light emitting element or (and) a light receiving element that absorbs light with an energy lower than the optical band gap of the substrate, and the light is transmitted through a thin layer made of the same material as the substrate. If a portion of the light is absorbed by the layers, optical signals can be exchanged between a considerable number of stacked two-dimensional integrated circuit layers. However, the thin layer portion may be formed of a material different from that of the substrate.

Further, even if it is not necessary to form a photoelectric conversion function part in a thin layer part, it is advantageous to select a blind hole as the recess referred to in the present invention.

First, the rate of deterioration of substrate strength is low.

Secondly, as mentioned above, since a thin layer is formed on the board corresponding to the blind hole, various types of integrated circuits can be used on this thin layer as well as on the surface of the thick board other than the thin layer. Circuit elements can be built in, and therefore, even if a positioning recess is formed according to the spirit of the present invention, this does not reduce the planar integration density. In other words, the positioning function according to the present invention can be provided without sacrificing the conventional integration density.

In addition, as yet another method for mechanically utilizing the depression formed according to the present invention, a method of using this depression from the side can also be considered. In other words, when each two-dimensional integrated circuit layer is scribed at a position that includes a depression, the depression breaks and becomes open laterally, so a support rod or the like as a type of auxiliary positioning member is applied from the side in series. By making the support rod conductive, it is possible to prevent the two-dimensional integrated circuit layers from shifting in the lateral direction by passing the support rod in series, and as described above with respect to the rod-shaped member, the electrodes between the layers can be prevented. It can also be used as a terminal.

As described above, according to the present invention, as a positioning device for a three-dimensional assembled integrated circuit, it is possible to simultaneously obtain reliability and ease of positioning involved in the assembly, and if necessary, the positioning recess can be used. Information can be exchanged between layers using light at high speed, with high reliability, and with a high space factor.
Moreover, an extremely wide range of significant effects can be obtained, such as improving the electrical characteristics of the photoelectric conversion functional part formed in the thin layer part.

Furthermore, the idea of the present invention is not only applicable to semiconductor integrated circuits, but also applicable to Gibzefson integrated circuits, magnetic bubble integrated circuits, and three-dimensional integrated circuits in which these are mixed. For example, it is possible to form a Josephson element in a thin layer and switch it by the incidence of light.If a large number of such Josephson elements are integrated in series, each switching voltage can be adjusted by the gap. Although the voltage is only a few mV at most, it is quite possible to drive a semiconductor transistor by summing the voltage due to the switching of a large number of Josephson elements, and it is also possible to drive the input/output signals related to the magnetic bubble element by optical signals. It is also possible to send and receive signals by converting the data into .

In any case, there is no doubt that the present invention discloses a technology that will be fundamental for the future of this type of three-dimensional assembled integrated circuit.

Embodiment FIG. 1 shows a three-dimensional assembled integrated circuit as a preferred embodiment constructed in accordance with the present invention.

In this three-dimensional assembled integrated circuit, a plurality of two-dimensional integrated circuit layers 10 are assembled and stacked in the vertical direction in the figure.
Each two-dimensional integrated circuit layer 1o can be prefabricated separately and independently, as in conventional assembly methods of this type.

What is characteristic about the present invention is that each two-dimensional integrated circuit layer 10
At least one depression 11 (in the illustrated case, three depressions are shown) is formed in each of the depressions 11 .

In the case of the embodiment shown in the first figure, the recess 11 is a blind hole, and this is generally obtained by etching the substrate 12 of each two-dimensional integrated circuit layer 1o from one side. . Specifically, for example, when the substrate 12 is made of the most common silicon and the plane index is (100),
Apply an alkaline solution such as KOH or hydrazine to the substrate through the opening in the etching-resistant mask! By etching 2, a recess 11 is obtained in which both the rounded wall surface 13 and the bottom 14 are uniform. It may be desirable for the wall surface 13 and the bottom surface 14 to be uniform for reasons described below.

In the present invention, at least one of these depressions is used as a planar positioning element for each adjacent two-dimensional integrated circuit layer 10.

After forming each two-dimensional integrated circuit layer 10, the corresponding depression 11 formed in advance at a predetermined position in the two-dimensional integrated circuit layer 10 is formed.
They are assembled and stacked so that they are arranged and overlapped on an imaginary straight line extending along the height direction.

In such a case, since the thickness of the substrate is thinner in the areas where the recesses 11 are provided and the thin layer portions 17 are formed, the recesses 11 can be visually observed using an appropriate optical magnification means.
It can be determined whether or not they overlap as expected. In other words, by such monitoring, it is possible to know whether there is a relative deviation in the planar direction between the two-dimensional integrated circuit layers 10.

However, as shown for the recess 11 on the far left in the figure, if a light beam IB of an appropriate wavelength is used, preferably having a diameter that is about the same as or slightly wider than the cross-sectional diameter of the recess 11,
It is not only possible to simply judge whether or not there is a deviation, but also to know the amount of deviation, if necessary, so that positioning can be performed more accurately.

For example, the light beam IB is irradiated in the height direction from an appropriate oscillator or light source (not shown), and after passing through the three-dimensional integrated circuit structure, it is appropriately focused by a lens system 15, etc.
If this is made to enter the photodetector 1B, which may also be a known existing one, the depressions 1 of each two-dimensional integrated circuit layer 10 will be completely covered.
It is possible to know when each two-dimensional integrated circuit layer 1o is perfectly aligned in the plane direction by utilizing the fact that when the two dimensional integrated circuit layers 1o are aligned in planar projection, the light intensity received by the photodetector IB is the highest. I can do it.

Further, by using an appropriate measurement system (not shown), it is also possible to measure the correlation between the intensity change and the amount of deviation. In particular, if the optical beam IB is modulated with a specific signal pattern, only that modulated amount is demodulated, and a lock-in amplifier or high-precision comparison amplifier is used to take out the difference between the output side and the reception side. Regardless of the wavelength or intensity of the light beam, it is possible to know the amount of positional deviation with considerable accuracy. In these cases,
The dimensional order regarding the amount of lateral deviation is much higher precision, at least compared to the thickness of this type of substrate (about 250 layers) that is normally used, and it is on the order of micron, which is the element integration density order, and even sub-micron.・It can be easily brought even to the area of ordering.

In the case of the embodiment shown in FIG. 1, the three two-dimensional integrated circuit layers 10 from the top in the figure have their respective recesses 11 opening downward.

However, as shown in the relationship between the two-dimensional integrated circuit layer lO below and the two-dimensional integrated circuit layer 10 above it, there is a mutual depression 11 between a pair of adjacent two-dimensional integrated circuit layers 10.10.
, 11 may face each other, or furthermore, as in the embodiment shown in FIG. Digged depressions 11, 11 may be formed. Also in the case shown in FIG. 2, the determination method regarding positioning described above with reference to FIG. 1 can be adopted as is. Of course, the two-dimensional integrated circuit layer 10 having the recess structure shown in the first figure and the two-dimensional integrated circuit layer 10 having the recess structure shown in the second figure can coexist in one three-dimensional integrated circuit.

In the embodiments shown in FIGS. 1 and 2, the recess 1
Since a blind hole is utilized in 1, a thin layer portion 17 is formed correspondingly at the bottom 14 of the hole.

The first thing that can be said is that when such a blind hole is used as the depression 11, the surface of the thin layer portion 17 can also be used as it is as an element integration area.

In other words, even if the above-mentioned positioning is achieved by the present invention, since the positioning element is a recess, especially when a blind hole is selected as the recess, there is no positioning means in the past, and the positioning element is a recess. Compared to an integrated circuit in which the entire element integration area can be used, this has the advantage that the integration density is not reduced in any way.

However, if we consider this more positively, by making this thin layer part 17 a formation area for the photoelectric conversion function part, it is possible to obtain effects that could never be obtained with the conventional structure, and the present invention can be used more effectively. I can do it.

As explained in the section on functions and effects, the photoelectric conversion function section is a general term for various light-emitting elements, light-receiving elements, and structures made up of sets and combinations of them. As schematically shown as a single element, for example, a light receiving element 18 and a light emitting element 18 can be formed in the thin layer portions 17 formed respectively.

In this way, the information optical signal Is generated by the light emitted by the light emitting element 18 formed in a certain thin layer section 17 is transmitted to the thin layer section 17 that corresponds to the position of the two-dimensional integrated circuit layer 10 located above and below it. The provided light-receiving element 18 receives and receives the light, and it becomes possible to perform operations such as assisting in signal processing within the two-dimensional integrated circuit layer 10, and information exchange between the two-dimensional integrated circuit layers without using wired electrical signals is possible. This allows the number of area-consuming mechanical elements, such as bonding pads, to be eliminated or reduced.

In particular, if each two-dimensional integrated circuit layer has a dedicated power source such as a solar cell (not shown), even an interlayer power supply line may be unnecessary. In this case, each two-dimensional integrated circuit layer is
For example, if the edge of the two-dimensional integrated circuit layer is made to protrude laterally beyond the edge of the two-dimensional integrated circuit layer located immediately above, and the entire structure is configured in the shape of a terrace or a staircase, the upward facing surface of the staircase shape can be formed. By forming solar cells for each calendar month in 2D layers, the amount of light incident on all the solar cells can be equalized, so that the output of solar cells in one layer is more extreme than that of solar cells in other 2D integrated circuit layers. Inconveniences such as becoming smaller can be avoided.

In this case, the interlayer positioning according to the present invention works extremely effectively. This is because, in the conventional method of positioning the two-dimensional integrated circuit layers to be stacked in a plane direction using an appropriate jig, the widths of the two-dimensional integrated circuit layers essentially differ. There is a risk that the jig holding the upper layer may damage the surface of the lower layer, which would make it extremely difficult, but according to the present invention, there is no such risk at all.

Furthermore, if the above-mentioned transmission and reception of the optical signal Is were to be carried out using a thick substrate as in the past, the optical loss in the thick substrate would become unignorable. By utilizing the region where 17 is formed, the degree of loss can be greatly reduced.

However, of course, the smaller the loss, the better. Therefore, in order to supply the information optical signal Ig emitted by one light emitting element 18 to many layers, for example, a thin layer section 17 is formed. Each light receiving element 18 may be made of a material that responds to long wavelength light with energy smaller than the optical band gap of the material.

Moreover, if the space created by the presence of the depression 11 is filled with, for example, a refractive index matching medium 20, loss therein can also be suppressed. This may be an effective means in some cases for the light beam IB used in the positioning measurement described above.

Furthermore, as shown in FIG. 2, photoelectric conversion elements 18 or 18 can be formed on both sides of the thin layer 917, respectively.

As a specific example, in order to obtain the desired light emitting element 18, when the material of the thin layer portion 17 is silicon, AIP, 11;
It is conceivable to grow a light-emitting compound semiconductor such as , GaAs, or the like. In particular, for example, the light emitting element 18 may be made of GaAs.
When using a system element to generate light with a wavelength of 825n■, if the thickness of the thin layer 17 is set to about 5 to 10jlff1, it is possible to send and receive the optical signal Is between the 5th layer and the soil layer. becomes.

Furthermore, in order to obtain a light-emitting element made of the above-mentioned material, only a growth temperature between 800°C at the highest and about 800°C at the lowest is required. Even if ordinary integrated circuits 21 such as MO3 integrated circuits are formed, the characteristics of these circuits 21 will not be impaired or physical or thermal damage will be caused.

Furthermore, as before, the integrated circuit 2 on the thick substrate portion
If the photoelectric conversion function part of the thin layer part 17 is formed of a material with an optical band gap narrower than that of the part in which 1 is formed, and long wavelength light is selected as the signal light, then the signal light can be temporarily transferred to the integrated circuit 21.
Even if it is scattered in the area, the effect can be suppressed. Specifically, for the crystalline silicon-based integrated circuit 21, an InGaAs-based material is selected for the photoelectric conversion function portion.

On the other hand, although not shown, the relatively thick substrate portion 12 and the thin layer portion 17 may be made of different materials from the beginning. This is the existing SOS (Sapphire on
This corresponds to the case where silicon technology, etc. is applied. That is, the substrate 12 is made of sapphire and the thin layer portion is made of silicon.

In addition, it is also possible to grow a semiconductor thin film such as Si or GaAs on the GaP substrate 12 as an example of a material with a narrower optical band gap than the GaP substrate 12, and use this as the thin layer portion 17.

In particular, as the light emitting element 18, for example, an alternating multilayer structure of AlC1aAs films having different composition ratios of AI and Ga, or an AlG
If you choose a vertical oscillation laser or the like that has a multilayer structure of alternating aAg films and GaAs films, you can easily obtain an optical signal Is in the direction perpendicular to each layer of the substrate without having to take special consideration of the geometric arrangement. This is advantageous because optical signal transmission in both the upward and downward directions is naturally possible.

Note that in each of the embodiments described later, the thin layer portion 1 is
When forming a photoelectric conversion function section in 7, the optical band
The various considerations mentioned above, such as the description of the gap, can be applied as they are, and as mentioned above, the circuit system integrated in each two-dimensional integrated circuit jiJ10 is not limited to the semiconductor element system, but can also be applied to Josephson circuit systems, etc. It may be a magnetic bubble circuit system or a combination circuit system thereof.

Furthermore, the present invention does not directly specify how to mechanically bond the two-dimensional integrated circuit layers that have been positioned and stacked one on top of the other; any suitable adhesive may be used. , crimping method, etc. may be employed.

FIG. 3 shows an embodiment in which the recess 11 defined by the present invention is a through hole and a positioning auxiliary member is used in accordance with the second invention.

In this case, the positioning auxiliary member is a rod-shaped member 22 with a small diameter, and for example, one end is embedded and fixed in the lowermost substrate 12, and the other end extends upward in the vertical direction.

In each two-dimensional integrated circuit layer 10 that is assembled and laminated in order on the lowest substrate, a depression 11 consisting of a through hole is formed in a positionally corresponding manner, and the diameter of the narrowest point of the through hole is as follows. The diameter is approximately the same as the diameter of the rod-shaped member 22.

The method of using such a structure in the assembly process of each two-dimensional integrated circuit layer 10 is already obvious from the figure, but with respect to the bottom layer substrate 12, each rod-shaped member 22 has a positioning hole 11 formed therein. What is necessary is to repeat the process of first overlapping the first two-dimensional integrated circuit layer 10 while passing it through, and then overlapping the second two-dimensional integrated circuit layer 10 thereon in the same manner.

In such a structure, it is convenient and functionally desirable to form the through hole 11 in such a manner as to punch out the bottom of the blind hole formed by etching as described above. The reason is that the through hole 11 formed in this way has a downwardly tapered sloped wall surface 13, so that this sloped wall surface can be used as a guide for smooth fitting to the rod-shaped member 22 during the above assembly process. This is because 13 can be used. However, this is not limiting, and appropriate machining may be used as long as the accuracy is good.

Further, the bottom layer substrate 12 may not have an integrated circuit formed thereon, and may simply serve as a supporting substrate with sufficient physical strength.

Of course, as shown in Figure 2 earlier, the blind hole 11.11
In the structure in which the holes are formed from both sides of the substrate, the two-dimensional integrated circuit layer 10 has a through hole obtained by removing the thin layer portion 17 left between the pair of blind holes using, for example, a laser beam.
can also be applied to the structure shown in FIG. 3 in the same way.

In FIG. 3, for the sake of simplicity, integrated circuits that are built on the surface or both sides of each substrate are not shown, except that it is not possible to form various elements or integrated structures thereon because there is no thin layer. Regarding other considerations, the explanation regarding the above-mentioned embodiment can be referred to, and as shown by the blind hole 11° in the figure, a recess which is not related to the positioning recess according to the present invention is used as a blind hole. Therefore, various explanations based on the thin layer portion 17 described above can be applied as is to the thin layer portion 17° formed correspondingly.

Further, as a special use of this auxiliary member 22, it is possible to form it from a conductive material and use it as a power supply or signal communication line in the living room. This is exemplified by the fact that the rod-shaped member 22 is electrically connected to the conductive surface C by solder S, as shown by the imaginary line in the top layer in the figure.

In addition, according to the normal positioning theory, at least three auxiliary members or rod-shaped members 22 are spaced apart from each other when viewed from above.
If there is, positioning can be performed in both x and y directions within the plane.

Each of the embodiments shown in FIG. 4 is an embodiment in which different types of auxiliary members are used.

In the embodiment shown in FIG. 2A, each two-dimensional integrated circuit layer 10 has blind holes 11, 11 formed from both sides of the substrate 12, as described above. Only one adjacent pair is shown.

What is characteristic is that a pair of adjacent two-dimensional integrated circuit layers 10.
When the mutual blind holes 11.11 in 10 facing on their adjacent sides are aligned face-to-face, a spherical member 23 is inserted which preferably just fits into the cavity created by them.

It is desirable that the blind holes 11, 11 have a sloped wall surface 13 having a uniform slope by etching as described above.
The spherical member 23 is placed in advance by dropping it to about half its diameter, and the upper two-dimensional integrated circuit layer 10 is placed over it, and the spherical member 23 is placed in the corresponding downward blind hole 11 of the upper two-dimensional integrated circuit layer 10. By fitting approximately the upper half of the spherical member 23, the sloped wall surface 13 of each blind hole.
13, positioning can be achieved in an automatic alignment manner.

As shown in FIG. 4(B), the same effect can be obtained when the cylindrical member 24 is used as an auxiliary member by lying on its side instead of the spherical member b 23.

In both of the embodiments shown in FIGS. 4(A) and 4(B), it is necessary to completely prevent rattling between a pair of overlapping two-dimensional integrated circuit layers 10 and 10 that are adjacent to each other. Naturally, the slanted wall surface 1 of the upper and lower blind holes 11, 11 is formed on a part of the peripheral surface or edge of the auxiliary members 23, 24.
3.13 parts are all in tight contact, but in practice this is a difficult requirement. These auxiliary members 2
3 and 24 are generally formed by chemical or mechanical means, but it is impossible to make one having the same diameter or radius as the cavity created when the blind holes 11 and 11 are completely overlapped.

However, for example, it is relatively easy to suppress the degree of wobbling of the auxiliary members 23 and 24 within the cavity to below the sub-micron order, even with existing technology.
A deviation amount on that order can be tolerated.

Rather, it is actually more desirable to design the dimensions of each auxiliary member to such an extent that some looseness can be expected. This is because, if the size of the auxiliary member is too large, it may cause "lifting" between a pair of adjacent two-dimensional integrated circuit layers 10.10 or damage the thin layer portions 17.17. This is because there is a risk of In particular, this becomes a big problem when an integrated circuit or a photoelectric conversion function section is built into the thin layer section 17.17 as described above.

Further, from this point of view, it may be more advantageous to use the cylindrical member 24 shown in FIG. 4(B) than to use the spherical member 23 shown in FIG. 4(^). Spherical member 2
3 is the thin layer portion 1 at both the top and bottom apexes in the vertical direction.
However, in the case of a cylindrical member 24, as long as a recess 11 having a sloped wall surface 13 as shown in the figure is used as the recess 11, This is because there is always a space between the upper and lower circumferential surfaces and the thin layer portion 17, and they do not come into direct contact with each other.

In the case of the embodiments shown in FIGS. 4(A) and 4(B), the photoelectric conversion function portion is formed in the thin layer portion 17 as described above, and the photoelectric conversion function portion is formed in the thin layer portion 17 as described above. Optical signal I between
When transferring g, the positioning auxiliary member 23,
24 can also be used as an optical element 6. For example, it is possible to obtain a kind of converging lens effect, thus suppressing the scattering of the optical signal Ig emitted by the light emitting element 18 and helping to input it to the corresponding light receiving element 18. be able to.

However, if such a convergence effect is not necessary,
Of course, any shape can be used as the auxiliary member, and even if the cylindrical member 24 is used as in the embodiment shown in FIG. 4(B), it can also be used as a stand. .

Furthermore, when forming a photoelectric conversion function part in the thin layer part 17,
As described above, the cavities housing the auxiliary members 23 and 24 may be filled with the refractive index matching medium 20 to effectively reduce optical loss.
, 24 and thus the previous two-dimensional integrated circuit layer 10.
10 or their laminates 17, 17 can also be used as cushions. However, a separate cushioning material may be further sandwiched between the previous two-dimensional integrated circuit layers 10.10.

It is already possible to mold using existing technology, and if molding in space is successful in the future, as has been studied in recent years, it will be possible to create spherical parts that are extremely similar to pearls and cylindrical parts with extremely high radius precision. etc. can also be obtained, making it more convenient to apply to the present invention.

Of course, it is normal to use auxiliary members at multiple locations on a plane, and if there is no need to form an integrated circuit in the thin layer portion 17, a through hole may be used instead of the auxiliary member.
Positioning is possible with the aid of this auxiliary member.

FIG. 4(C) shows an embodiment in which the auxiliary member is a raised member 25 formed on the surface of the substrate. For example, as shown in the figure, a two-dimensional integrated circuit is stacked on the surface of the lowermost substrate 12. A raised member 25 is formed in the layer 10 (a transparent hole or a blind hole may be used depending on whether or not the thin layer portion 17 is required), and the upper peripheral surface of the raised member 25 fits into the hollow 11. Positioning is achieved by contacting or facing the wall surface 13 of.

In the case of this embodiment as well, the bottom layer substrate 12 is not only used as a support substrate for a physical three-dimensional structure, but also an integrated circuit may be actively configured thereon, and if a thin layer is required, In the middle, as shown by the imaginary line 111, it is sufficient to form an appropriate depression and form a corresponding thin layer portion 17°.
This means that the structure using the raised member 25 can also be applied to the intermediate layer. In this case, of course, the above-mentioned refractive index matching medium 20 etc. can be similarly used.

In special cases, for example, if a conductive film is attached to the wall surface of the recess 11, the auxiliary members 23 and 24 arranged in the cavity formed by the pair of recesses 11 facing each other may be made of conductive material, or By making it into a molten solder ball, it can be used as a connecting line member for power or signals between layers, or even as a mechanical fixing means.

In the embodiment shown in FIG. 5, alignment in the planar direction is achieved by applying positioning auxiliary members from the sides of the substrate 12 of each two-dimensional integrated circuit layer IO.

Generally, each two-dimensional integrated circuit layer lO is often cut out from a single wafer 30 along a scribe line 31 as shown by a virtual line in FIG. 5(A). Therefore, in a group of recesses 11 in which a plurality of recesses are arranged at appropriate locations at intervals of withdrawal,
If a series of depressions 11 located at the edge of one two-dimensional integrated circuit layer are scribed, the depressions 11 are laterally divided and further scribed if necessary, as shown in FIG. 5CB). By removing the thin layer above it, a recess 11 that opens laterally can be formed.

Therefore, as shown in FIG. 5(B), the recesses 11 opened laterally along each side of each two-dimensional integrated circuit layer are used as positioning recesses 11 defined in the present invention.
If a rod member 2B extending in the stacking direction as an auxiliary member is bitten against this in a side-biting manner, the desired positioning according to the present invention can be performed in the same way as in each of the above-mentioned embodiments. .

Further, in such an embodiment, the rod-shaped member 28 can also be used as an interlayer power supply line or signal line, as described above.

Of course, the reason why the recesses 11 are arranged periodically as shown in the drawing is because other recesses that are not used as positioning recesses of the present invention have good electrical properties. This is to effectively utilize the obtained circuit integrated portion.

As already mentioned, for example, the recess 11 according to the invention may be a blind hole and the resulting thin layer! In particular, when 7 is used as a region for forming a photoelectric conversion function section, this thin layer section can be used more effectively by forming a plurality of elements in this region rather than forming a single element. To prove this, −
As an example, FIG. 6 shows a case where a photodiode array is assembled.

In the illustrated case, three junction formation regions 40 are integrated per cross section along one direction of the thin layer portion 17, and the photoelectric conversion portion configured per one of the junction formation regions 40 is a unit of The photoelectric conversion elements (substantially diodes) 42 are connected in series with the wiring layer 4G on the thin layer surface through contacts formed at appropriate positions, so that the entire photoelectric conversion function is achieved. 44. Of course, both ends of this series circuit are connected to the insulating film 4 on the substrate surface.
It is connected to a lead-out wiring layer 47 disposed on top of the wiring layer 5 .

The junction formation region 40 for forming each unit photoelectric conversion element 42 is, for example, a thin layer portion selected as a semiconductor! 7
In this case, the thin layer portion 17 is made of the same material as the substrate 12 and is p-type, and the rectifying junction forming region 40 is n-medium type.

However, the reason why it is most effective to use the thin layer portion 17 formed corresponding to the recess 11 according to the present invention in such an integrated circuit is that the separation portion provided between adjacent unit photoelectric conversion elements 42 is most effective. The argument is based on 41.

That is, as seen in this type of separation technology, this separation section 41 is arranged in a frame shape in a plan view and surrounds each unit photoelectric conversion element 42, but in cross section it is arranged in a frame shape as usual. The cutout does not stop midway through the depth of the thick substrate, but can be cut out completely from the top to the bottom of the thin layer portion 17 as shown in the figure.

In the illustrated case, this separation part or penetration part 41 is an n-medium type of conductivity type opposite to that of the semiconductor substrate 12, but of course, if the conductivity type of the semiconductor substrate is reversed, the conductivity type of this separation part will also be reversed. . Aluminum infiltrated into silicon can constitute metal silicide and has rectifying properties for n-type silicon, so if the semiconductor substrate 12 is of n-type, the separation part 41 may be made of this silicide, Therefore, conversely, this silicide can also be used as the rectifying junction forming region 40.

However, in any case, the fact that the isolation part 41 can be formed so that it passes completely vertically in this way fundamentally prevents the generation of parasitic transistors and parasitic diodes that go around under the isolation part as in the conventional method. It means that you can. On the contrary, a thin layer [I
11? The dimension tf is 1 for a normal board thickness of 250 mm.
The number of layers may be 00 or less, preferably about 40 or less.

Incidentally, in order to prevent surface parasitic channels and to improve contact with the thin layer section 17, it is necessary to remove the separation section 41 and the junction forming region 40 on the surface of the thin layer section 17.
It is preferable to form a P medium-sized region 43 with an appropriate depth between the two.

Furthermore, if a light reflecting film or a light absorbing film 48 is formed on the back surface side of the substrate 12 except for the thin layer portion 17, as described above, it is possible to form a light reflecting film or a light absorbing film 48 on the back side of the substrate 12, excluding the thin layer portion 17. When transmitting and receiving optical signals between the two, it is easy to meet the request to provide the optical signals only to the photoelectric conversion function section 44 and not input them to a circuit system (not shown) connected to the extraction wiring layer 47. obtain. Therefore, the optical band
This method is particularly effective when no countermeasures are taken for the gap, and can be similarly adopted in the other embodiments described above.

In addition, when forming a light receiving element in the thin layer part 17, the spectral sensitivity can also be adjusted by the thickness of the thin layer part 17.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram of a preferred embodiment of a three-dimensional assembled integrated circuit constructed according to the present invention, FIG. 2 is a schematic block diagram of an embodiment in which the shape of the recess formed according to the present invention is changed, and FIG. Figures 4 and 5 are schematic configuration diagrams of a three-dimensional assembled integrated circuit as an embodiment of the present invention using positioning auxiliary members.
The figure is an explanatory diagram of still another positioning method or another embodiment according to the present invention, and FIG. 6 is an example of forming an integrated structure of photoelectric conversion elements in a thin layer part that can be formed incidentally according to the present invention. FIG. In the figure, 10 is a two-dimensional integrated circuit layer, 11 is a depression, 12 is a substrate, 13 is a wall of the depression, 14 is a bottom of the depression, 17 is a thin layer, 18 is a light receiving element, 18 is a light emitting element, and 20 is a refracting element. rate matching medium, 21 is a suitable integrated circuit, 22, 23, 24°2
5 and 26 are auxiliary members for positioning, 40 is a bonding region, 42 is a unit photoelectric conversion element, 44 is a photoelectric conversion function unit as a whole, and 48 is a light reflection or light absorption film.

Claims (1)

[Scope of Claims] 1) A three-dimensional assembled integrated circuit formed by assembling and laminating a plurality of two-dimensional integrated circuit layers in a superimposed manner, each of which has separately and independently formed a two-dimensional integrated circuit on its own substrate. In each of the two-dimensional integrated circuit layers, one or more depressions are locally formed in a relatively thick substrate that serves as a physical support for the two-dimensional integrated circuit layers; A three-dimensional assembled integrated circuit characterized in that, when the integrated circuit layers are assembled and laminated one on top of the other, the recess is used as a positioning element in the planar direction between the adjacent two-dimensional integrated circuit layers. 2) A three-dimensional assembled integrated circuit formed by assembling and laminating a plurality of two-dimensional integrated circuit layers in a superimposed manner, each of which has previously formed a two-dimensional integrated circuit on its own substrate; The two-dimensional integrated circuit layer has one or more depressions formed locally in a relatively thick substrate that serves as a physical support for the two-dimensional integrated circuit layer; When assembling and stacking the layers together, the recess is used as a positioning element in the planar direction between the adjacent two-dimensional integrated circuit layers; and the recess is fitted into the positioning recess provided in each of the adjacent two-dimensional integrated circuit layers. A three-dimensional assembled integrated circuit characterized in that: an auxiliary member for positioning is provided that extends through or passes through the three-dimensional integrated circuit, and the auxiliary member mechanically prevents displacement of adjacent two-dimensional integrated circuit layers in the planar direction.