JPH0230191B2 - - Google Patents
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- Publication number
- JPH0230191B2 JPH0230191B2 JP56200469A JP20046981A JPH0230191B2 JP H0230191 B2 JPH0230191 B2 JP H0230191B2 JP 56200469 A JP56200469 A JP 56200469A JP 20046981 A JP20046981 A JP 20046981A JP H0230191 B2 JPH0230191 B2 JP H0230191B2
- Authority
- JP
- Japan
- Prior art keywords
- light
- light emitting
- light receiving
- emitting elements
- elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 claims description 42
- 239000000758 substrate Substances 0.000 claims description 20
- 230000003287 optical effect Effects 0.000 claims description 10
- 230000008878 coupling Effects 0.000 claims description 9
- 238000010168 coupling process Methods 0.000 claims description 9
- 238000005859 coupling reaction Methods 0.000 claims description 9
- 239000013078 crystal Substances 0.000 claims description 9
- 238000000605 extraction Methods 0.000 claims description 4
- 229910021417 amorphous silicon Inorganic materials 0.000 description 16
- 239000007789 gas Substances 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000004044 response Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 2
- 229910006404 SnO 2 Inorganic materials 0.000 description 2
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 239000008188 pellet Substances 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- ZOCHARZZJNPSEU-UHFFFAOYSA-N diboron Chemical compound B#B ZOCHARZZJNPSEU-UHFFFAOYSA-N 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000284 extract Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910000078 germane Inorganic materials 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000003208 petroleum Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Description
【発明の詳細な説明】
本発明はアモルフアス半導体等の非単結晶半導
体から成る受光素子を備えた半導体光結合装置に
関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor optical coupling device including a light receiving element made of a non-single crystal semiconductor such as an amorphous semiconductor.
近年半導体材料の開発が進む中で、シランのプ
ラズマ反応等により得られるアモルフアスシリコ
ンに於いて、従来から困難とされていたPN制御
が可能であることが判明し、此の種アモルフアス
半導体が注目を集めている。このアモルフアス半
導体は単結晶半導体に較べ製造エネルギが小さ
く、工程が簡単で、連続的に大量生産が可能であ
り、しかも使用材料が少なくてすむ、等の多くの
優れた特長点を有している。 As the development of semiconductor materials progresses in recent years, it has been discovered that PN control, which has traditionally been considered difficult, is possible in amorphous silicon obtained by silane plasma reaction, etc., and this type of amorphous semiconductor has attracted attention. are collecting. Compared to single-crystalline semiconductors, amorphous semiconductors have many advantages, such as requiring less manufacturing energy, simpler processes, continuous mass production, and requiring less materials. .
この様なアモルフアス半導体は石油等のエネル
ギ資源の枯渇に対処すべく、非枯渇、クリーンエ
ネルギ源である太陽光から直接電気を得る太陽電
池としての開発が盛んに行なわれている。 In order to cope with the depletion of energy resources such as petroleum, such amorphous semiconductors are being actively developed as solar cells that obtain electricity directly from sunlight, which is a non-depletable, clean energy source.
また、同じ理由により蒸着、印刷、スプレー、
気相成長等の方法によつて10ミクロンオーダで得
られる多結晶半導体の太陽電池についても開発が
行なわれている。 Also, for the same reason, vapor deposition, printing, spraying,
Polycrystalline semiconductor solar cells that can be obtained on the order of 10 microns by methods such as vapor phase growth are also being developed.
本発明は斯るアモルフアス半導体若しくは多結
晶半導体等の非単結晶半導体を備えた新規な半導
体光結合装置を提供するもので、以下に図面を参
照しつつ本発明の実施例につき詳述する。 The present invention provides a novel semiconductor optical coupling device equipped with such a non-single crystal semiconductor such as an amorphous semiconductor or a polycrystalline semiconductor, and embodiments of the present invention will be described in detail below with reference to the drawings.
第１図は本発明の一実施例を示し、１はガラ
ス・耐熱プラスチツク等の透光性絶縁基板、２
ａ，２ｂは該絶縁基板１の一方の一主面１ａに配
置された第１・第２の発光素子、３ａ，３ｂは上
記絶縁基板１の他方の一主面１ｂに形成された第
１・第２の受光素子で、夫々第１・第２の発光素
子２ａ，２ｂ並びに受光素子３ａ，３ｂは上記絶
縁基板１を隔てて対向する。 FIG. 1 shows an embodiment of the present invention, in which 1 is a translucent insulating substrate made of glass, heat-resistant plastic, etc.;
Reference numerals a and 2b indicate first and second light emitting elements disposed on one principal surface 1a of the insulating substrate 1, and reference numerals 3a and 3b indicate first and second light emitting elements disposed on the other principal surface 1b of the insulating substrate 1. In the second light receiving element, the first and second light emitting elements 2a and 2b and the light receiving elements 3a and 3b are opposed to each other with the insulating substrate 1 interposed therebetween.
上記第１・第２の発光素子２ａ，２ｂは例えば
ガリウム燐GaP単結晶から成り、その電極面の一
部分は第２図に示す如き絶縁基板１の一主面１ａ
にパターン印刷された銀ペースト等の導電性接着
剤４を介して上記絶縁基板１を透過しようとする
光を遮ることなく被着される。そして、上記第
１・第２の発光素子２ａ，２ｂの他の電極面はワ
イヤリード５ａ，５ｂを介して絶縁基板１上の第
１・第２の発光素子２ａ，２ｂの間に配されてい
る電極膜６に結合される。 The first and second light emitting elements 2a and 2b are made of, for example, gallium phosphorus GaP single crystal, and a part of the electrode surface is one main surface 1a of an insulating substrate 1 as shown in FIG.
The conductive adhesive 4 such as silver paste with a pattern printed thereon is applied without blocking the light that is about to pass through the insulating substrate 1. The other electrode surfaces of the first and second light emitting elements 2a and 2b are arranged between the first and second light emitting elements 2a and 2b on the insulating substrate 1 via wire leads 5a and 5b. The electrode film 6 is connected to the electrode film 6.
一方、絶縁基板１の他方の一主面１ｂに設けら
れた第１・第２の受光素子３ａ，３ｂは上記絶縁
基板１上にパターニングされた酸化スズ
（SnO2）、酸化インジウム（In2O3）、酸化インジ
ウム・スズ（In2O3：SnO2）等の透明電極膜７上
に例えばPIN接合型のアモルフアス半導体層８が
被着され、更にアルミニウム等の金属電極膜９が
重畳された積層構造を持つ。そして、上記第１の
受光素子３ａの金属電極膜９は絶縁基板１上に延
在し隣接する第２の受光素子３ｂの透明電極膜７
と結合する。その結果、第１の受光素子３ａと第
２の受光素子３ｂとは直列関係になるべく接続さ
れる。 On the other hand, the first and second light receiving elements 3a and 3b provided on the other main surface 1b of the insulating substrate 1 are made of tin oxide (SnO 2 ) and indium oxide (In 2 O) patterned on the insulating substrate 1. 3 ) For example, a PIN junction type amorphous semiconductor layer 8 is deposited on a transparent electrode film 7 made of indium tin oxide (In 2 O 3 :SnO 2 ), etc., and a metal electrode film 9 made of aluminum or the like is further superimposed. It has a laminated structure. The metal electrode film 9 of the first light receiving element 3a extends on the insulating substrate 1, and the transparent electrode film 7 of the adjacent second light receiving element 3b
combine with As a result, the first light receiving element 3a and the second light receiving element 3b are connected in series as much as possible.
次いでより具体的な実施例をその製造方法と共
に説明する。 Next, more specific examples will be described together with their manufacturing methods.
先ず透明電極膜７が蒸着若しくはスパツタによ
り被着されパターニングされたガラスから成る絶
縁基板７をプラズマ反応炉の反応電極間に配置
し、上記絶縁基板１を約300℃に加熱した状態で
シラン（SiH4）ガスと不純物ガスとしてジボラ
ン（B2H6）を1000ppm導入する。そして上記反
応電極に13.56MHz、100Wの高周波電力を付与し
て、上記絶縁基板１上に厚み約100ÅのＰ型のア
モルフアスシリコン（ａ−Si：Ｈ）を得る。その
後B2H6ガスのみを除去して厚み約5000ÅのＩ型
ａ−Si：Ｈを析出せしめ、更にフオスフイン
（PH3）を不純物ガスとして1000ppm混入し300Å
程度のＮ型ａ−Si：Ｈを形成し、絶縁基板１から
PIN各層を重畳したPIN接合を有するアモルフア
スシリコン（ａ−Si：Ｈ）半導体層８を得る。尚
上記ａ−Si：Ｈの成長速度は各層とも約1μｍ／hr
であるので、所望の厚みを得るべく時間制御され
る。 First, an insulating substrate 7 made of glass on which a transparent electrode film 7 has been deposited and patterned by vapor deposition or sputtering is placed between the reaction electrodes of a plasma reactor, and while the insulating substrate 1 is heated to approximately 300°C, silane (SiH) is applied. 4 ) Introduce 1000 ppm of diborane (B 2 H 6 ) as gas and impurity gas. A high frequency power of 13.56 MHz and 100 W is applied to the reaction electrode to obtain P-type amorphous silicon (a-Si:H) with a thickness of about 100 Å on the insulating substrate 1. After that, only the B 2 H 6 gas was removed to precipitate I-type a-Si:H with a thickness of about 5000 Å, and 1000 ppm of phosphine (PH 3 ) was added as an impurity gas to deposit a thickness of 300 Å.
Form an N-type a-Si:H of about
An amorphous silicon (a-Si:H) semiconductor layer 8 having a PIN junction in which PIN layers are overlapped is obtained. The growth rate of the above a-Si:H is approximately 1 μm/hr for each layer.
Therefore, the time is controlled to obtain the desired thickness.
次いで上記アモルフアスシリコン半導体層８を
予め定められたパターンにフオトエツチング若し
くはプラズマエツチング等の手段によつて形成す
る。また上記手段を使用せず、アモルフアスシリ
コン半導体層８を金属マスクを用いて選択的に形
成してもよい。最後に、上記アモルフアスシリコ
ン半導体層８上にアルミニウムの金属電極膜９を
蒸着し第１の受光素子３ａと第２の受光素子３ｂ
とが直列関係に接続されるべくエツチングにより
パターニングされる。 Next, the amorphous silicon semiconductor layer 8 is formed into a predetermined pattern by means such as photoetching or plasma etching. Alternatively, the amorphous silicon semiconductor layer 8 may be selectively formed using a metal mask without using the above method. Finally, an aluminum metal electrode film 9 is deposited on the amorphous silicon semiconductor layer 8 to form a first light receiving element 3a and a second light receiving element 3b.
are patterned by etching so that they are connected in series.
斯るPIN接合型アモルフアスシリコン半導体層
８から成る第１・第２の受光素子３ａ，３ｂは約
580nｍに受光の中心波長λ1が存在する。 The first and second light receiving elements 3a and 3b made of the PIN junction type amorphous silicon semiconductor layer 8 are approximately
The center wavelength λ 1 of light reception exists at 580 nm.
一方、第１・第２の発光素子２ａ，２ｂは上記
第１・第２の受光素子３ａ，３ｂの中心波長λ1と
発光の中心波長λ2とを一致せしめるべく、λ2≒
65nｍのGaP単結晶から成る緑色のLEDペレツト
を用いる。上記LEDペレツトの一方の電極面を
絶縁基板１の受光素子２ａ，２ｂが対向する一主
面１ａに、第２図の如くパターン印刷された導電
性接着剤４を介して破線で示すようにフエイスダ
ウンボンデイングする。そして、他方の電極面を
ワイヤーリード５ａ，５ｂを用いて絶縁基板１上
の第１・第２の発光素子２ａ，２ｂの間に設けら
れた電極膜６にボンデイングする。これ等第１・
第２の発光素子２ａ，２ｂは入力信号の給電に対
して独立して応答し発光すべく上記導電性接着剤
４及び電極膜６は結線される。 On the other hand, the first and second light emitting elements 2a and 2b are arranged so that the center wavelength λ 1 of the first and second light receiving elements 3a and 3b and the center wavelength λ 2 of light emission match, λ 2 ≒
A green LED pellet made of 65nm GaP single crystal is used. One electrode surface of the LED pellet is attached to the main surface 1a of the insulating substrate 1, where the light receiving elements 2a and 2b face each other, as shown in FIG. Bonding down. Then, the other electrode surface is bonded to the electrode film 6 provided between the first and second light emitting elements 2a and 2b on the insulating substrate 1 using wire leads 5a and 5b. This is the first one.
The conductive adhesive 4 and the electrode film 6 are connected so that the second light emitting elements 2a and 2b respond independently to the power supply of an input signal and emit light.
そして最終的に上記第１・第２の発光素子２
ａ，２ｂの入力線並び第１・第２の受光素子３
ａ，３ｂの出力線を司どるリードフレーム１０，
１１…を結合して第１図に示す如く外来光を遮蔽
するモールド体１２でモールドし半導体光結合装
置を完成する。 Finally, the first and second light emitting elements 2
Input lines a and 2b lined up first and second light receiving elements 3
A lead frame 10 that controls the output lines of a and 3b,
11... are combined and molded with a mold body 12 that blocks external light as shown in FIG. 1 to complete a semiconductor optical coupling device.
この様にして製造された半導体光結合装置の受
光側は第１・第２の受光素子３ａ，３ｂが直列接
続関係にあり等価的に第３図の如き回路図に置換
することができる。即ち、受光素子３ａ，３ｂは
夫々直流電流源１３ａ，１３ｂとダイオード１４
ａ，１４ｂとの逆並列回路で表わすことができ
る。第３図に於いて、Ｒは出力端子１５，１６間
に接続された負荷抵抗である。 On the light-receiving side of the semiconductor optical coupling device manufactured in this way, the first and second light-receiving elements 3a and 3b are connected in series, and the circuit diagram can be equivalently replaced with the circuit diagram shown in FIG. That is, the light receiving elements 3a and 3b are connected to the DC current sources 13a and 13b and the diode 14, respectively.
It can be represented by an anti-parallel circuit with a and 14b. In FIG. 3, R is a load resistance connected between output terminals 15 and 16.
而して、第１の発光素子２ａに入力信号がリー
ドフレーム１０，１０を介して給電されると、該
第１の発光素子２ａは発光動作し絶縁基板１を透
過して対向する第１の受光素子３ａを光照射す
る。光照射された第１の受光素子３ａはアモルフ
アスシリコン半導体層８の主にＩ型層に於いて自
由状態の電子及びホールが発生しその各々はPIN
接合電界に引かれて移動して透明電極膜７並びに
金属電極膜９間に光起電力を発生せしめる。とこ
ろが第２の発光素子２ｂは発光動作状態にないの
で、対向する第２の受光素子３ｂは、上記光起電
力による直流電流源１３ａと逆方向のダイオード
１４ｂ状態にある。従つて負荷抵抗Ｒには光電流
には流れず出力端子１５，１６間には出力が得ら
れない。 When an input signal is supplied to the first light emitting element 2a via the lead frames 10, 10, the first light emitting element 2a operates to emit light, transmitting light through the insulating substrate 1 to the opposing first light emitting element 2a. The light receiving element 3a is irradiated with light. In the first light receiving element 3a irradiated with light, free state electrons and holes are generated mainly in the I-type layer of the amorphous silicon semiconductor layer 8, and each of them becomes a PIN.
It moves under the influence of the junction electric field and generates a photovoltaic force between the transparent electrode film 7 and the metal electrode film 9. However, since the second light emitting element 2b is not in a light emitting operation state, the opposing second light receiving element 3b is in a diode 14b state in the opposite direction to the photovoltaic DC current source 13a. Therefore, no photocurrent flows through the load resistor R, and no output is obtained between the output terminals 15 and 16.
一方、この状態で第２の発光素子２ｂに入力信
号を供給し発光せしめると第２の受光素子３ｂは
逆方向のダイオード１４ｂ状態から順方向の直流
電流源１３ｂとなり、負荷抵抗Ｒに光電流が流れ
る。その結果出力端子１５，１６間に出力信号が
得られる。この様に２個の受光素子３ａ，３ｂを
直列接続し、夫々に入力信号に対して独立して発
光動作する２個の発光素子２ａ，２ｂを対向せし
めることによつて、出力信号として入力信号の論
理積を得ることができる。 On the other hand, when an input signal is supplied to the second light emitting element 2b in this state to cause it to emit light, the second light receiving element 3b changes from the reverse direction diode 14b state to the forward direction DC current source 13b, and a photocurrent is applied to the load resistor R. flows. As a result, an output signal is obtained between output terminals 15 and 16. By connecting the two light-receiving elements 3a and 3b in series in this way and having the two light-emitting elements 2a and 2b facing each other, each of which operates to emit light independently in response to an input signal, it is possible to receive the input signal as an output signal. We can obtain the logical product of .
同様の考え方から第４図に示す如く第１の受光
素子３ａと第２の受光素子３ｂとを並列関係に接
続すると少なくとも第１・第２の発光素子２ａ，
２ｂの何れか一方が発光することにより出力端子
１５，１６間に論理和出力を得ることができる。 From the same idea, if the first light receiving element 3a and the second light receiving element 3b are connected in parallel as shown in FIG. 4, at least the first and second light emitting elements 2a,
When either one of the terminals 2b emits light, an OR output can be obtained between the output terminals 15 and 16.
ところで、斯る半導体光結合装置において、第
１・第２の発光素子２ａ，２ｂからの出射光にク
ロストークが生じ、第１の発光素子２ａ（または
第２の発光素子２ｂ）からの出射光が第１の受光
素子３ａ（または第２の受光素子３ｂ）だけでな
く、第２の受光素子３ｂ（または第１の受光素子
３ａ）にも照射されると誤つた信号を出力するこ
とになる。 By the way, in such a semiconductor optical coupling device, crosstalk occurs in the light emitted from the first and second light emitting elements 2a and 2b, and the light emitted from the first light emitting element 2a (or the second light emitting element 2b) If the light is irradiated not only to the first light receiving element 3a (or second light receiving element 3b) but also to the second light receiving element 3b (or first light receiving element 3a), an erroneous signal will be output. .
ここで、斯るクロストークを抑制するために
は、第１・第２の発光素子２ａ，２ｂの間隔を大
きくすれば良いが、斯る間隔を単に大きくするだ
けでは、この間隔部分がデツドスペースとなつて
不要に装置の大型化を招くことになる。 Here, in order to suppress such crosstalk, it is sufficient to increase the interval between the first and second light emitting elements 2a and 2b, but simply increasing the interval will cause this interval to become a dead space. This results in an unnecessary increase in the size of the device.
そこで、本実施例によれば、第１・第２の発光
素子２ａ，２ｂの間隔を大きくすることにより出
来た空間に電極膜６を配することによつて、斯る
電極膜６を他の部分に配するに較べて装置の大型
化を防ぎ、かつクロストークの発生を抑制してい
る。 Therefore, according to this embodiment, by disposing the electrode film 6 in the space created by increasing the interval between the first and second light emitting elements 2a and 2b, the electrode film 6 can be This prevents the device from becoming larger and suppresses the occurrence of crosstalk compared to placing it in sections.
第５図は本発明の更に他の実施例であり、第
１・第２の発光素子２ａ，２ｂをアモルフアス半
導体で形成したところに特徴が存在する。製造方
法は受光素子３ａ，３ｂと同様にプラズマ反応に
より形成される。即ち、絶縁基板１の一主面１ａ
に透明電極膜１７をパターン形成した後、反応ガ
スとしてSiH4を70％、メタンCH4を30％導入し
PIN接合型のアモルフアスシリコンカーバイド
（ａ−SiC：Ｈ）半導体層１８を得る。この時Ｐ
型Ｎ型を制御する不純物ガスとしてB2H6及び
PH3が夫々1000ppmの濃度で使用される。得られ
たPIN各膜厚は順次100〜200Å、5000Å、500Å
であり発光の中心波長λ3は680nｍであつた。 FIG. 5 shows still another embodiment of the present invention, which is characterized in that the first and second light emitting elements 2a and 2b are formed of amorphous semiconductors. The manufacturing method is similar to that of the light receiving elements 3a and 3b, and is formed by plasma reaction. That is, one main surface 1a of the insulating substrate 1
After patterning the transparent electrode film 17, 70% SiH 4 and 30% methane CH 4 were introduced as reactive gases.
A PIN junction type amorphous silicon carbide (a-SiC:H) semiconductor layer 18 is obtained. At this time P
B 2 H 6 and
PH 3 is used at a concentration of 1000 ppm each. The obtained PIN film thicknesses are sequentially 100 to 200 Å, 5000 Å, and 500 Å.
The central wavelength of light emission λ 3 was 680 nm.
一方先の実施例に於ける第１・第２の受光素子
３ａ，３ｂはアモルフアスシリコン半導体層８か
ら成つていたがその中心波長λ2が580nｍである
為に本実施例には不都合である。その為に本実施
例に於いては第１・第２の受光素子３ａ，３ｂは
中心波長λ4が上記発光素子２ａ，２ｂのそれと同
じ680nｍであるアモルフアスシリコンゲルマニ
ウム（ａ−SiGe：Ｈ）半導体層８が使用される。
この時導入される反応ガスはSiH4：60％、ゲル
マン（GeH4）：40％である。 On the other hand, the first and second light-receiving elements 3a and 3b in the previous embodiment were made of an amorphous silicon semiconductor layer 8, but since the center wavelength λ 2 of the layer 8 was 580 nm, this was inconvenient for this embodiment. be. Therefore, in this embodiment, the first and second light receiving elements 3a and 3b are made of amorphous silicon germanium (a-SiGe:H) whose center wavelength λ 4 is 680 nm, which is the same as that of the light emitting elements 2a and 2b. A semiconductor layer 8 is used.
The reaction gases introduced at this time were SiH 4 :60% and germane (GeH 4 ): 40%.
斯る構造によれば発光素子２ａ，２ｂとしてア
モルフアス半導体を使用することによつて安価に
製造することができるのみならず、絶縁基板１上
にワイヤリード５ａ，５ｂを介さず直接金属電極
膜１９に延在せしめることができ、モールド体１
２を充填する際の上記ワイヤリード５ａ，５ｂの
断線事故を回避することができる。 According to such a structure, not only can the light emitting elements 2a and 2b be manufactured at low cost by using amorphous semiconductors, but also the metal electrode film 19 can be directly formed on the insulating substrate 1 without using the wire leads 5a and 5b. can be extended to the mold body 1
It is possible to avoid an accident of disconnection of the wire leads 5a and 5b when filling the battery.
また、上述の如くアモルフアス半導体層８，１
８は、同一素材で発光素子を形成した場合と受光
素子を形成した場合とでは発光中心波長が受光中
心波長に較べ長波長側に移動する特性を有してい
ると共に、反応ガスの組成並びに組成比を適宜選
択することによつて可視光領域に限らず紫外・赤
外の領域に感度を有する素子を自由に形成するこ
とができる。更にアモルフアス半導体層の形成時
に付与する高周波電力並びに水素濃度を増大せし
めることによつて、アモルフアス半導体層を微結
晶化し変換効率の向上を図つても良く、PIN接合
型でなくてもPN接合、ヘテロフエイス接合、シ
ヨツトキバリア型でも実現し得る。また受光素子
を形成するアモルフアス半導体層８は上述の如き
光照射に対し光起電力を発生せしめる接合形態を
持たず、光照射によつて導電率を上昇する光導電
効果を利用したものであつても本発明の作用効果
を妨げるものではない。 Further, as described above, the amorphous semiconductor layers 8, 1
8 has a characteristic that the emission center wavelength shifts to the longer wavelength side compared to the light reception center wavelength when the light emitting element and the light receiving element are formed from the same material, and the composition of the reactant gas and the composition By appropriately selecting the ratio, it is possible to freely form an element having sensitivity not only in the visible light region but also in the ultraviolet and infrared regions. Furthermore, by increasing the high-frequency power and hydrogen concentration applied during the formation of the amorphous semiconductor layer, the amorphous semiconductor layer can be microcrystallized and the conversion efficiency can be improved. It can also be realized with a face joint or a shot barrier type. Further, the amorphous semiconductor layer 8 forming the light receiving element does not have a bonding form that generates a photovoltaic force in response to light irradiation as described above, but utilizes the photoconductive effect that increases the conductivity by light irradiation. However, this does not impede the effects of the present invention.
尚、以上の説明に於いては発光素子、受光素子
は夫々２個用いて論理積出力若しくは論理和出力
を得ていたが、何にもこれに限定されるものでな
く、例えば論理積回路と論理和回路とを同一基板
に多数配置しそれ等を結線しても良く、また配置
状態も一次元に限ることなく二次元方向に拡がつ
ても良い等の種々の変更が考えられる。 In the above explanation, two light-emitting elements and two light-receiving elements were used to obtain an AND output or an OR output, but the invention is not limited to this, and for example, an AND circuit and Various modifications are conceivable, such as arranging a large number of OR circuits on the same board and connecting them, and the arrangement state is not limited to one dimension, but may be extended in two dimensions.
本発明半導体光結合装置は以上の説明から明ら
かな如く、複数の発光素子と、該複数の発光素子
の夫々に入力信号を給電するための電極と、上記
発光素子からの発光を受光して夫々電気信号に変
換する非単結晶半導体から成る複数の受光素子
と、該複数の受光素子の夫々から出力信号を取り
出す取出電極とを備え、上記複数の発光素子の間
に、上記電極の少なくとも１つを配設し、更に、
上記複数の受光素子の少なくとも２個の取出電極
を、これ等少なくとも２個の受光素子と対向する
発光素子へ給電される信号の論理積または論理和
を得るべく電気的に直列または並列に結合せしめ
たので、装置の大型化を招くことなく発光素子の
出射光のクロストーク発生を抑制し、上記２個の
受光素子から入力信号に対する論理的な出力信号
を正確に得ることができ、しかも入力信号は一旦
光信号に変換されている為に安価且つ製造が容易
な非単結晶半導体を使用したにも拘らず、単結晶
半導体を用いたものに較べ遜色のない応答速度を
実現することができる。 As is clear from the above description, the semiconductor optical coupling device of the present invention includes a plurality of light emitting elements, an electrode for feeding an input signal to each of the plurality of light emitting elements, and a plurality of electrodes for receiving light emitted from the light emitting elements. A plurality of light-receiving elements made of a non-single-crystal semiconductor that converts into electrical signals, and an extraction electrode that extracts an output signal from each of the plurality of light-receiving elements, and at least one of the electrodes is arranged between the plurality of light-emitting elements. and further,
At least two extraction electrodes of the plurality of light-receiving elements are electrically coupled in series or in parallel to obtain a logical product or a logical sum of signals supplied to the light-emitting element facing the at least two light-receiving elements. Therefore, it is possible to suppress the occurrence of crosstalk in the light emitted from the light emitting element without increasing the size of the device, and to accurately obtain a logical output signal in response to the input signal from the two light receiving elements. Although a non-single-crystal semiconductor is used, which is cheap and easy to manufacture because it has been converted into an optical signal, it is possible to achieve a response speed comparable to that using a single-crystal semiconductor.
第１図は本発明の一実施例断面図、第２図はそ
の製造工程の一部を説明する為の平面図、第３図
はその受光側の等価回路図、第４図は本発明の他
の実施例の受光側等価回路図、第５図は更に他の
実施例の断面図、を夫々示している。
１……透光性絶縁基板、２ａ，２ｂ……第１・
第２の発光素子、３ａ，３ｂ……第１・第２の受
光素子。
Fig. 1 is a sectional view of an embodiment of the present invention, Fig. 2 is a plan view for explaining part of the manufacturing process, Fig. 3 is an equivalent circuit diagram of the light receiving side, and Fig. 4 is a cross-sectional view of an embodiment of the present invention. FIG. 5 shows an equivalent circuit diagram on the light receiving side of another embodiment, and FIG. 5 shows a sectional view of still another embodiment. 1... Translucent insulating substrate, 2a, 2b... 1st.
Second light emitting element, 3a, 3b...first and second light receiving elements.
Claims (1)
に入力信号を給電するための電極と、上記発光素
子からの発光を受光して夫々電気信号に変換する
非単結晶半導体から成る複数の受光素子と、該複
数の受光素子の夫々から出力信号を取り出す取出
電極とを備え、上記複数の発光素子の間に、上記
電極の少なくとも１つを配設し、更に、上記複数
の受光素子の少なくとも２個の取出電極を、これ
等少なくとも２個の受光素子と対向する発光素子
へ給電される入力信号の論理積または論理和を得
るべく電気的に直列または並列に結合したことを
特徴とする半導体光結合装置。 ２ 上記複数の発光素子は透光性基板の一方の一
主面に配置され、複数の受光素子は他方の一主面
に形成されて夫々は対向することを特徴とした特
許請求の範囲第１項記載の半導体光結合装置。 ３ 上記非単結晶半導体はアモルフアス半導体で
あることを特徴とした特許請求の範囲第１項及び
第２項何れか記載の半導体光結合装置。[Scope of Claims] 1 A plurality of light emitting elements, an electrode for feeding an input signal to each of the plurality of light emitting elements, and a non-single crystal that receives light emitted from the light emitting elements and converts them into electrical signals, respectively. It comprises a plurality of light receiving elements made of a semiconductor, and an extraction electrode for extracting an output signal from each of the plurality of light receiving elements, at least one of the electrodes is disposed between the plurality of light emitting elements, and further, the At least two extraction electrodes of the plurality of light receiving elements are electrically coupled in series or parallel to obtain a AND or OR of input signals supplied to the light emitting element facing the at least two light receiving elements. A semiconductor optical coupling device characterized by: 2. Claim 1, wherein the plurality of light emitting elements are arranged on one principal surface of the light-transmitting substrate, and the plurality of light receiving elements are formed on the other principal surface, and are opposed to each other. A semiconductor optical coupling device as described in . 3. The semiconductor optical coupling device according to claim 1 or 2, wherein the non-single crystal semiconductor is an amorphous semiconductor.
Priority Applications (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56200469A JPS58101475A (en) | 1981-12-11 | 1981-12-11 | Semiconductor photocoupler |
| US06/447,195 US4626878A (en) | 1981-12-11 | 1982-12-06 | Semiconductor optical logical device |
| DE8282111464T DE3279526D1 (en) | 1981-12-11 | 1982-12-10 | Semiconductor optical logic device |
| EP82111464A EP0081827B1 (en) | 1981-12-11 | 1982-12-10 | Semiconductor optical logic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56200469A JPS58101475A (en) | 1981-12-11 | 1981-12-11 | Semiconductor photocoupler |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58101475A JPS58101475A (en) | 1983-06-16 |
| JPH0230191B2 true JPH0230191B2 (en) | 1990-07-04 |
Family
ID=16424831
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56200469A Granted JPS58101475A (en) | 1981-12-11 | 1981-12-11 | Semiconductor photocoupler |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58101475A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61121764U (en) * | 1985-01-14 | 1986-07-31 | ||
| JPS6455910U (en) * | 1987-09-30 | 1989-04-06 | ||
| JP3638328B2 (en) * | 1994-12-30 | 2005-04-13 | 株式会社シチズン電子 | Surface mount type photocoupler and manufacturing method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4985993A (en) * | 1972-12-20 | 1974-08-17 | ||
| JPS5382187A (en) * | 1976-12-27 | 1978-07-20 | Nec Corp | Photo coupler element |
-
1981
- 1981-12-11 JP JP56200469A patent/JPS58101475A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4985993A (en) * | 1972-12-20 | 1974-08-17 | ||
| JPS5382187A (en) * | 1976-12-27 | 1978-07-20 | Nec Corp | Photo coupler element |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58101475A (en) | 1983-06-16 |
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