JPH02301273A - Picture display system - Google Patents

Abstract

PURPOSE:To prevent baking caused when a picture pattern smaller than the screen is displayed by selecting a timing signal at random from plural timing signals with a different phase. CONSTITUTION:The number of scanning lines of a video signal by the high definition television system such as a MUSE base band signal is decreased by a scanning line number conversion means 4 and the resulting signal is stored in a time axis correction buffer memory 5. Then the generating timing of an address signal is controlled to vary the readout timing of the signal from the buffer memory 5 thereby moving the picture display position and avoiding the relation of position between the picture area and the space area from being fixed. The generating timing of the address signal is changed by generating plural timing signals with a different phase in advance, selecting one timing signal at random among them and using the selected timing signal to control the readout control means. Thus, baking caused by fixed picture and space areas is prevented.

Description

[Detailed Description of the Invention] [Industrial Field of Application] The present invention provides video signals based on high-definition television system,
The present invention relates to an image display system that converts into a video signal and displays it according to the current television system, and particularly relates to processing of the positional relationship between an image area and a margin area on the screen.

[Prior art] As a new television system to replace the current television system, it not only improves image and sound quality, but also provides advanced visual psychological effects such as a sense of presence and force that far exceeds that of the current television system. High-definition television systems, such as high-definition systems, have been proposed.

Since the high-definition system is significantly different from current television systems, such as the NTSC system, in screen format, scanning system, audio system, etc., high-definition signals cannot be reproduced as they are using a receiver based on the NTSC system. For this reason, differences in the number of scanning lines, aspect ratio, field frequency, etc. between both systems are absorbed and the high-definition signal is converted to NTSC.
High-definition/NTS to convert to signal and display
A C converter (down converter) has been proposed.

Figure 7 shows an example of the down converter output displayed on an NTSC screen.
In this mode, the 1032 effective scanning lines of the SE signal are reduced to 173:344 and allocated to the 485 effective scanning lines of the NTSC system, and displayed on the NTSC screen without changing the aspect ratio of 16:9 of the high-definition system. be. According to this mode, the aspect ratio of the NTSC system is 4:3 (
16:12), a margin area of about 10% of the number of effective scanning lines appears at the top and bottom of the screen, but since the horizontal direction matches that of a high-definition screen, it is difficult to obtain an image with the intended composition in high-definition. I can do it.

[Problems to be Solved by the Invention] By the way, in the conventional example described above, the blank areas that occur at the top and bottom of the screen are displayed with a black signal, so if this display continues for a long time, the degree of fatigue of the phosphor in the picture tube will deteriorate. Since the area and the margin area are different, when normal display using the entire screen is performed, the margin area becomes brighter and streaks appear at the boundary of the area, which is an inconvenience.

This is what is called CRT burn-in.

An object of the present invention is to prevent the burn-in phenomenon that occurs when displaying an image smaller than the screen.

[Means to solve the problem]

The present invention provides an image display system that converts a high-definition television system video signal into a current television system video signal and displays it on the screen. A scanning line number conversion means for reducing the number of scanning lines, a time axis correction buffer memory for temporarily storing the video signal converted by the conversion means, and a readout device for generating a read address signal for reading the video signal stored in the buffer memory. The read address signal is output in synchronization with a timing signal indicating the display position on the screen of the video signal stored in the buffer memory, and the timing signal is output at multiple timings having different phases from each other. One timing signal is randomly selected from among the signals.

[For production]

Video signal based on high-definition television system, e.g. BS
The number of scanning lines of the MUSE baseband signal input through the tuner is reduced by the scanning line number conversion means, and for example, a 1-line signal is generated from a 3-line signal and stored in a time axis correction buffer memory. .

The signals stored in the buffer memory are read out by a read address signal synchronized with the synchronization signal of the current television system, for example the NTSC system, and are supplied to the NTSC receiver together with the horizontal and vertical synchronization signals of the NTSC system.

In this case, if the signals stored in the buffer memory are always read out at the same timing, the positional relationship between the image area displayed on the screen of the receiver and the blank area will be fixed. Therefore, in the present invention, by controlling the generation timing of the address signal and changing the timing of reading the signal from the buffer memory, the display position of the image is moved and the positional relationship between the image area and the margin area is not fixed. ing.

To change the generation timing of the address signal, a plurality of timing signals having different phases from each other are generated in advance, and one timing signal is randomly selected from among them, for example, in connection with turning on the power, and this selected timing signal is This is done by controlling the readout control means.

In this way, it is possible to prevent burn-in caused by fixing the image area and the margin area.

〔Example〕

FIG. 1 is a block diagram showing an embodiment of an image display method according to the present invention. In this embodiment, an example will be described in which a MUSE signal obtained by band-compressing a high-definition signal for satellite broadcasting is converted into an NTSC signal and displayed.

In FIG. 1, a MUSE baseband signal received by a BS antenna and obtained through a BS tuner passes through a low-pass filter 1 with a cut-off frequency of 8.15 MHz, and then is converted into a digital signal by an AD converter 2. The frequency of sampling signal SP1 in AD converter 2 is MU
The SE resampling frequency is 16.2 MHz.

The MUSE signal converted into a digital signal by the AD converter 2 is de-emphasized by a de-emphasis circuit 3 and then supplied to a vertical filter 4 .

The vertical filter 4 generates a 1-line signal from 3 lines of the MUSE signal, reduces the 1032 effective scanning lines of the MUSE signal to 173 344 lines, and generates a luminance signal Y9 color signal R-Y and B of each line. -Y is supplied to the time axis buffer 5.

The time axis buffer 5 is a 32.4M field memory that sequentially stores one field's worth of luminance signals and color difference signals.
Each signal is written to the storage location specified by the write address signal WA having a clock frequency of 15.12 (=16.2X14/15) MHz.
A signal is read from the storage location using a read address signal RA having a clock frequency of . For details of the scanning line conversion in the vertical filter 4 and time axis buffer 5, please refer to the patent application filed in 1983 by the applicant.
-242605 (Title of invention: rMUsE-NTS
C conversion method").

The signal read out from the time axis buffer 5 by the read address signal RA is converted into an NTSC format signal with a horizontal synchronization signal HD and a vertical synchronization signal VD added thereto.
system video signal, and further has a frequency of 7.56MI (z
The signal SP2 is sampled by the DA converter 7, which converts the signal into an analog signal, and then supplies the signal to the NTSC receiver 8.

On the other hand, the MU converted into a digital signal by the AD converter 2
The SE signal is supplied to the MUSE timing generation circuit 9. This MUSE timing generation circuit 9 detects a horizontal synchronization signal and a frame pulse as a vertical synchronization signal from the MUSE signal, generates various timing signals, and
Converter 2. The vertical filter 42 is supplied to the time base buffer 5 and the NTSC timing generation circuit 10, which will be described later.

The horizontal synchronization signal is inserted into each line of the MtJSE transmission signal from the 1st sample point to the 11th sample point with the polarity reversed for each line.
Regenerate the 6.2MHz resampled signal. Also,
The frame pulse is inserted into each frame of the MUSE transmission signal using two lines, and the waveforms of the two lines have opposite polarities, so they can be easily distinguished from the video signal. synchronization signal) can be detected accurately.

The NTSC timing generation circuit 10 generates various timing signals based on the synchronization signal detected by the MUSE timing generation circuit 9 and the generated timing signal,
The time axis buffer 5 has a read address signal RA with a frequency of 15.12 MHz, an NTSC formatter 6 and an NTSC formatter 6.
Horizontal and vertical synchronizing signals HD and VD,
A sampling signal SP2 with a frequency of 7.56 MHz is supplied to the DA converter 7.

FIG. 2 is a block diagram showing a part of the configuration of the NTSC timing generation circuit 10, in which the timing signal TM, read address signal RA, horizontal synchronization signal HD and vertical synchronization signal VD are shown.
This shows a circuit that generates .

This circuit generates a plurality of timing signals T based on the outputs of horizontal and vertical counters 20 and 21 and vertical counter 21.
The plurality of image display timing generation circuits 22a to 22n that generate a=Tn select any one timing signal from the timing signals Ta-Tn to generate the timing signal TM.
A read address generation circuit 24 generates a read address signal RA for the time axis buffer 5 based on the output of the horizontal counter 20 and the timing signal TM, and a horizontal and vertical synchronization signal HD is output from the outputs of both counters 20 and 21. and a timing signal Ta that controls the synchronization signal generation circuit 25 and selector 23 that generate
It consists of a select data generation circuit 26 that selects one timing signal from -Tn.

The select data generation circuit 26 includes a random number generator 27 that generates random numbers with a certain probability distribution every time the power is turned on, a distribution converter 28 that converts the probability distribution of the random number generator 27, a fixed data generator 29, and a distribution converter. switch 30 and switch 3 for switching between the output of 28 and the output of the fixed data generator 29;
It consists of a register 31 that stores data selected by 0.

If the output of the random number generator 27 is a uniform random number, the distribution characteristic will be rectangular, so there is a possibility that burn-in will occur at the upper and lower limit positions, so the distribution converter 28 converts the distribution characteristic to a normal distribution or the like. If the characteristics of the random number generator 27 itself are normal distribution, this distribution converter 28 becomes unnecessary.

In the timing generation circuit 10, the horizontal counter 20 divides the frequency of the 15.12 MHz input clock signal to 15.
A horizontal scanning signal of 75 KHz (=15.12 MHz/960) is generated and supplied to the vertical counter 21. The vertical counter 21 counts the horizontal scanning signals and outputs line data indicating the line number of each line of one field, and outputs it to the image display timing generation circuits 22a to 22n. The timing generation circuits 22a to 22n generate timing signals Ta-Tn having mutually different phases based on the supplied line data.

Each timing signal TaxTn is a signal that defines the display position of the video signal stored in the time axis buffer 5 on the NTSC screen, and is a signal that defines the display position of the video signal stored in the time axis buffer 5.
The level is "1" for 344 lines (172 lines per field) in a frame (frame), and as shown in the waveform diagram of FIG. 3, they are generated with a phase shift of a plurality of lines from each other. From the timing signals Ta-Tn generated in this way, one timing signal is selected by the selector 23 based on the select data supplied from the select data generation circuit 26,
It is output as a timing signal TM.

Next, the timing signal TM is sent to the read address generation circuit 2.
4. The read address generation circuit 24 generates an address signal RA, which is reset every time the timing signal TM arrives and increases sequentially from the first address value, at a frequency of 1.
It outputs at 5.12 MHz, supplies it to the time axis buffer 5, and reads out 344 video signals for one frame (172 video signals for one field).

The synchronization signal generation circuit 25 generates an NTSC horizontal synchronization signal HD and a vertical synchronization VD based on the data output from the horizontal and vertical counters 20 and 21, and
It is supplied to the SC formatter 6.

FIG. 4 is a block diagram showing the configuration of the NTSC formatter 6, which adds first and second selectors 40 and 41, a margin level generator 42, a blanking level generator 43, and horizontal and vertical synchronizing signals HD and VD. It consists of an OR circuit 44 that generates a blanking signal BL.

The first selector 40 switches between the video signal read from the time axis buffer 5 and the video signal output from the margin level generator 42 using the timing signal TM described above. The timing signal TM receives the video signal from the axis buffer 5 at level "0".
'', the video signal from the margin level generator 42 is output. Therefore, the output of the margin level generator 42 is set to the same level as the brightness level of the image area,
If the hue is also inconspicuous, the brightness level of the entire screen is averaged, and burn-in of an unbalanced screen is reduced compared to the conventional method in which blank areas are displayed at a black level.

The second selector 41 switches between the output from the first selector 40 and the output from the black level generator 43 according to the blanking signal BL, and when the blanking signal BL is at level "1", the blanking level generator is switched. The blanking level signal from 43 is sent to selector 4 while the level is "0".
Each video signal from 0 is selected, a planking signal is added to the video signal, and the result is output.

Next, the operation of this embodiment having such a configuration will be explained.

The MUSE baseband signal input through the BS tuner is subjected to 3-line/1-line conversion by the vertical filter 4 to generate 344 effective scanning lines from 1032 effective scanning lines. The generated luminance signal Y and color difference signals RY and BY of each line are sequentially written into the time axis buffer 5. The signal written in the time axis buffer 5 is read out by the read address signal RA which is output while the timing signal TM is at level "1", and is supplied to the NTSC Formantaro. In the NTSC7 Ohmatsuta 6, the video signal of the margin area and the blanking signal are added to the NT
Output as an SC video signal.

By the way, since the timing signal TM is a signal randomly selected from among the plurality of timing signals T a - T n as described above, for example, if the timing signal Ta is selected, the result shown in FIG. 5(a) is An image is displayed at the top of the screen as shown, and if the timing signal Tn is selected, an image is displayed at the bottom of the screen as shown in FIG. Therefore, if the timing signal TM is randomly switched each time the power is turned on by the switching signal from the select data generation circuit 26, the position of the image area changes on the screen, which prevents burn-in caused by fixing the image area and the margin area. Reduced. In addition, the switch 30
It is also possible to fix the image area by selecting the output of the fixed data generator 29 and fixing the timing signal TM.

FIG. 6 is a block diagram showing another embodiment of the NTSC timing generation circuit 10. This embodiment uses a plurality of image display timing generation circuits 22a to 22 in the configuration shown in FIG.
An image display timing generation circuit 22 and an n-1 stage shift register 32 for delaying the output of the generation circuit 22 are provided in place of the generation circuit 22 and the shift register 32.
The configuration is such that each output signal is supplied to the selector 23 as a timing signal Ta-Tn.

In addition, although the above-mentioned embodiment described the case of converting the MUSE system to the NTSC system, it goes without saying that it can be applied to conversion between other systems. Further, in the above-described embodiment, the timing signal TM is selected in conjunction with turning on the power, but the timing signal TM is not limited to this and may be selected in accordance with other triggers.

〔Effect of the invention〕

According to the image display method according to the present invention, when displaying an image smaller than the screen, the display position of the image area is changed randomly, so that burn-in caused by partial use of the screen can be prevented. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the image display method according to the present invention, FIG. 2 is a block diagram showing a partial configuration of the NTSC timing generation circuit in FIG. 1, and FIG. 3 is the operation of FIG. 2. FIG. 4 is a block diagram showing the NTSC formatter in FIG. 1, FIG. 5 is a screen display example according to the present invention, and FIG. 6 is another embodiment of the NTSC timing generation circuit. The block diagram, FIG. 7, is an example of a screen display using the conventional method. Patent applicant Pioneer Corporation Waveform diagram screen display example Figure 5 42 4.3 /'NTS
C-Formatsuta Figure 4

Claims (1)

[Scope of Claims] In an image display method that converts a video signal according to a high-definition television system into a video signal according to a current television system and displays it on a screen, scanning of the video signal according to the high-definition television system is performed. A scanning line number conversion means for reducing the number of lines; a time axis correction buffer memory for temporarily storing the video signal converted by the conversion means; and a read address signal for reading out the video signal stored in the buffer memory. The read address signal is output in synchronization with a timing signal indicating the display position on the screen of the video signal stored in the buffer memory, and the timing signals are in phase with each other. An image display method characterized in that one timing signal is randomly selected from a plurality of timing signals with different values.