JPH0229991B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a signal extraction calculation device, such as a sampling oscilloscope, having a sampling device.

Generally, a sampled output of a signal under test can be obtained from an oscilloscope or the like having a sampling device. However, these outputs include correction signals for adjusting the position reflected on the cathode ray tube screen, and most of the signals under measurement have a DC component superimposed on them, so they do not directly indicate the magnitude of the signal. In other words, in general, these outputs are (signal component) + (DC component of signal) + (measuring instrument drift)
+ (measurement instrument DC component). Therefore, it is difficult to read the voltage difference between any two points in the signal waveform under test.

It is easy to think of providing two sampling circuits to obtain these two voltages, but sampling circuits are particularly sensitive to high frequency characteristics and DC voltage offsets, which are susceptible to variations in component characteristics, circuit assembly variations, and temperature changes. Therefore, it is difficult to use this method because different errors occur in the voltage outputs at the two points due to large variations.

The present invention provides a signal extraction arithmetic device including a sampling device that improves these drawbacks. Examples will be described below with reference to FIGS. 1 to 5.

FIG. 1 is a block diagram showing an embodiment of the present invention, in which the signal under test a passes through a synchronization signal extraction circuit 1, is selected as another synchronization signal b by a synchronization signal source selection switch 2, and is converted into a slope signal by a synchronization circuit 3. A starting signal is generated to drive the slope signal generating circuit 4. The slope signal is applied to a comparator 6 together with a sampling time control signal provided by a variable voltage source circuit 5, and its output is supplied to a sampling pulse generation circuit 7. The sampling pulse outputted from the sampling pulse generation circuit 7 is supplied to a sampling gate and hold circuit 8, and samples the signal under measurement that is also applied to the circuit 8.

The sampling signal obtained by the sampling gate and hold circuit 8 is converted into a digital signal by an analog-to-digital conversion circuit 9, and a calculation output c is generated by a calculation circuit 10 equipped with a register according to instructions from the variable voltage source circuit 5. .

2 and 3 show specific examples of the embodiment shown in FIG. 1. FIG. The synchronous signal extraction circuit 1 consists of a matching branch circuit consisting of a capacitance C ₁ and inductances L ₁ and L ₂ , and a buffer amplifier formed by a transistor Q ₁ , and the synchronous circuit 3 includes a synchronous level comparison comparator U ₁ and an Esaki diode D ₁ . The waveform is shaped by the circuit as the main component, and the inductance L ₃
A pulse signal for starting the slope signal is formed by a differentiator circuit using capacitance _C2 . Further, the slope signal generation circuit 4 includes gate circuits U ₂ -U ₃ and gate circuit U _{4 .}
- two bistable circuits with U ₅ and transistor Q ₂ ,
Q ₃ , resistor R ₁ , capacitance C ₃ and transistor Q ₄ , resistor R ₂ , and capacitance C ₄ are the main components.The output is temperature compensated by transistors Q ₅ and Q _6. provided via a buffer amplifier. The operation of the slope signal generating circuit 4 shown in FIG. 2 is well known and will not be described here.

Receiving a sampling time control signal h having a voltage value corresponding to the slope signal output and the sampling time from the variable voltage source circuit 5, the comparator 6 uses the comparison output as a main component of the Esaki diode _D2 of the sampling pulse generation circuit 7. The pulse shaping circuit is driven, and an amplification shaping circuit mainly composed of transistor Q ₇ forms a sampling pulse, and an amplification shaping circuit mainly composed of transistor Q ₈ forms a sample hold pulse. The sampling gate and hold circuit 8 consists of a sampling gate mainly composed of diodes D _{3 ,} D ₄ , D ₅ , and D ₆ that receive balanced sampling pulses from capacitances C ₅ and C 6, and a hold circuit composed of a transistor Q ₁₀ and a capacitance C ₇ . becomes transistor Q ₉ ,
A buffering high input resistance amplifier circuit consisting of Q ₁₁ and Q ₁₂ is placed between each stage.

The register and arithmetic circuit 10 that receives the output of the analog-to-digital conversion circuit 9 consists of at least two registers U ₆ and U ₇ and a digital adder/subtractor U ₈ .
The sampling output is read as appropriate according to the timing signal from the variable voltage source circuit 5, addition and subtraction are performed, and the output C is provided.

Note that 11 in FIG. 3 is a delay circuit provided as necessary for signal timing. FIG. 4 is a waveform diagram when the embodiment of the present invention shown in FIGS. 1, 2, and 3 is operated. For example, if the signal under test has a waveform as shown in A,
Time t ₀ when the synchronization of the synchronous circuit 3 is shifted from voltage V ₀ to V ₁
If it is adjusted to , it becomes possible to generate a slope signal such as B in the slope signal generation circuit 4. Potentials E ₁ , E ₂ , E ₃ , E ₄ , which are selected every cycle by the variable voltage source circuit 5 in response to this slope signal
When one of the stationary signals such as E ₅ is applied to the comparator 6, the sampling pulse is generated near the point where the slope signal intersects this comparison voltage, that is, at times t ₁ , t ₂ , t ₃ , t ₄ ,
As shown in C at either t ₅ , the pulse P ₁ ,
It is possible to generate one of P ₂ , P ₃ , P ₄ , and P ₅ . This sampling pulse results in outputs corresponding to V ₁ , V ₂ , V ₃ , V ₄ , and V ₀ of the waveform shown in A. Now, for example, E ₂ is applied to the comparator 6 during a certain period of the first period, sampling pulse P ₂ is generated at time T ₂ to cause sampling, and during a certain period of the next second period, the comparator 6
A sampling pulse P 3 is generated at time T ₃ by adding E ₃ to the sampling pulse P ₃ to perform sampling, and the sampling output of each period is AD-converted by an analog-to-digital converter 9 in each period. And the variable voltage source circuit 5
When E ₂ occurs, register U ₆ is operated, and when E ₃ occurs, register U ₇ is operated, and the sampled values at E ₂ and E ₃ are read into separate registers U ₆ and U ₇ . Next, the outputs of the respective registers are subtracted by an adder/subtractor 8 to obtain a digital output corresponding to the difference between V ₃ -V ₂ . In the output of this difference, the signal component, that is, the DC component, included equally in V ₂ and V ₃ can be used to remove the drift component of the measuring device or the DC voltage for position adjustment seen in a sampling oscilloscope or the like. The comparison signals E ₁ , E ₂ , E ₃ , E ₄ , and E ₅ can be set continuously, and continuing operation while changing the speed to a constant speed corresponds to the function of a conventional sampling device. .

FIG. 5 shows another specific embodiment of the present invention.
The digital register in the figure is replaced with an analog circuit, and its output can also be provided as an analog signal.

The output from the sampling gate is a transistor
This output is provided through a buffer amplifier by Q ₉ , which has the same configuration as transistors Q ₁₀ , Q ₁₁ , and Q ₁₂ .
It is also supplied to the hold circuit formed by Q ₁₃ , Q ₁₄ , and Q ₁₅ . By switching the hold gate operation of the transistor _Q10 and the transistor _Q13 by the variable voltage source circuit 5, the sampling output accumulated in the capacitance _C7 and the capacitance _C8 is shown in FIG. 4A.
It is possible to correspond to any two of V ₀ , V ₁ , V ₂ , V ₃ , and V ₄ shown in FIG. These outputs are applied to a differential amplifier circuit U ₉ from buffer amplification transistors Q ₁₁ and Q ₁₄ , respectively, so that a difference signal output C can be obtained.

According to this configuration, if the capacitance is _C7 ,
If the output corresponding to V ₀ is accumulated and the capacitance C ₈ is supplied with a sampling output that scans the entire signal under test, the output C will be based on the output corresponding to the V ₀ level in Figure 4. _V1 ,
It can be made compatible with V ₂ , V ₃ , and V ₄ .

It is also possible to provide two or more registers or hold circuits in FIGS. 2 and 5 to perform computations with complex combinations.

As described above, according to the present invention, it is possible to improve the drawbacks of conventional sampling devices in which DC components, drift components of measurement devices, DC voltage components for position adjustment, etc. appear in the output, and to A signal extraction calculation device that can measure the voltage between any two points without having to install multiple sampling circuits, and also avoids the negative effects of new errors that occur when multiple sampling circuits are installed. It has the effect of being able to provide the following.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a signal extraction calculation device according to an embodiment of the present invention, FIGS. 2 and 3 are wiring diagrams showing the detailed configuration of the main parts, and FIG. 4 is a waveform diagram thereof.
FIG. 5 is a wiring diagram of main parts showing another specific configuration example. 3... Synchronous circuit, 4... Slope signal generation circuit, 5... Variable voltage source circuit, 6... Comparator, 7... Sampling pulse generation circuit, 8... Sampling gate and hold circuit, 10... Arithmetic circuit.

Claims (1)

[Claims] 1. A synchronization circuit for synchronizing slope signals, a slope signal generation circuit driven by the synchronization circuit, and a variable voltage source controlled by a periodic signal of the slope signal from the slope signal generation circuit. a comparator having two inputs: a slope signal output of the slope signal generation circuit and a voltage output of the variable voltage source circuit; a pulse generation circuit activated by the output of the comparator; A sampling gate circuit consisting of a gate that is driven by an output pulse and samples the signal under test and a buffer amplifier that receives the output, a hold circuit that receives the output of this sampling gate circuit, and a digital signal that converts the output of this hold circuit. A circuit that converts into
A signal extraction calculation device comprising a circuit that receives this digital signal, classifies the digital signal according to a voltage switching timing signal from the variable voltage source circuit, performs an addition/subtraction operation between the classified digital signals, and outputs the result. 2. A synchronization circuit for synchronizing the slope signals, a slope signal generation circuit driven by the synchronization circuit, a variable voltage source circuit controlled by the periodic signal of the slope signal from the slope signal generation circuit, and the slope signal a comparator having two inputs: the slope signal output of the generation circuit and the voltage output of the variable voltage source circuit; a pulse generation circuit activated by the output of the comparator; and a pulse generation circuit driven by the output pulse of the pulse generation circuit. A sampling gate circuit consisting of a gate that samples a measurement signal and a buffer amplifier that receives the output thereof, and a sampling gate output signal that receives the output of the sampling gate circuit and receives the voltage switching timing signal from the variable voltage source circuit. 2 sets of hold circuits for holding by type, and 2 sets obtained from this hold circuit.
A signal extraction arithmetic device consisting of a differential arithmetic circuit with two outputs as differential inputs.