JPH02297938A - Wiring formation of semiconductor device - Google Patents

Abstract

PURPOSE:To suppress the hillock of upper and horizontal directions and improve the reliability of wiring by performing ion implantation on upper faces and at sidewalls of wiring with an oblique rotation ion implantation process with respect to patterned wiring. CONSTITUTION:A metal layer 4a acting as a wiring layer is formed by sputtering and a deposition process on the surface of a silicon board 2 at which a semiconductor element and the like are formed by diffusion of impurities and oxide film formation and the like. Photolithography and etching ate performed to the metal layer 4a and a wiring layer 4 is formed. In this way oblique ion implantation is performed. Further, the board 2 is mounted in an ion implantation device so that an angle theta made by the normal direction of the board 2 to the direction of ions 5 entering into the board 2 comes to 30 deg., besides, ion implantation is performed while rotating the board 2 within the in-plane of the surface of the board. Implanting ions consist of Ar and wiring in which ion implantation is performed at upper faces and sidewalls of its wiring layer is thus obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of forming metal wiring of a semiconductor integrated circuit device.

(Prior Art) Aluminum or an AQ-8i alloy made of aluminum containing a small amount of silicon is mainly used as a wiring material for semiconductor integrated circuit devices.

As such aluminum-based wiring becomes finely patterned, hillocks occur due to thermal cycles, leading to disconnection of the wiring.

Therefore, ion implantation is performed to prevent hillocks. In this ion implantation, after forming a metal layer that will become wiring, ions are implanted into the surface, and then patterning is performed to form wiring.

(Problem to be Solved by the Invention) In the conventional hillock suppression method, ions are implanted only on the surface of the wiring material, so hillocks in the upward direction of the wiring are suppressed, but hillocks are added by heat treatment after the wiring is formed. Stress causes lateral hillocks, which can short-circuit or break adjacent wires.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for suppressing not only upward hillocks but also lateral hillocks and preventing wire breaks and short circuits.

(Means for Solving the Problems) In the present invention, hillocks in the upward and lateral directions are suppressed by performing ion implantation not only on the top surface of the wiring but also on the side surface. Therefore, ion implantation is performed after patterning rather than before patterning. Further, the ion implantation step is performed while tilting the substrate with respect to the ion traveling direction and rotating the substrate within the substrate plane.

If the angle θ between the normal direction of the substrate and the ion traveling direction is the substrate inclination angle, this inclination angle O is set so that ions are implanted into the sidewalls of the wiring depending on the thickness of the wiring and the distance between adjacent wirings. However, the range is, for example, from several degrees to about 60 degrees.

(Function) After patterning and forming wiring, ions are implanted from an oblique direction, so that ions are implanted not only into the top surface of the wiring but also on the side surfaces. This suppresses not only upward hillocks but also lateral hillocks.

(Example) FIG. 1 represents one embodiment.

(A) A metal layer 4a, which will become a wiring, is formed by sputtering or vapor deposition on the surface of the substrate 2 on which semiconductor elements and other elements are formed by impurity diffusion or oxide film formation on a silicon substrate. The metal layer 4a is made of, for example, aluminum containing 1% silicon, and its film j11 has a thickness of approximately 90 C)0.

(B) Photolithography and etching are performed on this metal WJ4tx in the conventional manner to form wiring 4. For example, the line width of this wiring 4 is 1.5μIn, and the distance between adjacent wirings is also 1.5μIn.
It is μm.

(C) Perform oblique ion implantation. The substrate 2 is mounted on the ion implantation apparatus so that the angle O formed by the normal direction of the substrate 2 is 30 degrees with respect to the direction in which the ions 5 enter the substrate 2, and! Ion implantation is performed while rotating the +'+ plate 2 within the plane of the substrate. The implanted ions are, for example, Ar, and the main amount of the implanted ions is about 5×IO15/c. As a result, as shown in (D), a wiring 4 in which ions are implanted into the top surface and sidewalls is obtained.

Next, FIG. 2 shows a comparison of the test results of the failure rate when ion implantation is performed according to the present invention and when ion implantation is performed into a wiring layer before patterning as in the conventional method.

In Figure 2, 7.8.9 shows the case where oblique ion implantation was performed after patterning using the method of the present invention, and 17°18.19 shows the case where ion implantation was performed on the surface before patterning using the conventional method. . The implanted ions are Ar for 7,17, 8,1
8 is As, and 9 and 19 are BF2. The wires tested had a width of 1.5 μm, a distance between adjacent wires of 1.5 μm, a material of aluminum containing 1% silicon, and a film thickness of about 9,000. These wires were meandered and connected into a single wire, and tests were conducted to determine whether or not the wires would break. 5 x 10' on that wire during the test.
A current of "A/cm" was applied and the temperature was maintained at 150° C. The failure rate represents the rate at which the wiring was disconnected.

According to the results shown in Figure 2, the wiring formed by ion implantation on the top surface and side walls according to the present invention has a lower failure rate than the conventional wiring, indicating that it is effective in suppressing hillocks. .

In the above example, Ar is used as the ion to be implanted.

Although As and B are shown, the type of implanted ions is not limited to these, and may be P or other ions.

(Effects of the Invention) In the present invention, ions are implanted into the top surface and sidewalls of the wiring after patterning using the diagonal rotation ion implantation method, so both hillocks in the upward direction and hillocks in the lateral direction can be suppressed. reliability is improved.

[Brief explanation of the drawing]

FIG. 2 is a process sectional view showing one embodiment, and FIG. 2 is a diagram comparing the failure rate between wiring according to the method of the present invention and conventional wiring. 2... Board, 4... Wiring, 5...
...Ions to be implanted.

Claims (1)

[Claims] (1) A process of forming a metal layer on a substrate, a process of patterning the metal layer, and then a process of tilting the substrate with respect to the ion traveling direction and performing ion implantation while rotating the substrate within the substrate plane. A wiring formation method for a semiconductor device, including a wiring formation method for a semiconductor device.