JPH0448733A - Multilayer wiring and its manufacture, and film transistor matrix wherein it is used - Google Patents

Abstract

PURPOSE:To prevent the short trouble between a gate electrode and source and drain electrodes, and the breaking trouble, the increased of wiring resistance, etc., of the upper layer bus line caused by the step in the lower layer bus line and reduce cost by making the width of the wiring of a first metallic film, whereon a second metallic film is not formed, smaller than the value being gotten by subtracting the width of the wiring of the second metallic film from the width of the wiring of the first metallic film, whereon a second metallic film is formed. CONSTITUTION:With the resist pattern on an Al film as a mask, only the Al film is etched, using the solution (the mixture of phosphoric acid, nitric acid, acetic acid, and water, liquid temperature 40 deg.C) in the line of phosphoric acid. Next, with the resist pattern and the Al film after etching as masks, only the Cr film is etched in the solution of diammonium cerium nitrate. Then, the sides of the Al film are etched in phosphoric acid solution until the Al film on the Cr film is completely removed in the b-b' section. By removing the resist pattern, multilayer wiring is formed. Since it can be made by the photoprocess of one time, the manufacturing cost can be cut down.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is applicable to thin film transistors incorporated into, for example, liquid crystal display devices.
The present invention relates to the structure and manufacturing method of a multilayer film wiring body of laminated metal films used for wiring and electrodes of matrix circuit boards (hereinafter abbreviated as TFT).

[Conventional technology]

In the case of forming a multilayer film wiring body, in the conventional technique, each single film is etched using a photomask.

Therefore, a method for forming a multilayer film wiring body by etching a multilayer film using one photomask is disclosed in Japanese Patent Application Laid-Open No.
95536 has been proposed.

Further, the multilayer film wiring body is made of amorphous silicon (A
It is also used in a TPT matrix having an active layer such as morphous 5 ilicon (hereinafter abbreviated as a-5i).

The general structure of an a-5i TFT matrix (inverted staggered a-5i TFT) is shown in FIG.

3(a) is a plan view, and FIG. 2(b) is a sectional view taken along line AA' in FIG. 1(a).

11 is a glass substrate, 12 is a gate electrode made of chromium (Cr), etc., and 13 is silicon nitride (Silicon N).
1tride (hereinafter abbreviated as SiN film), 14 is a semiconductor active layer made of a-5i, 15 is a semiconductor layer made of n-type a-5i doped with phosphorus, 16
17 is a source electrode made of aluminum 16a and chromium 16b (upper layer Al film and lower layer Cr film, hereinafter referred to as A1/Cr film), etc.; 17 is aluminum 16a and chromium 16b (
18 is an oxide film of indium and tin (Indium Tin Oxide).
, hereinafter abbreviated as ITO film), etc., 22 is C
A gate bus line 27 is made of an R film or the like, and a drain bus line 27 is made of a multilayer wiring body such as an Al/Cr film.

In the prior art, in order to reduce the wiring resistance of the gate bus line 22, an A1 film, which is a resistive metal, is often superimposed on a Cr film, which is a high melting point metal.

However, since the A1 film is not superimposed on the gate bus line 22 and the gate electrode 12Cr film formed at the same time, the gate bus line and the gate electrode are formed in two photo steps.

This is shown in FIG.

FIG. 6(a) is a plan view showing the above configuration, and FIG. 6(b) is a plan view showing the above configuration.
) is a BB' sectional view of (a).

On the Cr film 2, which is a high melting point metal, A, which is a low resistance metal, is
1 film 3 is formed.

Further, in the case of forming the gate bus line 22 and the gate electrode 12 in the two photo steps described above, in order to eliminate disconnection of the drain bus line 27 and increase in wiring resistance due to the step of the gate bus line 22, SiN
A portion of the gate bus line 22 where the drain bus line 27 intersects through the film 13 or the SiN film 13 and the A-3I film 14 (including the n-type ASI 15) may be made of a Cr single film to reduce the step difference. .

This is shown in FIG.

Figure 7(a) is a plan view, and Figure 7(b) is c-c of (a).
'Cross-sectional view, FIG. In FIG. 7, 2 is a Cr film, which is a high melting point metal;
12 represents an Al film which is a low resistance metal, 12 represents a gate electrode, and 22 represents a gate bus line.

[Problem to be solved by the invention]

Among the above conventional techniques, a multilayer film (Al/
Regarding the method of forming wiring (Cr film), when used as a bus line of a TPT matrix, there is no problem when using it as an upper layer bus line (drain bus line 27 in FIG. 5), but when using it as a lower layer bus line (see FIG. 5) When used as the gate bus line 22), the Al film is also superimposed on the gate electrode 12 formed at the same time as the gate bus line 22, so the gate electrode 12, source electrode 16, and drain electrode are formed by growing the Al film. 17
Failures such as short circuits between the two may occur, causing defects in the TPT element.

Furthermore, the gate bus line 2 of the drain bus line 27
There are problems in that disconnection failures may occur due to the step difference in the drain bus line 27, and the wiring resistance of the drain bus line 27 may increase.

Among the above-mentioned conventional techniques, the method of forming gate bus lines and gate electrodes in two photo steps has the problem that the photo steps are performed twice, increasing the number of steps and increasing manufacturing costs.

An object of the present invention is to form a multilayer wiring body used for bus lines and part of electrodes of a TPT matrix in a single photo process, thereby preventing short-circuit defects between gate electrodes and source/drain electrodes, and preventing lower layer bus lines. The purpose is to prevent disconnection failures and increases in wiring resistance of upper layer bus lines caused by line steps, and to reduce costs compared to conventional methods.

[Means to solve the problem]

In order to achieve the above object, the pattern of the multilayer film wiring body is such that the wiring width of the first metal film on which the second metal film is not formed is the same as that of the first metal film. 2nd layer on top of the membrane
The shape is smaller than the value obtained by subtracting the wiring width of the second metal film to be formed from the wiring width of the first metal film forming the metal film (smaller than the normal wiring width). .

Specifically, it is as follows.

FIG. 8 shows the pattern of the multilayer film wiring body.

Wl indicates the wiring width of the first metal film in the portion where the second metal film is not laminated, and W2 indicates the wiring width of the first metal film in the portion where the second metal film is laminated.

W3 indicates the wiring width of the second metal film. The dotted line indicates the area where the second metal film remains.

In the figure, it is assumed that W1≦W2−W3.

In addition, in order to suppress an increase in wiring resistance due to a reduction in wiring width, the portion where the wiring width is reduced is formed into a shape in which two or more wirings are branched in parallel.

Furthermore, a resist pattern is formed in accordance with the shape of the multilayer wiring body, and using this resist pattern as a mask, the second metal film is etched using the first etching solution. After etching the first metal film using the above-mentioned etching solution, the second metal film is side-etched using the first etching solution, and the second metal film is placed on top of the first metal film. A part to be laminated and a part to remove the second metal film from above the first metal film are formed, and finally, the resist pattern is removed to form the multilayer wiring body. .

[Effect]

For example, in the case of an Al/Cr film in which the first metal film is a Cr film and the second metal film is an Al film, the Al film will be side etched.

The relationship between the temperature of the phosphoric acid solution (mixture of phosphoric acid, nitric acid, acetic acid, and water) used as an etching solution for the Al film, which is the second metal film, and the side etching rate of the Al film is shown in the ninth section. As shown in the figure.

The side etching rate of the Al film changes depending on the temperature of the etching solution, but side etching can be performed with good reproducibility as long as the solution temperature is kept constant.

By proceeding this side etching from above the Cr film in the area where the wiring width is smaller than usual until the AIJl is removed, an Al film is present in the area with the normal wiring width, and the wiring width is smaller than usual. A multilayer wiring body made of an Al/Cr film without an Al film is formed in the portion where the area is reduced.

〔Example〕

Next, embodiments of the present invention will be described using FIGS. 1 to 4.

A first embodiment of the present invention will be described with reference to FIG.

FIG. 1 shows a first embodiment of the present invention, a multilayer film wiring body in which the upper layer film is side-etched while changing the wiring width, and the manufacturing process of the multilayer film wiring body.

In the figure, 1 is a substrate such as a silicon wafer or a glass plate, 32 is a lower layer Cr film, 33 is an upper layer Al film, and 4 is a resist.

Figures (a) and (e) are plan views seen from above;
a) to (e) are cross-sectional views a-a' in the plan view, and bb-b
'A cross-sectional view is shown.

A resist pattern as shown in FIG. 3(a) is formed on the Al/Cr film. After that, as shown in the same figure (b),
Using the resist pattern as a mask, remove only the A1 film with a phosphoric acid solution (phosphoric acid, nitric acid).

Etching is performed using a mixture of acetic acid and water (solution temperature: 40°C).

Next, using the resist pattern and the etched A1 film as a mask, only the Cr film is etched with a solution of ceric ammonium nitrate, as shown in FIG. Furthermore, as shown in FIG.
'This process is carried out until all of the A1 film is removed from above the Cr film in the cross section.

Finally, as shown in FIG. 3(e), the resist pattern is removed to form a multilayer wiring body.

Next, a second embodiment of the present invention will be described using FIG. 2.

FIG. 2 shows a multilayer wiring body according to a second embodiment of the present invention.
This is an example of two or more parallel branches (the figure shows an example of three parallel branches).

In the figure, 1 indicates a substrate such as a silicon wafer or a glass plate, 42 indicates a lower layer Cr film, and 43 indicates an upper layer Al film.

According to this embodiment, since the wiring portion whose width is smaller than the normal wiring width is branched into two or more lines in parallel, it is possible to eliminate an increase in resistance due to the wiring portion.

Next, a third embodiment of the present invention will be described using FIG.

FIG. 3(a) shows the multilayer film wiring body of the present invention in a-5iT
A plan view of an example of a PT matrix bus line, and FIG.

In the figure, 51 is a glass substrate, 52 is a gate electrode made of a Cr film, etc., 53 is a gate insulating layer made of a SiN film, 54 is a semiconductor active layer made of a-5i, and 55 is an n-type a-5i doped with phosphorus. Semiconductor layer made of 5i, 56 is Al
57 is a drain electrode made of Al/Cr film, 58 is a pixel electrode made of ITO film,
59 is a gate bus line made of an Al/Cr film, and 67 is a drain bus line made of an AI/(, r film).

The manufacturing process is described below.

First, carbon is deposited on the glass substrate 51 by sputtering or the like.
The r film 2 and the Al film 3 are sequentially formed, and the wiring pattern and the Al film 3 are formed sequentially.
A photoetching process using side etching of the film is performed to form the gate electrode 52 and the gate bus line 22.

Next, using gases such as silane, ammonia, hydrogen, and phosphine, plasma CVD (Chemical Vacuum
The gate insulating layer SiN film 53. Semiconductor layer a-5i film 54. An n-type a-5i semiconductor layer 54 doped with phosphorus is successively formed, and a normal photo process and dry etching using CCQF3 gas or the like are performed to form a semiconductor active layer 54 made of an a-5i film.
A semiconductor layer 55 made of an n-type A-5i film is formed in an island shape.

Next, a normal photo process and dry etching using CF4 gas or the like are performed to form a gate insulating layer 53 made of a SiN film on the terminal portion (not shown) of the gate bus line 22.
remove.

Next, an IT◯ film is formed by a sputtering method or the like, and a normal photo process and etching using a mixed solution of hydrochloric acid, nitric acid, and water are performed to form the pixel electrode 58.

Next, a Cr film 2 and an A1 film 3 are sequentially formed by sputtering or the like, and a normal photoetching process is performed to form the source electrode 56. Drain electrode 57. Drain bath line 2
form 7.

Next, source electrode 56. Using the drain electrode 57 as a mask, the semiconductor layer 55 made of an n-type a-5i film on the TPT channel portion is removed by dry etching using CCQF, gas, or the like.

After that, the gate bus line 2 is covered with a passivation film.
2. Exposing the terminal part of the drain bus line 27 a
-SiTFT matrix is completed.

According to this embodiment, the intersecting portion of the gate bus line 22 becomes a Cr film layer via the drain bus line 27 and the gate insulating layer 53 made of a SiN film, and the drain bus line 27 becomes a Cr film layer. This has the effect of preventing wire breakage and increase in resistance due to differences in level.

Next, a fourth embodiment of the present invention will be described using FIG. 4.

FIG. 4 is a plan view of an example in which the multilayer wiring body of the present invention is used for bus lines and electrodes of an a-5iTPT matrix, and FIG. 4(b) is a sectional view taken along line dd' in FIG. 4(a).

In the figure, 61 is a glass substrate, 62 is a gate electrode made of a Cr film, 63 is a SiN film, 64 is an a-5i film, 6
5 is an n-type a-5i, 66 is a source electrode made of an Al/Cr film, 67 is a drain electrode made of an Al/Cr film, 68
72 shows a pixel electrode made of an ITO film, 72 a gate bus line made of an Al/Cr film, and 77 a drain bus line made of an Al/Cr film.

The manufacturing process is the same as described in Example 3.

According to this embodiment, gate electrodes 62 are provided on each branched gate bus line 72, and one T
Even if there is a defect in the PT element, there is an effect that it can be relieved by using another element as long as there is no defect in all the elements.

〔Effect of the invention〕

According to the present invention, conventionally formed by two photo steps,
In a multilayer wiring body consisting of a first metal film (lower layer) and a second metal film (upper layer), the second metal film is
Since a multilayer film wiring body that exists on a certain part of the metal film and does not exist on a certain part can be formed in one photo process, there is an effect that the manufacturing cost can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a multilayer film wiring body in which the wiring width of the first embodiment is changed and the upper layer film is side-etched, and its a
-a' cross section and b-b' cross section, Fig. 2 is a plan view of a multilayer film wiring body in which a part of the wiring of the second embodiment is branched into two or more parallel lines, and Fig. 3 is a multilayer film wiring A plan view and a cc' cross-sectional view of the a-5i TFT matrix of the third example using the body,
Fig. 4 is a plan view of a fourth embodiment of an a-5i TFT matrix using a multilayer film interconnection body, and a cross-sectional view taken along line dd'. Fig. 5 is a plan view of a conventional a-3i TFT matrix, and a cross-sectional view taken along line A-A'. 6 is a plan view and a BB' cross-sectional view of a gate bus line and gate electrode of a conventional multilayer wiring body, and FIG. 7 is a plan view of a gate bus line and gate electrode of a conventional multilayer wiring body. , cc' cross section, D-D' cross section, FIG. 8 is a diagram of the pattern of the multilayer film interconnection body of the present invention, and FIG. 9 is the side etching rate of the aluminum film used in these embodiment methods. 3 is a graph showing the relationship between etching liquid temperature and etching liquid temperature. ■...Substrates such as silicon wafers and glass plates, 2...
Lower layer Cr film, 3... Upper layer Al film, 4... Resist,
11...Glass substrate, 12...Gate electrode, 13.
...Gate insulating layer. 14... Semiconductor active layer (a-5i), 15... Semiconductor active layer (n-type a-5i), 16... Source electrode,
17... Drain electrode, 18... Pixel electrode, 22...
・Gate bus line. 1st (1) n (d) 1st closed (e) 4th country (α) 2nd country (σ) 27F Shii > 7X Slino (b) 1st closed (α) Muscle 1st tomoe Wl <: W2-W3

Claims (1)

[Claims] 1. A first metal film and a second metal film partially formed on the first metal film and made of a metal different from the first metal film. , in a multilayer wiring body formed by stacking layers, the wiring width of the first metal film on which the second metal film is not formed is the wiring width of the first metal film on which the second metal film is formed. A multilayer film wiring body characterized in that the wiring width of the metal film is smaller than the value obtained by subtracting the wiring width of the second metal film. 2. The multilayer wiring body according to claim 1, characterized in that the portion of the wiring made of the first metal film on which the second metal film is not formed is branched into two or more in parallel. . 3. A multilayer metal film formed by sequentially forming a first metal film and a second metal film made of a different metal from the first metal film is etched using a single photomask. A method for manufacturing a multilayer film interconnection body formed by forming a multilayer film wiring body comprising: forming a resist pattern having a desired pattern shape on the second metal film, and selecting only the second metal film using the resist pattern as a mask. a step of etching the second metal film using a first etching solution that etches the second metal film selectively; and selecting only the first metal film using the resist pattern and the etched second metal film as a mask; etching the first metal film using a second etching solution that etches the second metal film side-etching the second metal film using the first etching solution; A method for manufacturing a multilayer film interconnection body, comprising the step of forming a portion where the film is not present on the first metal film. 4. A thin film transistor matrix formed by connecting a gate electrode to a first bus line, a drain electrode to a second bus line, and a source electrode to a pixel electrode of a thin film transistor, the multilayer film interconnection body according to claim 1 or 2. A thin film transistor matrix characterized in that it is used as at least one bus line or at least a part of any of the above electrodes.