JPH0229632A - Active matrix type liquid crystal display device - Google Patents
Active matrix type liquid crystal display deviceInfo
- Publication number
- JPH0229632A JPH0229632A JP63180788A JP18078888A JPH0229632A JP H0229632 A JPH0229632 A JP H0229632A JP 63180788 A JP63180788 A JP 63180788A JP 18078888 A JP18078888 A JP 18078888A JP H0229632 A JPH0229632 A JP H0229632A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- film
- transparent conductive
- bus line
- scan bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011159 matrix material Substances 0.000 title claims description 13
- 239000004973 liquid crystal related substance Substances 0.000 title claims description 12
- 239000010408 film Substances 0.000 claims abstract description 60
- 239000004020 conductor Substances 0.000 claims abstract description 15
- 239000010409 thin film Substances 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 14
- 238000000034 method Methods 0.000 abstract description 4
- 239000000463 material Substances 0.000 abstract description 3
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000009832 plasma treatment Methods 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 239000002356 single layer Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔概 要〕
アクティブマトリクス型液晶表示装置に関し、要求特性
を満足し且つ製造容易なアクティブマトリクス型液晶表
示装置を提供することを目的とし、
透明絶縁性基板上にマトリクス状に配列された透明導電
材料からなる複数個の画素電極と、該画素電極に対応づ
けて配設された薄膜トランジスタと、前記マトリクスの
行または列方向に平行に配設された複数個のスキャンバ
スラインを具備する液晶表示パネルにおいて、前記薄膜
トランジスタのゲート電極および該ゲート電極が導出さ
れるスキャンバスラインが、前記画素電極と同一の透明
導電材料を不透明化した膜から形成されてなる構成とす
る。[Detailed Description of the Invention] [Summary] The purpose of this invention is to provide an active matrix liquid crystal display device that satisfies required characteristics and is easy to manufacture. a plurality of pixel electrodes made of a transparent conductive material arranged in a row, a thin film transistor arranged in correspondence with the pixel electrode, and a plurality of scan canvas lines arranged in parallel in the row or column direction of the matrix. In the liquid crystal display panel, the gate electrode of the thin film transistor and the scan canvas line from which the gate electrode is derived are formed from a film made of the same transparent conductive material as the pixel electrode and made opaque.
本発明はアクティブマトリクス型液晶表示装置に関する
。The present invention relates to an active matrix liquid crystal display device.
アクティブマトリクス型液晶表示装置は、薄型で高画質
フルカラー化が可能であることから、各方面で開発が進
められ、はぼ実用化段階まで来ている。問題点としては
、製造工程が複雑であることによる歩留の低下があげら
れ、この問題を解消するため製造工程を簡単化する方向
で検討が進められている。Active matrix liquid crystal display devices are thin and capable of producing high-quality, full-color images, so their development is progressing in various fields and has almost reached the stage of practical use. The problem is that the manufacturing process is complicated, resulting in a decrease in yield, and studies are underway to simplify the manufacturing process in order to solve this problem.
従来のアクティブマトリクス型液晶表示装置においては
、第3図の1画素分解図に示す如く、ゲート電極Gを、
画素電極Eと同一材料である透明導電材料からなる透明
導電膜2と金属膜3との2層構造に形成していた。かか
る積層構造を形成するには、まず透明導電膜2と金属膜
3とを積層し、これをパターニングしてゲート電極G部
、スキャンバスライン(図示せず)部、および画素電極
E部を除く他の部分を除去した後、画素電極E部の金属
膜を除去する。In a conventional active matrix liquid crystal display device, as shown in the exploded view of one pixel in FIG.
It was formed to have a two-layer structure of a transparent conductive film 2 made of a transparent conductive material, which is the same material as the pixel electrode E, and a metal film 3. To form such a laminated structure, first, the transparent conductive film 2 and the metal film 3 are laminated, and this is patterned to exclude the gate electrode G portion, the scan canvas line (not shown) portion, and the pixel electrode E portion. After removing the other portions, the metal film on the pixel electrode E portion is removed.
このように従来のアクティブマトリクス型液晶表示装置
ではゲート電極Gが2層構造であるために、ゲート電極
G及びスキャンバスラインとその近傍との段差が大きく
なる。また積層構造とするための工程が必要で、製造工
程も複雑化するという問題があった。As described above, in the conventional active matrix liquid crystal display device, since the gate electrode G has a two-layer structure, the difference in level between the gate electrode G and the scan canvas line and the vicinity thereof becomes large. Further, there is a problem in that a process for creating a laminated structure is required, which complicates the manufacturing process.
そこでゲート電極Gおよびスキャンバスラインを透明導
電膜1層のみで構成することも考えられる。この構成と
すれば製造工程は簡単化される反面、薄膜トランジスタ
(T P T)のチャネル部が光を透過するため、TP
Tの光リーク電流が増大する。Therefore, it is also conceivable to configure the gate electrode G and the scan canvas line with only one layer of transparent conductive film. This configuration simplifies the manufacturing process, but since the channel part of the thin film transistor (TPT) transmits light, the TP
The photoleakage current of T increases.
上述した如〈従来のアクティブマトリクス型液晶表示装
置においては、種々の要求特性を満足させようとすると
製造工程が複雑化し、製造工程を簡単化しようとすると
、特性上に問題を生じる。As mentioned above, in conventional active matrix liquid crystal display devices, attempts to satisfy various required characteristics complicate the manufacturing process, and attempts to simplify the manufacturing process cause problems in characteristics.
本発明は要求特性を満足し且つ製造容易なアクティブマ
トリクス型液晶表示装置を提供することを目的とする。An object of the present invention is to provide an active matrix liquid crystal display device that satisfies required characteristics and is easy to manufacture.
第1図に本発明の構成を示す。 FIG. 1 shows the configuration of the present invention.
同図に示す如く本発明においては、ゲート電極Gおよび
ゲート電極Gが導出されるスキャンバスライン(第2図
参照) SBを、画素電極Eと同一材料の透明導電材料
を不透明化した膜からなる構成とする。As shown in the figure, in the present invention, the gate electrode G and the scan canvas line SB from which the gate electrode G is derived (see Figure 2) are made of a film made of an opaque transparent conductive material, which is the same material as the pixel electrode E. composition.
即ち、画素電極Eとゲート電極Gおよびスキャンバスラ
インSBは、ITOのような透明導電材料からなる膜に
より構成され、画素電極Eは透明導電膜2をそのまま使
用し、ゲート電極Gおよびスキャンバスラインは上記透
明導電膜を不透明化した膜2゛を使用する。That is, the pixel electrode E, the gate electrode G, and the scan canvas line SB are composed of a film made of a transparent conductive material such as ITO, the pixel electrode E uses the transparent conductive film 2 as is, and the gate electrode G and the scan canvas line In this example, a film 2' made of the transparent conductive film described above is made opaque.
ITOのような透明導電材料からなる膜は、水素プラズ
マ処理を施すことにより容易にメタリック化する。この
メタリック化された膜は黒化して非透光性となるととも
に、抵抗値も上記プラズマ処理を施す前と比較して約1
/2に低下する。A film made of a transparent conductive material such as ITO is easily made metallic by hydrogen plasma treatment. This metallic film turns black and becomes non-transparent, and its resistance value is also about 1 compared to before the plasma treatment.
/2.
従って、この膜のみでゲート電極Gを構成しても、チャ
ネル部に光が透過することがなく、またスキャンバスラ
インの抵抗も1層構成で実用上充分に低い値とすること
ができ、更に、ゲート電極Gおよびスキャンバスライン
の段差が小さくなること及び成膜工程が1工程減少する
ので、製造工程が容易となる。Therefore, even if the gate electrode G is composed of only this film, no light will pass through the channel part, and the resistance of the scan canvas line can be made to a sufficiently low value for practical use with a single layer structure. , the step difference between the gate electrode G and the scan canvas line becomes smaller, and the number of film forming steps is reduced by one, so that the manufacturing process becomes easier.
以下本発明の一実施例を第2図(a)〜(1))により
説明する。なお第2図(11〜(piは、それぞれ(a
)〜(h)のn−n矢視部の要部断面図である。An embodiment of the present invention will be described below with reference to FIGS. 2(a) to (1)). In addition, Fig. 2 (11~(pi is each (a)
) to (h) are main part sectional views taken along the line nn arrow.
(第2図(a)、 (11参照〕
透明絶縁性基板2例えばガラス基板l上に、透明導電材
料からなる膜5例えばITO膜2を、約30〜1100
nの厚さに成膜する。次いでこれの上にイメー・シリバ
ーサルフォトレジスト(シブレー社製)を塗布し、これ
をバターニングして画素電極形成領域及びゲート電極、
スキャンバスライン形成領域を被覆するレジスト膜11
.11′を形成する。(See FIG. 2(a), (11)) A film 5 made of a transparent conductive material, for example, an ITO film 2, is deposited on a transparent insulating substrate 2, for example, a glass substrate l, with a thickness of approximately 30 to 1,100 mm.
A film is formed to a thickness of n. Next, an image siliversal photoresist (manufactured by Sibley) is applied on top of this, and this is patterned to form the pixel electrode formation area, the gate electrode,
Resist film 11 covering the scan canvas line forming area
.. 11' is formed.
〔第2図(b)、 (J)参照〕
次いで上記レジスト膜11.11°のうち、図に右下が
りの斜線を施した部分、即ち画素電極形成領域を被覆し
たレジスト膜11に露光を施したのち、約120℃の温
度で凡そ30分間ベーキングを行う。[See FIGS. 2(b) and (J)] Next, the portion of the resist film 11.11° indicated by diagonal lines downward to the right in the figure, that is, the resist film 11 covering the pixel electrode formation region, is exposed to light. After that, baking is performed at a temperature of about 120° C. for about 30 minutes.
イメージリバーサルフォトレジスト膜に対して露光後に
施す上記ベーキングは、リバーサルベークと呼ばれる。The above baking performed on the image reversal photoresist film after exposure is called reversal baking.
イメージリバーサルフォトレジストは本来ポジ型である
が、リバーサルベークを施すと、被露光部はネガ型の如
く現像液に対して非溶解性となる。従って本工程によっ
てレジスト膜11は現像液に非溶解性となる。An image reversal photoresist is originally a positive type, but when subjected to reversal baking, the exposed area becomes insoluble in a developer like a negative type. Therefore, this step makes the resist film 11 insoluble in the developer.
このあと、上記レジスト膜11.11”全面に露光を施
して、ゲート電極およびスキャンバスライン形成領域を
被覆したレジスト膜11゛ を、現像液に可溶性とする
。Thereafter, the entire surface of the resist film 11.11'' is exposed to light to make the resist film 11'' covering the gate electrode and scan canvas line formation region soluble in a developer.
〔第2図(C)、 (k)参照〕
上記レジスト膜11.11°をマスクとして、ウェット
エツチング法によりITO膜2の露出部を除去して、画
素電極部のITO膜2とゲート電極部およびスキャンバ
スライン部のITO膜2”を形成した後、レジスト膜1
1.11’の現像を行う。これにより、画素電極形成領
域上のレジスト膜11のみが残留し、レジスト膜11゛
は除去される。[See FIGS. 2(C) and (k)] Using the resist film 11.11° as a mask, the exposed portion of the ITO film 2 is removed by wet etching to remove the ITO film 2 of the pixel electrode portion and the gate electrode portion. After forming the ITO film 2'' on the scan canvas line portion, the resist film 1
1. Perform 11' development. As a result, only the resist film 11 on the pixel electrode formation region remains, and the resist film 11' is removed.
〔第2図(d)、 +11参照〕
次いでこのレジスト膜11をマスクとしてITO膜2に
対して、温度約120℃1反応圧力約3 Torr。[See Figure 2(d), +11] Next, using this resist film 11 as a mask, the ITO film 2 was applied at a temperature of about 120° C. and a reaction pressure of about 3 Torr.
高周波電力約30Wの条件下で水素プラズマ処理を施す
。これにより、透明導電材料のITOはメタリックとな
って、黒化するとともに、抵抗値は凡そ1/2に低下す
る。ここでゲート電極GとスキャンバスラインSRが形
成される。Hydrogen plasma treatment is performed under conditions of high frequency power of approximately 30W. As a result, the transparent conductive material ITO becomes metallic and blackened, and the resistance value decreases to approximately 1/2. Here, a gate electrode G and a scan canvas line SR are formed.
このあと、レジスト膜11を除去する。After this, the resist film 11 is removed.
〔第2図(e)、 (m)参照〕
次いで、ゲート絶縁膜として厚さ約100〜300nm
の5iNX膜4を、プラズマ化学気相成長(CVD)法
により成膜し、次に動作半導体層として厚さ約20=
1100nのa−3t(アモルファスシリコン)層5.
コンタクト層としてP (燐)をドープしたn″a−3
i層6を凡そ30nmの厚さに積層する。[See Figures 2(e) and (m)] Next, a gate insulating film with a thickness of about 100 to 300 nm is formed.
A 5iNX film 4 of
1100n a-3t (amorphous silicon) layer5.
n″a-3 doped with P (phosphorus) as a contact layer
The i-layer 6 is laminated to a thickness of approximately 30 nm.
(第2図(f)、 (n)参照〕
次いで上記n”a−3i層6 r a S 1層5
゜及びSiN、膜4をレジスト膜(図示せず)をマスク
としてエツチングを行い、素子形成部Tおよびデータバ
ス94208部に上記積層膜を形成した後、上記レジス
ト膜を除去する。(See FIGS. 2(f) and (n)) Next, the above n"a-3i layer 6 r a S 1 layer 5
Etching is performed on the SiN film 4 using a resist film (not shown) as a mask to form the laminated film in the element forming portion T and the data bus 94208 portion, and then the resist film is removed.
〔第2図((イ)、(O)参照〕
AI (アルミニウム)膜7のような金属膜を、凡そ
300〜11000nの厚さに成膜する。[See FIGS. 2 (A) and (O)] A metal film such as an AI (aluminum) film 7 is formed to a thickness of about 300 to 11000 nm.
〔第2図(h)、 (P)参照〕
上記Al膜7のパターニング行なって不要部を除去し、
ドレイン電極り、データバスラインDB。[See FIGS. 2(h) and (P)] The Al film 7 is patterned to remove unnecessary parts,
Drain electrode, data bus line DB.
及びソース電極Sを形成し、更に、n“a−3i層6の
一部を除去して、本実施例のアクティブマトリクス型液
晶表示装置が完成する。and source electrodes S are formed, and a part of the n"a-3i layer 6 is removed to complete the active matrix type liquid crystal display device of this embodiment.
上述の本実施例では、ゲート電極Gおよびスキャンバス
ラインSBともにITO膜を黒化処理した膜のみで構成
したので、段差は小さくなること及び膜を積層し且つエ
ツチングする工程が不要となることにより製造工程が簡
単となり、しかもパスラインの抵抗値も実用上充分に低
くなり、且つチャネル部に光が透過しないので、光リー
ク電流が生じることもない。In this embodiment described above, since both the gate electrode G and the scan canvas line SB are made of only the blackened ITO film, the step difference becomes small and the process of laminating and etching the films becomes unnecessary. The manufacturing process is simplified, the resistance value of the pass line is sufficiently low for practical use, and no light leakage current occurs because no light passes through the channel portion.
以上説明した如く本発明によれば、製造工程が簡単化さ
れ、ゲート電極の段差が小さく、且つ、スキャンバスラ
インの抵抗も1層構造で充分に低くすることが可能とな
る。As described above, according to the present invention, the manufacturing process is simplified, the step difference in the gate electrode is small, and the resistance of the scan canvas line can be made sufficiently low with a single layer structure.
第1図は本発明の構成説明図、
第2図(a)〜(P)は本発明一実施例説明図、第3図
は従来のTPT構成説明図である。
図において、1はガラス基板、2は透明導電材料膜、2
゛は不透明化した透明導電材料膜、3はCr等の金属膜
、4はゲート絶縁膜、5は動作半導体層、6はコンタク
ト層、7はA1等の金属膜、Gはゲート電極、Eは画素
電極、SBはスキャンバ本
発
明
構
成
説
明
図
第
図
従来のTPT構成説明図
第
図
本発明−実施例説明図
m 2 図 (その2)FIG. 1 is an explanatory diagram of the configuration of the present invention, FIGS. 2(a) to (P) are explanatory diagrams of one embodiment of the present invention, and FIG. 3 is an explanatory diagram of the conventional TPT configuration. In the figure, 1 is a glass substrate, 2 is a transparent conductive material film, 2
゛ is an opaque transparent conductive material film, 3 is a metal film such as Cr, 4 is a gate insulating film, 5 is an active semiconductor layer, 6 is a contact layer, 7 is a metal film such as A1, G is a gate electrode, and E is a metal film such as A1. The pixel electrode, SB, is a scan bar.Fig.Explanatory diagram of the configuration of the conventional TPT.Fig.Explanatory diagram of the present invention-embodiment.m2 (Part 2)
Claims (1)
明導電材料からなる複数個の画素電極(E)と、該画素
電極に対応づけて配設された薄膜トランジスタと、前記
マトリクスの行または列方向に平行に配設された複数個
のスキャンバスライン(SB)を具備する液晶表示パネ
ルにおいて、前記薄膜トランジスタのゲート電極(G)
および該ゲート電極が導出されるスキャンバスライン(
SB)が、前記画素電極(E)と同一の透明導電材料を
不透明化した膜から形成されてなることを特徴とするア
クティブマトリクス型液晶表示装置。A plurality of pixel electrodes (E) made of a transparent conductive material arranged in a matrix on a transparent insulating substrate (1), thin film transistors arranged in correspondence with the pixel electrodes, and rows or columns of the matrix. In the liquid crystal display panel including a plurality of scan canvas lines (SB) arranged parallel to the direction, the gate electrode (G) of the thin film transistor
and a scan canvas line from which the gate electrode is derived (
An active matrix type liquid crystal display device, characterized in that SB) is formed from a film made of the same transparent conductive material as the pixel electrode (E) and made opaque.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63180788A JPH0229632A (en) | 1988-07-19 | 1988-07-19 | Active matrix type liquid crystal display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP63180788A JPH0229632A (en) | 1988-07-19 | 1988-07-19 | Active matrix type liquid crystal display device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0229632A true JPH0229632A (en) | 1990-01-31 |
Family
ID=16089336
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP63180788A Pending JPH0229632A (en) | 1988-07-19 | 1988-07-19 | Active matrix type liquid crystal display device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0229632A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61111976A (en) * | 1984-11-07 | 1986-05-30 | 日本碍子株式会社 | Ceramic turbine rotor and manufacture |
-
1988
- 1988-07-19 JP JP63180788A patent/JPH0229632A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61111976A (en) * | 1984-11-07 | 1986-05-30 | 日本碍子株式会社 | Ceramic turbine rotor and manufacture |
JPH0229633B2 (en) * | 1984-11-07 | 1990-07-02 | Ngk Insulators Ltd |
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