JPH02294844A - Logical verification device - Google Patents

Abstract

PURPOSE:To perform speedy logical verification for a large-scale logic circuit model by providing a test pattern distributing means, plural simulation means, and an output data editing means. CONSTITUTION:The test pattern distributing means 1 reads test patterns (a) out of a test pattern file A one after another, transfers them to a data transfer means 2 are after another, and further sends a signal (c) for letting simulation means in a wait state among the simulation means 3 - 5 start interruption processing. Then the simulation means 3 - 5 perform simulation simultaneously by individual processors and then transfer output data (b) as simulation results to the data transfer means 6. Further, the output data editing means 7 is made to start the interruption processing and the output data (b) and a correct answer value pattern (e) are compared and displayed. Consequently, the large-scale logic circuit model can be simulated without requiring much verification time.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a logic verification device for logic circuits.

[Conventional technology]

Conventional logic verification devices sequentially simulate and verify a large number of test patterns. Therefore, as the number of test patterns increases, the time required for verification is arithmetically added up and tends to increase indefinitely. For example, "Survey on Logic Design CAD J, March 1985," pp. 31-44, edited by the Japan Electronics Industry Promotion Association. Since simulations were performed and verified sequentially, a large amount of verification time was wasted on large-scale logic circuit models.

[Means to solve the problem]

The logic verification device of the present invention includes a test pattern distribution means for inputting a plurality of test patterns read from a test pattern file and distributing the test patterns to a plurality of simulation means, and a test pattern distribution means for distributing one test pattern from the test pattern distribution means. a plurality of simulation means for inputting a pattern, performing a simulation defined in the test pattern, and transmitting the resulting output data to an output data editing means; and outputs obtained from the plurality of simulation means. The apparatus is configured to include output data editing means for comparing and displaying the data and the correct value pattern read from the correct value pattern file.

〔Example〕

FIG. 1 is a block diagram of one embodiment of the present invention.

The test pattern distribution means 1 reads a test pattern a for executing a simulation from a test pattern file A. Then, the test pattern distribution means 1 transfers the test pattern a to the data transfer means 2, and further sends a signal C to the simulation means 3 in a waiting state to start interrupt processing. When the simulation means 3 receives the signal C from the test pattern distribution means 1, it activates an interrupt process for receiving the test pattern a from the data transfer means 2, and executes the simulation for the test pattern a.

The test pattern distribution means 1 reads the next test pattern a from the test pattern file A after sending an interrupt processing signal C to the simulation means 3 to start interrupt processing. Then, the test pattern distribution means 1 transfers the test pattern a to the data transfer means 2, and further sends a signal C to the simulation means 4 in a waiting state to start interrupt processing. When the simulation means 4 receives the signal C from the test pattern distribution means 1, it activates an interrupt process for receiving the test pattern a from the data transfer means 2, and executes the simulation for the test pattern a.

In this way, the test pattern distributing means 1 reads the test patterns a one after another from the test pattern file A, further transfers the test patterns a one after another to the data transfer means 2, and further transfers the test patterns a one after another to the data transfer means 2. Of these, simulation means 3~ are in a waiting state.
Sends signal C to 5 to start interrupt processing. The simulation means 3 to 5 which receive the signal C from the test pattern distribution means 1 simultaneously execute simulations using separate processors.

After each simulation ends, the plurality of simulation means 3 to 5 transfer output data b, which is the simulation result, to the data transfer means 6, and further send a signal d to the output data editing means 7 to start interrupt processing.
Furthermore, it sends a signal C to the test pattern distribution stage 1 indicating that it is in a waiting state. When the output data editing means 7 receives the signal d from the simulation means 3 to 5, it activates an interrupt process to receive the output data b from the data transfer means 6, and further corrects the correct value pattern e corresponding to the output data b. Read from value pattern file B, compare output data b and correct value pattern e, and display.

FIG. 2 is an explanatory diagram showing the temporal operation flow of the test pattern distribution means 1, the plurality of simulation means 3 to 5, and the output data editing means 7. K represents the input and distribution of the test pattern, 31, S2, and S3 represent simulations for test pattern #1, test pattern #2, and test pattern #3, respectively, and O represents the correct value pattern of output data for the test pattern. It represents the comparison and display.

At a certain time t1, the test pattern distribution means inputs test pattern #1, test pattern #2, and test pattern #3 one after another, and further inputs test pattern #1, test pattern #2, and test pattern #3, respectively. Processing K is performed to be distributed to simulation means #1, simulation means #2, and simulation means #3. and,
At a certain time t2, simulation means #1 executes simulation S1 for test pattern #1, and at the same time simulation means #2 executes simulation S1 for test pattern #2.
At the same time, simulation means #3 executes simulation S3 for test pattern #3. Then, at a certain time t
3, the output data editing means selects the test pattern #1.
, test pattern #2, and test pattern #3. Then, at a certain time t3, the output data editing means compares and displays the respective output data for test pattern #1, test pattern #2, and test pattern #3 with the correct value button. In this way, the plurality of simulation means simultaneously execute simulations for different test patterns using separate processors.

〔Effect of the invention〕

As explained above, the present invention has the effect that logic verification can be performed at high speed on a large-scale logic circuit model by including a test pattern distribution means, a plurality of simulation means, and an output data editing means. be.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is an explanatory diagram showing the temporal flow of operation of the embodiment.

DESCRIPTION OF SYMBOLS 1... Test pattern distribution means, 2... Data transfer means, 3-5... Simulation means, 7... Output data editing means.

Claims (1)

[Scope of Claims] Test pattern distributing means for inputting a plurality of test patterns read from a test pattern file and distributing the test patterns to a plurality of simulation means; and a test pattern distribution means for distributing one test pattern from the test pattern distributing means. a plurality of simulation means for inputting data, performing a simulation defined in the test pattern, and transmitting the resulting output data to an output data editing means; and output data obtained from the plurality of simulation means. A logic verification device comprising output data editing means for comparing and displaying a correct value pattern read from a correct value pattern file.