JPS63288356A - Logical simulator - Google Patents

Abstract

PURPOSE:To process a delay and to execute a simulation of a high speed by assigning an element in a circuit for executing a simulation to each element evaluating part consisting of an arithmetic part and a delay part, and executing the simulation. CONSTITUTION:Before executing a simulation, under the control of a control part 3, each element evaluating part 1 having an arithmetic part 4 and a delay part 5 is connected by a wiring part 3 in accordance with connecting information of a circuit for executing the simulation. Simultaneously, to the element evaluating part 1, an element in said circuit is assigned, and a definition of a logical operation of the arithmetic part 4 and a definition of a delay time of the delay part 5 are executed by the control part 3. On the other hand, at the time of executing the simulation, each element evaluating part 1 is operated, while varying a signal inputted to each element evaluating part 1 by the control part 3, and a variation of an output of each element evaluating part 1 is observed. In this case, each element evaluating part 1 operates independently, therefore, the processing is executed at a high speed due to the parallel property contained latently in the circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a dedicated logic simulator that executes logic simulations at high speed.

Conventional technology Conventional logic simulators are
and Test of Computers (IEEE De
sign & Te5t of Computers)
, vol 1. n.

, 3. pp21-39. 'A 5urvey of Hardware Acce, published in August, 1984.
leratorsUsed in Computer
-Aided Design” etc.

Logic simulation methods include a compiled code method and an event-driven method. The compiled code algorithm generates an instruction code corresponding to the operation for each element in the circuit, and executes the simulation by executing the generated instruction code in the order of signal propagation. The event-driven algorithm uses a change in a signal value in a circuit as an event, and executes a simulation by sequentially performing calculations on the portion where the event occurs. Details of these methods are described in, for example, Chapter 4 of ``Design of rVLSI ■'' published by Iwanami Shoten Co., Ltd.

The logic simulator described in the aforementioned III Design and Test of Computers also has a configuration in which a compiled code type or event driven type algorithm is implemented in hardware.

Problems to be Solved by the Invention Conventional compiled code type logic simulators can only handle zero delay or unit delay and cannot directly handle arbitrary delays for each element. , it was necessary to insert a virtual element for delay and perform the simulation multiple times. Furthermore, it is not possible to directly handle circuits containing loops, and simulations must be performed using partial circuits obtained by cutting the loops.

In addition, event-driven logic simulators can directly handle delays and can run simulations even if a circuit includes a loop. In order to speed up the simulation in this event-driven logic simulator, there is a method of pipelining the processing related to the event-driven algorithm.

Speeding up by pipelining is achieved by performing the same number of stages of processing in parallel, but the number of pipeline stages in which parallel processing is performed is constant. In an actual circuit, signal changes flow in parallel, but in event-driven processing, signal changes correspond to events, and the events are processed sequentially. The time required for processing also increases. Another method is to divide the circuit and perform simulation using multiple event-driven logic simulators, but since events occur dynamically, if events occur in a concentrated manner in a certain partial circuit, The effect of parallel processing is reduced and the overall processing speed is reduced.

In view of this, it is an object of the present invention to provide a logic simulator that can handle delays and performs logic simulations at high speed by utilizing the parallelism potentially included in the circuit even when the circuit scale increases. purpose.

Means for Solving the Problems In order to solve the above-mentioned problems, the logic simulator according to the present invention includes a plurality of element evaluation units each including a calculation unit that executes a logical operation and a delay unit that executes a delay; This logic simulator includes a wiring section that connects the sections, and a control section that controls the element evaluation section and the wiring section.

Function: In the configuration of the logic simulator according to the present invention described above, the elements in the circuit are assigned to each element evaluation part, and each element evaluation part is connected by the wiring part according to the connection information of the circuit,
Run a logical simulation. In each element evaluation section, the arithmetic section executes a logical operation on the assigned element, and the delay section changes the state according to the delay of the element.

Since the element evaluation sections are connected by the wiring section according to the circuit connection information, changes in the state of each element evaluation section are propagated by the wiring section, and logical operations and delay processing are performed in the connected element evaluation section. In this way, the entire circuit is simulated by each element evaluation section performing an operation equivalent to the assigned element in the circuit. In this case, even if a loop or the like is included in the circuit, the element evaluation section operates equivalent to the actual circuit, so correct simulation results can be obtained. Further, the element evaluation section operates independently, and processing is performed at high speed due to the parallelism potentially included in the circuit.

Embodiment FIG. 1 shows a schematic configuration diagram showing an embodiment of the logic simulator according to the present invention. Here, 1 is an element evaluation section, which is assigned to an element in a circuit, and performs logical operations and delay processing of the element. There are a plurality of element evaluation units 1 that perform the following, and each element in the circuit is assigned to each element evaluation unit. However, if the logical operation or delay processing of − number of elements cannot be realized by one element evaluation unit, - elements are assigned to a plurality of element evaluation units to realize an operation equivalent to that of the element. Reference numeral 2 denotes a wiring section that connects between the element evaluation sections 1. Connections between the element evaluation sections 1 are made by the control section 3 according to circuit connection information before execution of the simulation. Before executing the simulation, the control unit 3 defines logical operations for the element evaluation unit 1, delay time for delay processing, wiring for the wiring unit 2, and the like. During simulation execution, the synchronization of delay processing of each element evaluation section 1 is controlled. After the simulation is executed, the current state of the element evaluation section 1 and the results stored during the simulation are read out.

FIG. 2 is a schematic diagram of the element evaluation section 1. As shown in FIG. The arithmetic unit 4 executes logical operations on the elements assigned to the element evaluation unit. This logical operation is a basic logical operation such as AND or OR when the element is a basic gate, a flip-flop such as a D flip-flop or a JK flip-flop when the element is a sequential circuit, and a flip-flop such as a D flip-flop or JK flip-flop when the element is a functional element. Functional logic operations such as memory, adders, and multipliers. The delay unit 5 performs delay processing on the input and output of each element, and can also perform delay processing corresponding to the set-up time and hold time of flip-flops and memory, if necessary.

FIG. 3 is a logic circuit diagram showing an example of a gate level logic circuit. FIG. 4 is a configuration diagram showing an embodiment in which the circuit example shown in FIG. 3 is simulated. In the configuration example shown in FIG. 4, each element evaluation section 1 is composed of an operation section 3 that performs basic logic operations at the gate level and a delay section 5 that realizes output propagation delay of the gate, and the input from the wiring section 2 is It is connected to the calculation section 3, and the output of the calculation section 3 is connected to the output to the wiring section 2 through the delay section 5.

Before running the simulation, for the logic circuit in Figure 3,
The logic operation of each logic gate 6 is assigned to the operation unit 3 of the element evaluation unit 1 in FIG. 4, the delay of each logic gate 6 is assigned to the delay unit 5, and the input to each element evaluation unit is made by the wiring unit 2 according to the circuit connection information. and connect the output. The external input signal lines 10111, 2 and 3 of the logic circuit, and the external output signal line Q are also connected to the control unit 3 through the wiring unit 2. When running the simulation, control l! 3, the external input signal line■
The element evaluation section 1 is operated by changing the values of the signal lines corresponding to 0.11, I2, and I3, and changes in the external signal line Q and, if necessary, the output of each element evaluation section 1 are observed.

In the embodiment shown in FIG. 4, the delay section 5 is provided only on the output side of each gate, but if necessary, the delay section 5 is also provided on the input side.

FIG. 5 shows an embodiment in which a plurality of the embodiments shown in FIG. 1 are used. 7 is a collective element evaluation section consisting of a plurality of element evaluation sections 1 and a wiring section 2, and by connecting a plurality of these spirit-type element evaluation sections 7 with the wiring section 2, it is possible to simulate a circuit including more elements. Realized. In the design of logic circuits, when the circuit scale increases, it is designed hierarchically using subcircuits, so by assigning each subcircuit to the collective element evaluation unit 7, the circuit can be efficiently designed. It is possible to allocate the elements to the element evaluation section. Furthermore, when using the configuration example shown in FIG. 5, it is possible to reduce the scale of the wiring section compared to the configuration example shown in FIG. 1 in which the number of element evaluation sections is increased. It is.

Effects of the Invention As described above, the logic simulator according to the present invention is capable of handling delays for each element, utilizes the parallelism potentially included in the circuit, and realizes high-speed logic simulation. It is possible.

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing an embodiment of a logic simulator according to the present invention, FIG. 2 is a schematic block diagram showing an embodiment of an element evaluation section, and FIG. 3 is an example of a gate-level logic circuit. 4 is a schematic configuration diagram of an embodiment for simulating the circuit example shown in FIG. 3, and FIG. 5 is a hierarchical configuration diagram of the embodiment of FIG. 1. A schematic configuration diagram of an example is shown. 1...Element evaluation section, 2...Wiring section, 3
...Control section, 4...Calculation section, 5...
...Delay section, 6...Logic gate, 7...
...Collective element evaluation section. Name of agent: Patent attorney Toshio Nakao No. 1
A3/ZF3 drawings

Claims (1)

[Claims] A plurality of element evaluation units each including a calculation unit that executes a logical operation and a delay unit that executes a delay, a wiring unit that connects the element evaluation units, and a control that controls the element evaluation unit and the wiring unit. A logic simulator characterized by comprising: