JPH0229145A - Ema trace system - Google Patents

Abstract

PURPOSE:To collect internal information of a processor in the EMA processing effectively by reading the internal information of all processors at that point when the result of detection of an operation fault of a processor reaches a prescribed number of times. CONSTITUTION:An emergency control (EMA) circuit 105 detects an operation fault of plural processors 101-103 applying exchange control to apply each processing such as the system switching from a active system processor to a standby system processor, data initial setting of the new active system processor and restart command. Then in response to the detection of operation fault of the processors 101-103, all processor trace means 111 is provided to a console control circuit 110 to read the internal state, number of times of operation fault detection of the processors 101-103 is counted and when it reaches a prescribed value, restart processing is stopped to all the processors 101-103 to reach the internal information of all the processors 101-103. Thus, the internal information of the processors 101-103 is collected effectively in the EMA processing.

Description

[Detailed Description of the Invention] [Summary] In an electronic switching system where switching is controlled by a plurality of processors, an E
Regarding the MA trace method, the purpose is to enable effective collection of internal information of processors in EMA processing, and detects operational abnormalities of multiple processors that perform exchange control, and detects operational abnormalities in the EMA circuit that performs HMA processing. In an electronic exchange equipped with a console control circuit that reads out the internal state of the processor in response to detection, the console control circuit counts the number of times an operational abnormality is detected, and when the count reaches a predetermined value, a signal is sent to all processors. All processor trace means that stops restart processing and reads internal information of all processors, or counts the number of times a processor malfunction is detected, and reads and holds internal information of a designated processor each time until the count reaches a predetermined value. It is configured with designated processor tracing means.

[Industrial application field]

The present invention relates to an EMA tracing method for detecting operational abnormalities in each processor in an electronic switching system in which switching is controlled by a plurality of processors.

[Conventional technology]

FIG. 6 is a block diagram showing the general configuration of the control system and the monitoring system of the exchange.

In the figure, a plurality of processors 60 including O-system and 1-system basic processors perform basic switching control of the switching equipment.
1 to 603 are accommodated in a basic console unit (BCNS) 605. A console control unit (CNSC) 610 is connected to the basic console unit 605 as a component of a monitoring system, and a monitoring information processing unit 623 is further connected to the basic console unit 605 via a communication control unit (COMC) 621.

In an exchange in which exchange control is performed by a plurality of processors 601 to 603, the active processor (
601), an emergency control (EMA) circuit located in the basic console section 605 of the exchange operates.
An operational abnormality detection signal indicating an abnormality in the processor is sent to the console control unit 610.

The EMA circuit activates restart processing after a predetermined period of time after detecting an abnormality in the processor's operation, and instructs the processor to initialize data and restart from a fixed address. Processes such as reconfiguration and reloading the program into main memory are performed.

On the other hand, the console control unit 610 starts EMA interrupt processing upon receiving the operation abnormality detection signal, and the basic console unit 610 starts EMA interrupt processing.
05 to instruct reading of the internal state of the processor before data initialization.

Note that the series of processes described above will be referred to as "rEMA processing" hereinafter.

FIG. 7 is a flowchart illustrating the flow of conventional HMA processing.

The EMA circuit can be designated as "operating" or "non-operating", and when HMA suppress (non-operating) is designated, abnormal operation of the processor is not detected.

If a processor failure occurs while the EMA circuit is in operation, the basic console section (EMA circuit)
In response to the notification from 605, the console control unit 610 instructs the collection of internal information of the corresponding processor. on the other hand,
The EMA circuit activates restart processing after a predetermined time, initializes the data of the new active processor to which the system has been switched, and instructs restart of processing from a fixed address.

[Problem to be solved by the invention]

In conventional EMA processing, the EMA circuit detects abnormal operation of the processor and instructs the new tax processor to initialize data and restart from a fixed address after a predetermined time. Usually, only the internal information of the corresponding processor at the time of HMA detection is collected.

Incidentally, internal information of a processor is essential in determining the cause of a failure in a processor that performs EMA processing, or in determining the extent to which initial settings should be performed. The information was not necessarily sufficient.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an EMA tracing method that enables effective collection of internal information of a processor in HMA processing in order to address these conventional problems.

[Means to solve the problem] FIG. 1 is a block diagram of the principle of the present invention.

In the figure, an emergency control (EMA) circuit 105 detects an abnormality in the operation of a plurality of processors 101 to 103 that performs switching control, performs system switching from the active processor to the backup processor, and initializes the data of the new active processor. Performs settings and restart instruction processing.

The console control circuit 11O, which reads out the internal state of the processor in response to detection of an operational abnormality in the processor, is provided with all-processor tracing means 111 or designated processor tracing means 113 as a configuration compatible with the EMA I-race method of the present invention.

The all-processor trace means 111 is configured to count the number of abnormal operation detections of processors, and when the number reaches a predetermined value, stop restart processing for all processors and read internal information of all processors.

The designated processor tracing means 113 is configured to count the number of times an abnormal operation of the processor is detected, and each time reads and holds the internal information of the designated processor until the number reaches a predetermined value.

[For production]

The present invention provides a console control circuit for performing EMA processing in response to abnormal operation detection of a processor. By using the all processor tracing means 111 or the designated processor tracing means 113 provided in 10, it is possible to effectively collect internal information of the processor.

That is, the all-processor trace means 111 makes it possible to read the internal information of all the processors when the number of abnormal operation detections of the processors reaches a predetermined value. Further, the designated processor tracing means 113 is configured to be able to collect and accumulate internal information of the designated processor each time until the number of times the tracing reaches a predetermined value.

Therefore, by using each tracing means, EM
It is possible to easily investigate the cause of the failure leading to the A process or obtain initial setting information related to the restart process.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 is a flowchart illustrating the processing flow of the 10 EMA I-race system of the present invention.

The basic configuration of the exchange is the same as that shown in FIG. 6, so the following description will be made with reference to the configuration of each part shown in FIG.

When a processor failure occurs, the basic console section 60
The HMA circuit in the operating state within the controller 5 detects this and sends an operational abnormality detection signal to the console controller 610. The console control unit 610 starts the EMA interrupt process upon receiving this operational abnormality detection signal.

In the EMA interrupt processing, first, the number of occurrences of this EMA interrupt (detection of abnormal operation of the processor) is counted and compared with a predetermined value. Only counting is performed until the number of EMA interruptions reaches a predetermined value.

When the number of occurrences of EMA interrupts reaches a predetermined value, console control unit 610 instructs basic console unit 605 to suppress EMA to all processors 601 to 603,
Next, it instructs all processors to stop operating. As a result, restart processing of the exchange whose operation has been suspended is no longer performed, and subsequent reading of internal information of all processors becomes possible.

By the way, in the basic console unit (EMA circuit) 605, an abnormal operation of the processor is detected and a predetermined period of time (16
ms), data initialization processing of the corresponding processors is performed in parallel. The processor on which this initial setting is performed is usually a basic processor (0 system, 1 system) with a duplex configuration that is in charge of basic exchange control, so before the data is initialized, the basic processor Internal information is read from the processor first. Next, the internal information of other processors is sequentially read out.

Note that the processor restart processing is performed separately after canceling the EMA suppress instruction.

FIG. 3 is a flowchart illustrating the process flow of the second OEMA trace method of the present invention.

The console control unit 610 uses similar EMA interrupt processing to instruct the basic console unit 605 to read internal information of the designated processor.

Here, the read internal information is stored in the memory, and the memory address is updated each time.

Further, the number of occurrences of EMA interrupt (detection of malfunction in processor operation) is counted and compared with a predetermined value. Until the number of occurrences of HMA interrupts reaches a predetermined value, only the internal information of the designated processor is collected, and then data initialization and restart processing of the new active processor are performed under the control of the EMA circuit. .

When the number of occurrences of EMA interrupts reaches a predetermined value, the EMA race ends, and the history of internal information stored in the memory at the time of each operational abnormality detection is read out. Note that the data initialization and restart processing by the EMA circuit continues.

In this manner, the first HMA) race method is capable of reading out the internal information of all processors at that time when a predetermined number of abnormal operations have been detected in the target processor. In addition, the second EMA tracing method detects an operation abnormality of the target processor until it reaches a predetermined number of times.
Internal information read each time is retained, so
It is possible to retrieve the history of internal information of a designated processor, making it possible to compare each internal information.

Note that when starting up the exchange, there are cases where the EMA processing is started intentionally, but it is not necessary to collect the internal information of the processor at that time. Therefore, the first EMA
The trace method 2 method and the designation of the number of times of abnormal operation detection must be set at least from the second time onwards.

FIG. 4 is a block diagram showing the hardware configuration of the console control section (CNSC).

In the figure, a console part interface circuit (CNS IF) 411 that interfaces with the basic console part (BCNS) 405, a control circuit (MPC) 412,
Arithmetic processing circuit (RALU) 413, memory (BM) 41
4 and the communication control unit (COMC) 421 (
The bus interface circuit (IBIF) 415 provides an interface with the IB. Note that the all processor tracing means (111) and the designated processor tracing means (113) of the present invention are realized by program processing of the control circuit 412.

Figure 5 shows the console interface circuit (CNSI
FIG. 3 is a block diagram showing the main part configuration of F).

In the figure, E of the basic console section (Fig. 4, 405)
Receiving ends 501 and 503 of the processor malfunction detection signal sent from the MA circuit correspond to the 0-system and 1-system processors, respectively. This received signal is input to each D flip-flop 521, 523 via drivers 511, 513 and inverters 515, 517. The D flip-flops 521 and 523 output logic "l" signals (EMAO,
EMAI) is sent to each output terminal 525, 527. Upon receiving an operational abnormality detection signal from any of the prefectures, the OR gate 531 sends it to the output terminal 529 as an HMA interrupt signal (EMAI NT).

In the console control section, in response to this EMA interrupt signal,
A process for reading internal information of the corresponding processor is started.

The reset signals (EMAOR, EMAIR) of the 0-system and 1-system EMA interrupt signals are taken into NOR gates 545, 547 via D flip-flops 541, 543, and are logically connected to the initial setting reset signal (NR3T). The sum output resets the D flip-flops 521 and 523 and resets the EMA interrupt signal.

〔Effect of the invention〕

As described above, according to the present invention, in the process of collecting internal information of a processor in which an operational abnormality has been detected, internal information of all processors when an operational abnormality is detected a predetermined number of times, or collected at each detection time. Since the history of the internal information of the specified processor that has been executed can be known, it becomes easy to investigate the cause of failures leading to EMA processing, or to obtain initial setting information related to restart processing, which is extremely useful in practical terms, such as enabling continuous restart. Useful.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the principle of the present invention. FIG. 2 is a flowchart explaining the process flow of the first EMA trace method of the present invention. FIG. 3 is a flow chart of the process of the second OEMA trace method of the present invention. 4 is a block diagram showing the /"t-ware configuration of the console control section (CMSC), and FIG. 5 is a block diagram showing the console section interface circuit (CNSIF).
), FIG. 6 is a block diagram showing the general structure of the control system and monitoring system of the exchange, and FIG. 7 is a flowchart explaining the flow of conventional EMA processing. In the figure, 101 to 103 are processors, 105 is an emergency control (EMA) circuit, 110 is a console control circuit, 111 is all processor tracing means, 113 is designated processor tracing means, 601 to 603
is a processor, 605 is a basic console unit (BCNS), 610 is a console control unit (CNSC), and 621 is a communication control unit (CO
MC), 623 is a monitoring information processing unit.

Claims (2)

[Claims] (1) Multiple processors (101 to 1
Emergency control (03) detects an operational abnormality and performs system switching from the active processor to the standby processor, data initialization of the new active processor, and restart instruction.
EMA) circuit (105); and a console control circuit (110) that reads out the internal state of the processor in response to the detection of the malfunction, wherein the console control circuit (110) is configured to detect the malfunction of the malfunction. All processor trace means (111) that counts the number of times and when it reaches a predetermined value, stops restart processing for all processors and reads internal information of all processors.
) is an EMA tracing method. (2) In the electronic exchange according to claim 1, the console control circuit (110) counts the number of times the abnormal operation of the processor is detected, and each time reads and holds the internal information of the designated processor until the number reaches a predetermined value. An EMA tracing method characterized by comprising a designated processor tracing means (113).